Rainbow Electronics DS1993 User Manual

SPECIAL FEATURES

1993

DS1992/DS1993

www.dalsemi.com

§ 4096 bits of read/write nonvolatile memory

(DS1993 and DS1994)

§ 1024 bits of read/write nonvolatile memory

(DS1992)

§ 256-bit scratchpad ensures integrity of data

transfer

§ Memory partitioned into 256-bit pages for

packetizing data

§ Data integrity assured with strict read/write

protocols

§ Contains real time clock/calendar in binary

format (DS1994)

§ Interval timer can automatically accumulate

time when power is applied (DS1994)

§ Programmable cycle counter can accumulate

the number of system power-on/off cycles
(DS1994)

§ Programmable alarms can be set to generate

interrupts for interval timer, real time clock,
and/or cycle counter (DS1994)

§ Write protect feature provides tamper-proof

time data (DS1994)

§ Programmable expiration date that will limit

access to SRAM and timekeeping (DS1994)

§ Clock accuracy is better than ±2 minute/

month at 25°C (DS1994)

§ Operating temperature range from -40°C to

+70°C

§ Over 10 years of data retention

1kbit/4kbit Memory iButton

DS1994

4-kbit Plus Time Memory iButton

§ Data can be accessed while affixed to object

§ Economically communicates to bus master

with a single digital signal at 16.3k bits per
second

§ Standard 16 mm diameter and 1-Wire

protocol ensure compatibility with iButton
family

§ Button shape is self-aligning with cup-

shaped probes

§ Durable stainless steel case engraved with

registration number withstands harsh
environments

§ Easily affixed with self-stick adhesive

backing, latched by its flange, or locked with
a ring pressed onto its rim

§ Presence detector acknowledges when reader

first applies voltage

§ Meets UL#913 (4th Edit.); Intrinsically Safe

Apparatus, Approved under Entity Concept
for use in Class I, Division 1, Group A, B, C
and D Locations

F5 MICROCAN

5.89

0.36

TM

0.51

YYWW REGISTERED RR

AF

000000FBC52B

c

04

16.25

17.35

TM

TM

COMMON iButton FEATURES

§ Unique, factory-lasered and tested 64-bit

registration number (8-bit family code + 48­bit serial number + 8-bit CRC tester) assures
absolute traceability because no two parts are
alike

§ Multidrop controller for MicroLAN

§ Digital identification and information by

momentary contact

§ Chip–based data carrier compactly stores

information

DATA

GROUND

All diminsions shown in millimeters.

ORDERING INFORMATION

DS1992L-F5 F5 MicroCan
DS1993L-F5 F5 MicroCan
DS1994L-F5 F5 MicroCan

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DS1992/DS1993/DS1994

EXAMPLES OF ACCESSORIES

DS9096P Self-Stick Adhesive Pad
DS9101 Multi-Purpose Clip
DS9093RA Mounting Lock Ring
DS9093F Snap-In Fob
DS9092 iButton Probe

iButton DESCRIPTION

The DS1992/DS1993/DS1994 Memory iButton (hereafter referred to as DS199X) is a rugged read/write
data carrier that acts as a localized database that can be easily accessed with minimal hardware. The
nonvolatile memory and optional timekeeping capability offer a simple solution to storing and retrieving
vital information pertaining to the object to which the iButton is attached. Data is transferred serially via
the 1–Wire protocol which requires only a single data lead and a ground return.

The scratchpad is an additional page that acts as a buffer when writing to memory. Data is first written to
the scratchpad where it can be read back. After the data has been verified, a copy scratchpad command
will transfer the data to memory. This process ensures data integrity when modifying the memory. A 48–
bit serial number is factory lasered into each DS199X to provide a guaranteed unique identity which
allows for absolute traceability. The durable MicroCan package is highly resistant to environmental
hazards such as dirt, moisture, and shock. Its compact coin–shaped profile is self–aligning with mating
receptacles, allowing the DS199X to be easily used by human operators. Accessories permit the DS199X
to be mounted on almost any surface including plastic key fobs, photo–ID badges and printed circuit
boards.

Applications include access control, work–in–progress tracking, electronic travelers, storage of
calibration constants, and debit tokens. With the optional time-keeping functions (DS1994), a real time
clock/calendar, interval timer, cycle counter, and programmable interrupts are available in addition to the
nonvolatile memory. The internal clock can be programmed to deny memory access based on absolute
time/date, total elapsed time, or the number of accesses. These features allow the DS1994 to be used to
create a stopwatch, alarm clock, time and date stamp, logbook, hour meter, calendar, system power cycle
timer, interval timer, and event scheduler.

OPERATION

The DS199X has four main data components: 1) 64-bit lasered ROM, 2) 256-bit scratchpad, 3) 1024–bit
(DS1992) or 4096–bit (DS1993 and DS1994) SRAM, and 4) timekeeping registers (DS1994). The
timekeeping section utilizes an on-chip oscillator that is connected to a 32.768 kHz crystal. The SRAM
and time-keeping registers reside in one contiguous address space referred to hereafter as memory. All
data is read and written least significant bit first.

The memory functions will not be available until the ROM function protocol has been established. This
protocol is described in the ROM functions flow chart (Figure 9). The master must first provide one of
four ROM function commands: 1) read ROM, 2) match ROM, 3) search ROM, or 4) skip ROM. After a
ROM function sequence has been successfully executed, the memory functions are accessible and the
master may then provide any one of the four memory function commands (Figure 6).

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DS1992/DS1993/DS1994

DS199X BLOCK DIAGRAM Figure 1

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DS1992/DS1993/DS1994

PARASITE POWER

The block diagram (Figure 1) shows the parasite-powered circuitry. This circuitry “steals” power
whenever the data input is high. The data line will provide sufficient power as long as the specified
timing and voltage requirements are met. The advantages of parasite power are two-fold: 1) by parasiting
off this input, lithium is conserved and 2) if the lithium is exhausted for any reason, the ROM may still be
read normally.

64-BIT LASERED ROM

Each DS199X contains a unique ROM code that is 64 bits long. The first eight bits are a 1-Wire family
code. The next 48 bits are a unique serial number. The last eight bits are a CRC of the first 56 bits. (See
Figure 2.) The 1-wire CRC is generated using a polynomial generator consisting of a shift register and
XOR gates as shown in Figure 3. The polynomial is X

8

+ X5 + X4 + 1. Additional information about the

Dallas 1-Wire Cyclic Redundancy Check is available in the Book of DS19xx iButton Standards. The shift
register bits are initialized to zero. Then starting with the least significant bit of the family code, one bit at
a time is shifted in. After the 8th bit of the family code has been entered, then the serial number is
entered. After the 48th bit of the serial number has been entered, the shift register contains the CRC
value. Shifting in the eight bits of CRC should return the shift register to all zeros.

64-BIT LASERED ROM Figure 2

FAMILY
CODE

SERIAL
NUMBER

CRC 8 BITS

1-WIRE CRC CODE Figure 3

04h = DS1994
06h = DS1993
08h = DS1992

48-BIT

UNIQUE

NUMBER

LSB

MSB

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DS1992/DS1993/DS1994

DS1994 MEMORY MAP Figure 4a

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DS1992/DS1993/DS1994

DS1993 MEMORY MAP Figure 4b

DS1992 MEMORY MAP Figure 4c

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DS1992/DS1993/DS1994

MEMORY

The memory map in Figure 4 shows a 32–byte page called the scratchpad and additional 32–byte pages
called memory. The DS1992 contains pages 0 though 3 which make up the 1024–bit SRAM. The
DS1993 and DS1994 contain pages 0 through 15 which make up the 4096–bit SRAM. The DS1994 also
contains page 16 which has only 30 bytes that contain the timekeeping registers.

The scratchpad is an additional page that acts as a buffer when writing to memory. Data is first written to
the scratchpad where it can be read back. After the data has been verified, a copy scratchpad command
will transfer the data to memory. This process ensures data integrity when modifying the memory.

TIMEKEEPING (DS1994)

A 32.768 kHz crystal oscillator is used as the time base for the timekeeping functions. The oscillator can
be turned on or off by an enable bit in the control register. The oscillator must be on for the real time
clock, interval timer and cycle counter to function.

The timekeeping functions are double buffered. This feature allows the master to read time or count
without the data changing while it is being read. To accomplish this, a snapshot of the counter data is
transferred to holding registers which the user accesses. This occurs after the eighth bit of the Read
Memory Function command.

Real-Time Clock

The real-time clock is a 5-byte binary counter. It is incremented 256 times per second. The least
significant byte is a count of fractional seconds. The upper four bytes are a count of seconds. The real­time clock can accumulate 136 years of seconds before rolling over. Time/date is represented by the
number of seconds since a reference point which is determined by the user. For example, 12:00 A.M.,
January 1, 1970 could be a reference point.

Interval Timer

The interval timer is a 5-byte binary counter. When enabled, it is incremented 256 times per second. The
least significant byte is a count of fractional seconds. The interval timer can accumulate 136 years of
seconds before rolling over. The interval timer has two modes of operation which are selected by the
AUTO/MAN bit in the control register. In the auto mode, the interval timer will begin counting after the
data line has been high for a period of time determined by the DSEL bit in the control register. Similarly,
the interval timer will stop counting after the data line has been low for a period of time determined by
the DSEL bit. In the manual mode, time accumulation is controlled by the STOP/START bit in the
control register.

NOTE: For auto mode operation, the high level on the data line must be greater than or equal to 2.1 volts.

Cycle Counter

The cycle counter is a 4-byte binary counter. It increments after the falling edge of the data line if the
appropriate data line timing has been met. This timing is selected by the DSEL bit in the control register.
(See “Status/Control” section).

NOTE: For cycle counter operation, the high level on the data line must be greater than or equal to 2.1
volts.

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