Rainbow Electronics DS1985 User Manual

SPECIAL FEATURES

www.dalsemi.com

1993

YYWW REGISTERED RR

1993

§ 16384 bits Electrically Programmable Read

Only Memory (EPROM) communicates with
the economy of one signal plus ground

§ EPROM partitioned into sixty-four 256-bit

pages for randomly accessing packetized
data records

§ Each memory page can be permanently

write-protected to prevent tampering

§ Device is an “add only” memory where

additional data can be programmed into
EPROM without disturbing existing data

§ Architecture allows software to patch data by

superseding an old page in favor of a newly
programmed page

§ Reduces control, address, data, power, and

programming signals to a single data pin

§ 8-bit family code specifies DS1985

communications requirements to reader

§ Reads over a wide voltage range of 2.8V to

6.0V from -40°C to +85°C; programs at

11.5V to 12.0V from -40°C to +85°C

COMMON iButton FEATURES

§ Unique, factory-lasered and tested 64-bit

registration number (8-bit family code + 48­bit serial number + 8-bit CRC tester) assures
absolute traceability because no two parts are
alike

DS1985

16-kbit Add-Only iButton

TM

§ Multidrop controller for MicroLAN

§ Digital identification and information by

momentary contact

§ Chip-based data carrier compactly stores

information

§ Data can be accessed while affixed to object

§ Economically communicates to bus master

with a single digital signal at 16.3k bits per
second

§ Standard 16 mm diameter and 1-Wire

protocol ensure compatibility with iButton
family

§ Button shape is self-aligning with cup-

shaped probes

§ Durable stainless steel case engraved with

registration number withstands harsh
environments

§ Easily affixed with self-stick adhesive

backing, latched by its flange, or locked with
a ring pressed onto its rim

§ Presence detector acknowledges when reader

first applies voltage

§ Meets UL#913 (4th Edit.); Intrinsically Safe

Apparatus, Approved under Entity Concept
for use in Class I, Division 1, Group A, B, C
and D Locations (application pending)

TM

F3 MICROCAN

0.36

DATA

GROUND

1 of 25 090299

3.10

0.51

ED

000000FBC52B

TM

F5 MICROCAN

5.89

0.36

c

0B

16.25

17.35

DATA

GROUND

All dimensions shown in millimeters.

0.51

YYWW REGISTERED RR

6D

000000FBD8B3

TM

c

0B

16.25

17.35

DS1985

ORDERING INFORMATION

DS1985-F3 F3 MicroCan
DS1985-F5 F5 MicroCan

EXAMPLES OF ACCESSORIES

DS9096P Self-Stick Adhesive Pad
DS9101 Multi-Purpose Clip
DS9093RA Mounting Lock Ring
DS9093F Snap-In Fob
DS9092 iButton Probe

iButton DESCRIPTION

The DS1985 16-kbit Add-Only iButton is a rugged read/write data carrier that identifies and stores
relevant information about the product or person to which it is attached. This information can be accessed
with minimal hardware, for example a single port pin of a microcontroller.The DS1985 consists of a
factory-lasered registration number that includes a unique 48-bit serial number, an 8-bit CRC, and an 8­bit Family Code (0BH) plus 16k bit of EPROM which is user-programmable. The power to program and
read the DS1985 is derived entirely from the 1-Wire communication line. Data is transferred serially via
the 1-Wire protocol which requires only a single data lead and a ground return. The entire device can be
programmed and then write-protected if desired. Alternatively, the part may be programmed multiple
times with new data being appended to, but not overwriting, existing data with each subsequent
programming of the device. Note: Individual bits can be changed only from a logical 1 to a logical 0,
never from a logical 0 to a logical 1. A provision is also included for indicating that a certain page or
pages of data are no longer valid and have been replaced with new or updated data that is now residing at
an alternate page address. This page address redirection allows software to patch data and enhance the
flexibility of the device as a standalone database. The 48-bit serial number that is factory-lasered into
each DS1985 provides a guaranteed unique identity which allows for absolute traceability. The durable
MicroCan package is highly resistant to harsh environments such as dirt, moisture, and shock. Its compact
button-shaped profile is self-aligning with cup-shaped receptacles, allowing the DS1985 to be used easily
by human operators or automatic equipment. Accessories permit the DS1985 to be mounted on printed
circuit boards, plastic key fobs, photo-ID badges, ID bracelets, and many other objects. Applications
include work-in-progress tracking, electronic travelers, access control, storage of calibration constants,
and debit tokens.

OVERVIEW

The block diagram in Figure 1 shows the relationships between the major control and memory sections of
the DS1985. The DS1985 has three main data components: 1) 64-bit lasered ROM, 2) 16384-bits
EPROM Data Memory, and 3) 704-bits EPROM Status Memory. The device derives its power for read
operations entirely from the 1-Wire communication line by storing energy on an internal capacitor during
periods of time when the signal line is high and continues to operate off of this “parasite” power source
during the low times of the 1-Wire line until it returns high to replenish the parasite (capacitor) supply.
During programming, 1-Wire communication occurs at normal voltage levels and then is pulsed
momentarily to the programming voltage to cause the selected EPROM bits to be programmed. The 1­Wire line must be able to provide 12 volts and 10 milliamperes to adequately program the EPROM
portions of the part. Whenever programming voltages are present on the 1-Wire line a special high
voltage detect circuit within the DS1985 generates an internal logic signal to indicate this condition. The
hierarchical structure of the 1-Wire protocol is shown in Figure 2. The bus master must first provide one
of the four ROM Function Commands, 1) Read ROM, 2) Match ROM, 3) Search ROM, 4) Skip ROM.
These commands operate on the 64-bit lasered ROM portion of each device and can singulate a specific
device if many are present on the 1-Wire line as well as indicate to the bus master how many and what
types of devices are present. The protocol required for these ROM Function Commands is described in
Figure 8. After a ROM Function Command is successfully executed, the memory functions that operate
on the EPROM portions of the DS1985 become accessible and the bus master may issue any one of the

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DS1985

Figure 8. After a ROM Function Command is successfully executed, the memory functions that operate
on the EPROM portions of the DS1985 become accessible and the bus master may issue any one of the
five Memory Function Commands specific to the DS1985 to read or program the various data fields. The
protocol for these Memory Function Commands is described in Figure 5. All data is read and written least
significant bit first.

DS1985 BLOCK DIAGRAM Figure 1

64-BIT LASERED ROM

Each DS1985 contains a unique ROM code that is 64 bits long. The first 8 bits are a 1-Wire family code.
The next 48 bits are a unique serial number. The last 8 bits are a CRC of the first 56 bits. (See Figure 3.)
The 64-bit ROM and ROM Function Control section allow the DS1985 to operate as a 1-Wire device and
follow the 1-Wire protocol detailed in the section “1-Wire Bus System.” The memory functions required
to read and program the EPROM sections of the DS1985 are not accessible until the ROM function
protocol has been satisfied. This protocol is described in the ROM functions flow chart (Figure 8). The 1­Wire bus master must first provide one of four ROM function commands: 1) Read ROM, 2) Match ROM,

3) Search ROM, or 4) Skip ROM. After a ROM function sequence has been successfully executed, the
bus master may then provide any one of the memory function commands specific to the DS1985 (Figure

5).

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DS1985

The 1-Wire CRC of the lasered ROM is generated using the polynomial X8 + X5 + X4 + 1. Additional
information about the Dallas Semiconductor 1-Wire Cyclic Redundancy Check is available in the Book
of DS19xx iButton Standards. The shift register acting as the CRC accumulator is initialized to 0. Then
starting with the least significant bit of the family code, one bit at a time is shifted in. After the 8th bit of
the family code has been entered, then the serial number is entered. After the 48th bit of the serial number
has been entered, the shift register contains the CRC value. Shifting in the 8 bits of CRC should return the
shift register to all 0s.

HIERARCHICAL STRUCTURE FOR 1-WIRE PROTOCOL Figure 2

64-BIT LASERED ROM Figure 3

8-Bit CRC Code 48- Bit Serial Number 8-Bit Family Code (0BH)

MSB LSB MSB LSB MSB LSB

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DS1985

16384 BITS EPROM

The memory map in Figure 4 shows the 16384 bits EPROM section of the DS1985 which is configured
as 64 pages of 32 bytes each. The 8-bit scratchpad is an additional register that acts as a buffer when
programming the memory. Data is first written to the scratchpad and then verified by reading a 16-bit
CRC from the DS1985 that confirms proper receipt of the data and address. If the buffer contents are
correct, a programming voltage should be applied and the byte of data will be written into the selected
address in memory. This process ensures data integrity when programming the memory. The details for
reading and programming the 16384 bits EPROM portion of the DS1985 are given in the Memory
Function Commands section.

EPROM STATUS BYTES

In addition to the 16384 bits of data memory the DS1985 provides 704 bits of Status Memory accessible
with separate commands.

The EPROM Status Bytes can be read or programmed to indicate various conditions to the software
interrogating the DS1985. The first 8 bytes of the EPROM Status Memory (addresses 000 to 007H)
contain the Write Protect Page bits which inhibit programming of the corresponding page in the 16384-bit
main memory area if the appropriate write protection bit is programmed. Once a bit has been
programmed in the Write Protect Page section of the Status Memory, the entire 32-byte page that
corresponds to that bit can no longer be altered but may still be read.

The next 8 bytes of the EPROM Status Memory (addresses 020 to 027H) contain the Write Protect bits
which inhibit altering the Page Address Redirection Byte corresponding to each page in the 16384-bit
main memory area.

The following 8 bytes within the EPROM Status Memory (addresses 040 to 047H) are reserved for use
by the iButton operating software TMEX. Their purpose is to indicate which memory pages are already in
use. Originally, all of these bits are unprogrammed, indicating that the device does not store any data. As
soon as data is written to any page of the device under control of TMEX, the bit inside this bitmap
corresponding to that page will be programmed to 0, marking this page as used. These bits are application
flags only and have no impact on the internal logic of the DS1985.

The next 64 bytes of the EPROM Status Memory (addresses 100H to 13FH) contain the Page Address
Redirection Bytes which indicate if one or more of the pages of data in the 16384 bits EPROM section
have been invalidated by software and redirected to the page address contained in the appropriate
redirection byte. The hardware of the DS1985 makes no decisions based on the contents of the Page
Address Redirection Bytes. These additional bytes of Status EPROM allow for the redirection of an entire
page to another page address, indicating that the data in the original page is no longer considered relevant
or valid. With EPROM technology, bits within a page can be changed from a logical 1 to a logical 0 by
programming, but cannot be changed back. Therefore, it is not possible to simply rewrite a page if the
data requires changing or updating, but with space permitting, an entire page of data can be redirected to
another page within the DS1985 by writing the one’s complement of the new page address into the Page
Address Redirection Byte that corresponds to the original (replaced) page.

This architecture allows the user’s software to make a “data patch” to the EPROM by indicating that a
particular page or pages should be replaced with those indicated in the Page Address Redirection Bytes.
To leave an authentic audit trail of data patches, it is recommended to also program the write protect bit
of the Page Address Redirection Byte, after the page redirection is programmed. Without this protection,
it is still possible to modify the Page Address Redirection Byte, making it point to a different memory
page than the true one.

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DS1985

SCRATCHPAD

If a Page Address Redirection Byte has a FFH value, the data in the main memory that corresponds to that
page is valid. If a Page Address Redirection Byte has some other hex value, the data in the page
corresponding to that redirection byte is invalid, and the valid data can now be found at the one’s
complement of the page address indicated by the hex value stored in the associated Page Address
Redirection Byte. A value of FDH in the redirection byte for page 1, for example, would indicate that the
updated data is now in page 2. The details for reading and programming the EPROM status memory
portion of the DS1985 are given in the Memory Function Commands section.

DS 1985 MEMORY MAP Figure 4

8-BIT

88 BYTES
STATUS MEMORY

REDIRECTION
BYTES

BIT MAP OF
USED PAGES

STATUS MEMORY MAP

WRITE-PROTECT BITS
REDIRECTION BYTES

WRITE-PROTECT BITS
DATA MEMORY

BIT 0 OF ADDRESS 000H=

WRITE PROTECT

OF PAGE 0, ETC.

ADDRESS 100H=PAGE ADDRESS

REDIRECTION BYTE FOR PAGE 0, ETC.

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DS1985

The Status Memory address range of the DS1985 extends from 000 to 13FH. The memory locations
008H to 01FH, 028H to 03FH, 048H to 0FFH and 140H to 7FFH are physically not implemented.
Reading these locations will usually result in FFH bytes. Attempts to write to these locations will be
ignored. If the bus master sends a starting address higher than 7FFH, the five most significant address bits
are set to 0s by the internal circuitry of the chip. This will result in a mismatch between the CRC
calculated by the DS1985 and the CRC calculated by the bus master, indicating an error condition.

MEMORY FUNCTION COMMANDS

The “Memory Function Flow Chart” (Figure 5) describes the protocols necessary for accessing the
various data fields within the DS1985. The Memory Function Control section, 8-bit scratchpad, and the
Program Voltage Detect circuit combine to interpret the commands issued by the bus master and create
the correct control signals within the device. A 3-byte protocol is issued by the bus master. It is comprised
of a command byte to determine the type of operation and two address bytes to determine the specific
starting byte location within a data field. The command byte indicates if the device is to be read or
written. Writing data involves not only issuing the correct command sequence but also providing a 12V
programming voltage at the appropriate times. To execute a write sequence, a byte of data is first loaded
into the scratchpad and then programmed into the selected address. Write sequences always occur a byte
at a time. To execute a read sequence, the starting address is issued by the bus master and data is read
from the part beginning at that initial location and continuing to the end of the selected data field or until
a reset sequence is issued. All bits transferred to the DS1985 and received back by the bus master are sent
least significant bit first.

READ MEMORY [F0H]

The Read Memory command is used to read data from the 16384-bits EPROM data field. The bus master
follows the command byte with a two byte address (TA1=(T7:T0), TA2=(T15:T8)) that indicates a
starting byte location within the data field. With every subsequent read data time slot the bus master
receives data from the DS1985 starting at the initial address and continuing until the end of the 16384-bits
data field is reached or until a Reset Pulse is issued. If reading occurs through the end of memory space,
the bus master may issue sixteen additional read time slots and the DS1985 will respond with a 16-bit
CRC of the command, address bytes and all data bytes read from the initial starting byte through the last
byte of memory. This CRC is the result of clearing the CRC generator and then shifting in the command
byte followed by the two address bytes and the data bytes beginning at the first addressed memory
location and continuing through to the last byte of the EPROM data memory. After the CRC is received
by the bus master, any subsequent read time slots will appear as logical 1s until a Reset Pulse is issued.
Any reads ended by a Reset Pulse prior to reaching the end of memory will not have the 16-bit CRC
available.

Typically a 16-bit CRC would be stored with each page of data to ensure rapid, error-free data transfers
that eliminate having to read a page multiple times to determine if the received data is correct or not. (See
Book of DS19xx iButton Standards, Chapter 7 for the recommended file structure to be used with the 1­Wire environment.) If CRC values are imbedded within the data, a Reset Pulse may be issued at the end
of memory space during a Read Memory command.

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DS1985

READ STATUS [AAH]

The Read Status command is used to read data from the EPROM Status data field. The bus master
follows the command byte with a 2-byte address (TA1=(T7:T0), TA2=(T15:T8)) that indicates a starting
byte location within the data field. With every subsequent read data time slot the bus master receives data
from the DS1985 starting at the supplied address and continuing until the end of an 8-byte page of the
EPROM Status data field is reached. At that point the bus master will receive a 16-bit CRC of the
command byte, address bytes and status data bytes. This CRC is computed by the DS1985 and read back
by the bus master to check if the command word, starting address and data were received correctly. If the
CRC read by the bus master is incorrect, a Reset Pulse must be issued and the entire sequence must be
repeated.

Note that the initial pass through the Read Status flow chart will generate a 16-bit CRC value that is the
result of clearing the CRC generator and then shifting in the command byte followed by the two address
bytes, and finally the data bytes beginning at the first addressed memory location and continuing through
to the last byte of the addressed EPROM Status data page. The last byte of a Status data page always has
an ending address of xx7 or xxFH. Subsequent passes through the Read Status flow chart will generate a
16-bit CRC that is the result of clearing the CRC generator and then shifting in the new data bytes starting
at the first byte of the next page of the EPROM Status data field.

This feature is provided since the EPROM Status information may change over time making it impossible
to program the data once and include an accompanying CRC that will always be valid. Therefore, the
Read Status command supplies a 16-bit CRC that is based on and always is consistent with the current
data stored in the EPROM Status data field.

After the 16-bit CRC of the last EPROM Status data page is read, the bus master will receive logical 1s
from the DS1985 until a Reset Pulse is issued. The Read Status command sequence can be ended at any
point by issuing a Reset Pulse.

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