Rainbow Electronics DS1972 User Manual

www.maxim-ic.com

Button DESCRIPTION

The DS1972 is a 1024-bit, 1-Wire® EEPROM organized as four memory pages of 256 bits each in a rugged i byte scratchpad, verified, and then copied to the EEPROM memory. As a special feature, the four memory pages can individually be write protected or put in EPROM-emulation mode, where bits can only be changed from a 1 to a 0 state. The DS1972 communicates over the single-conductor 1-Wire bus. The communication follows the standard Dallas Semiconductor 1-Wire protocol. Each device has its own unalterable and unique 64-bit ROM registration number that is factory lasered into the device. The registration number is used to address the device in a multidrop 1-Wire net environment.

Button package. Data is written to an 8-

APPLICATIONS

Access Control/Parking Meter Work-In-Progress Tracking Tool Management Inventory Control Maintenance/Inspection Data Storage

F5 AND F3 MicroCAN

F3 size F5 size Branding

0.51

5.89

GND

0.51

51 2D

0000006234FB

1-Wire

16.25

17.35

3.10

IO GND

Commands, Registers, and Modes are capitalized for clarity.

Button, 1-Wire, and MicroCAN are registered trademarks of Dallas

I Semiconductor Corp.

DS1972

1024-Bit EEPROM i

SPECIAL FEATURES

§ 1024 Bits of EEPROM Memory Partitioned into

Four Pages of 256 Bits

§ Individual Memory Pages can be Permanently

Write Protected or Put in EPROM-Emulation Mode ("Write to 0")

§ Switchpoint Hysteresis and Filtering to Optimize

Performance in the Presence of Noise

§ IEC 1000-4-2 Level 4 ESD Protection (8kV

Contact, 15kV Air, typical)

§ Reads and Writes Over a Wide Voltage Range of

2.8V to 5.25V from -40°C to +85°C

§ Communicates to Host with a Single Digital

Signal at 15.4kbps or 125kbps Using 1-Wire Protocol

COMMON iButton FEATURES

§ Unique Factory-Lasered 64-Bit Registration Number Assures Error-Free Device Selection and Absolute Traceability Because No Two Parts are Alike

§ Built-In Multidrop Controller for 1-Wire Net

§ Chip-Based Data Carrier Stores Digital Identifi-

cation and Information, Armored in a Durable Stainless-Steel Case

§ Data can be Accessed While Affixed to Object

§ Button Shape is Self-Aligning with Cup-Shaped

Probes

§ Easily Affixed with Self-Stick Adhesive Backing, Latched by its Flange, or Locked with a Ring Pressed onto its Rim

§ Presence Detector Acknowledges when Reader First Applies Voltage

§ Designed to meet UL#913 (4th Edit.); Intrinsically Safe Apparatus: Under Entity Concept for use in Class I, Division 1, Group A, B, C, and D Locations, contact Dallas Semiconductor for certification schedule

ORDERING INFORMATION

PART TEMP RANGE PIN-PACKAGE

DS1972-F5# -40°C to 85°C F5 iButton DS1972-F3# -40°C to 85°C F3 iButton

# indicates RoHS complience Contact factory lead-free compliance

Button

Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata

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DS1972: 1024-Bit EEPROM iButton

ABSOLUTE MAXIMUM RATINGS

I/O Voltage to GND -0.5V, +6V I/O Sink Current 20mA Operating Temperature Range -40°C to +85°C Junction Temperature +150°C Storage Temperature Range -40°C to +85°C

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS

(TA = -40°C to +85°C; see Note 1.)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

I/O PIN GENERAL DATA

1-Wire Pullup Voltage V 1-Wire Pullup Resistance

PUP

(Notes 2) 2.8 5.25 V

(Notes 2, 3) Input Capacitance CIO (Notes 4, 5) 1000 pF Input Load Current I High-to-Low Switching

Threshold Input Low Voltage V Low-to-High Switching Threshold Switching Hysteresis V Output Low Voltage V

Recovery Time (Notes 2,12)

(Notes 5, 13)

(Note 2, 14)

REC

REH

SLOT

I/O pin at V

0.05 6.7 µA

PUP

(Notes 5, 6, 7) 0.46 4.4 V

(Notes 2, 8) 0.3 V

(Notes 5, 6, 9) 1.0 4.9 V

(Notes 5, 6, 10) 0.21 1.70 V

At 4mA (Note 11)

Standard speed, R

Overdrive speed, R

PUP

= 2.2kW

= 2.2kW Overdrive speed, directly prior to Reset Pulse; R

PUP

= 2.2kW Standard speed 0.5 5.0 Rising-Edge Hold-off Time Overdrive speed Not applicable (0) Standard speed 65 Timeslot Duration Overdrive speed 8

I/O PIN, 1-WIRE RESET, PRESENCE DETECT CYCLE

Reset Low Time (Note 2) t

Presence Detect High Time

Presence Detect Low Time

Presence Detect Sample Time (Notes 2, 15)

RSTL

PDH

PDL

MSP

Standard speed 480 640 Overdrive speed 48 80 Standard speed 15 60

Overdrive speed 2 6 Standard speed 60 240

Overdrive speed 8 24 Standard speed 60 75

Overdrive speed 6 10

I/O PIN, 1-Wire WRITE

Write-0 Low Time (Notes 2, 16)

Write-1 Low Time (Notes 2, 17)

W0L

W1L

Standard speed 60 120 Overdrive speed, V

> 4.5V 5 15.5

PUP

Overdrive speed 6 15.5 Standard speed 1 Overdrive speed 1

I/O PIN, 1-Wire READ

Read Low Time (Notes 2, 18)

Read Sample Time (Notes 2, 18)

MSR

Standard speed 5 Overdrive speed 1 Standard speed Overdrive speed

0.3 2.2

0.4 V

5 2

µs

15 - e

2 - e

µs

15 - d

2 - d

+ d

15 2

µs

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DS1972: 1024-Bit EEPROM iButton

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

EEPROM

Programming Current I

Programming Time t

durance) (Notes 21, 22) Data Retention

(Notes 23, 24)

Note 1: Note 2: Note 3:

Note 4:

Note 5: Note 6:

Note 7: Note 8: Note 9: Note 10: Note 11: Note 12: Note 13: Note 14: Note 15:

Note 16: Note 17: Note 18:

Note 19:

Note 20:

Note 21: Note 22: Note 23: Note 24:

Specifications at T

= -40°C are guaranteed by design only and not production-tested.

System requirement. Maximum allowable pullup resistance is a function of the number of 1-Wire devices in the system and 1-Wire recovery times. The specified value here applies to systems with only one device and with the minimum 1-Wire recovery times. For more heavily loaded systems, an active pullup such as that found in the DS2482-x00, DS2480B, or DS2490 may be required. Maximum value represents the internal parasite capacitance when V data line, 2.5µs after V Guaranteed by design, characterization and/or simulation only. Not production tested.

, VTH, and V

are a function of the internal supply voltage which is itself a function of V

capacitive loading on IO. Lower V and V

Voltage below which, during a falling edge on IO, a logic 0 is detected. The voltage on IO needs to be less or equal to V Voltage above which, during a rising edge on IO, a logic 1 is detected. After V

is crossed during a rising edge on IO, the voltage on IO has to drop by at least VHY to be detected as logic '0'.

The I-V characteristic is linear for voltages less than 1V. Applies to a single device attached to a 1-Wire line. The earliest recognition of a negative edge is possible at t Defines maximum possible bit rate. Equal to t Interval after t is t

PDH(max)

during which a bus master is guaranteed to sample a logic-0 on IO if there is a DS1972 present. Minimum limit

RSTL

; maximum limit is t

Highlighted numbers are NOT in compliance with legacy 1-Wire product standards. See comparison table below.

e represents the time required for the pullup circuitry to pull the voltage on IO up from V d represents the time required for the pullup circuitry to pull the voltage on IO up from V

master. Current drawn from IO during the EEPROM programming interval. The pullup circuit on IO during the programming interval should be such that the voltage at IO is greater than or equal to Vpup(min). If Vpup in the system is close to Vpup(min) then a low impedance bypass of Rpup which can be activated during programming may need to be added. Interval begins t

WiLMIN

sequence. Interval ends once the device's self-timed EEPROM programming cycle is complete and the current drawn by the device has returned from I Write-cycle endurance is degraded as T Not 100% production-tested; guaranteed by reliability monitor sampling. Data retention is degraded as T Guaranteed by 100% production test at elevated temperature for a shorter time; equivalence of this production test to data sheet limit at operating temperature range is established by reliability testing.

PROG

has been applied the parasite capacitance will not affect normal communications.

PUP

PDH(min)

(Note 5, 19) 0.8 mA

(Note 20) 10 ms At 25°C 200k Write/Erase Cycles (EnAt 85°C (worst case) 50k

At 85°C (worst case) 10

is first applied. If a 2.2kW resistor is used to pull up the

PUP

, higher R

PUP

+ t

PDL(min)

W0L(min)

, shorter t

PUP

IL(MAX)

+ t

, and heavier capacitive loading all lead to lower values of VTL, VTH,

REC

at all times the master is driving IO to a logic-0 level.

after VTH has been reached on the preceding rising edge.

REH

REC(min)

after the leading negative edge on IO for the last timeslot of the E/S byte for a valid Copy Scratchpad

to IL.

PROG

increases.

---

, R

PUP

to VTH.

to the input high threshold of the bus

, 1-Wire timing, and

PUP

years

LEGACY VALUES DS1972 VALUES

PARAMETER STANDARD SPEED OVERDRIVE SPEED STANDARD SPEED OVERDRIVE SPEED

MIN MAX MIN MAX MIN MAX MIN MAX

(incl. t

SLOT

RSTL

PDH

PDL

W0L

Intentional change, longer recovery time requirement due to modified 1-Wire front end.

REC)

61µs (undef.) 7µs (undef.) 65µs1) (undef.) 8µs1) (undef.)

480µs (undef.) 48µs 80µs 480µs 640µs 48µs 80µs

15µs 60µs 2µs 6µs 15µs 60µs 2µs 6µs 60µs 240µs 8µs 24µs 60µs 240µs 8µs 24µs 60µs 120µs 6µs 16µs 60µs 120µs 6µs 15.5µs

EXAMPLES OF ACCESSORIES

PART DESCRIPTION

DS9096P Self-Stick Adhesive Pad DS9101 Multipurpose Clip DS9093RA Mounting Lock Ring DS9093A Snap-In Fob DS9092 iButton Probe

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DS1972: 1024-Bit EEPROM iButton

DESCRIPTION

The DS1972 combines 1024 bits of EEPROM, an 8-byte register/control page with up to 7 user read/write bytes, and a fully-featured 1-Wire interface in a rugged i registration number that is factory lasered to provide a guaranteed unique identity for absolute traceability. Data is transferred serially via the 1-Wire protocol, which requires only a single data contact and a ground return. The DS1972 has an additional memory area called the scratchpad that acts as a buffer when writing to the main memory or the register page. Data is first written to the scratchpad from which it can be read back. After the data has been verified, a Copy Scratchpad command transfers the data to its final memory location. Applications of the DS1972 include access control/parking meter, Work-In-Progress tracking, tool management, inventory control, and maintenance/inspection data storage. Software for communication with the DS1972 is available for free download from the http://www.maxim-ic.com/products/ibutton/ website.

Button package. Each DS1972 has its own 64-bit ROM

OVERVIEW

The block diagram in Figure 1 shows the relationships between the major control and memory sections of the DS1972. The DS1972 has four main data components: 1) 64-bit lasered ROM, 2) 64-bit scratchpad, 3) four 32-byte pages of EEPROM, and 4) 64-bit register page. The hierarchical structure of the 1-Wire protocol is shown in Figure

2. The bus master must first provide one of the seven ROM Function Commands, 1) Read ROM, 2) Match ROM, 3) Search ROM, 4) Skip ROM, 5) Resume, 6) Overdrive-Skip ROM or 7) Overdrive-Match ROM. Upon completion of an Overdrive ROM command byte executed at standard speed, the device enters Overdrive mode where all subsequent communication occurs at a higher speed. The protocol required for these ROM function commands is described in Figure 9. After a ROM function command is successfully executed, the memory functions become accessible and the master may provide any one of the four memory function commands. The protocol for these memory function commands is described in Figure 7. All data is read and written least significant bit first.

Figure 1. Block Diagram

PARASITE POWER

I/O

Memory

Function

Control Unit

CRC16

Generator

Data Memory

4 Pages of

256 bits each

64 bits

1-Wire

Function Control

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64-bit

Lasered ROM

DS1972

64-bit

Scratchpad

Figure 2. Hierarchical Structure for 1-Wire Protocol

DS1972 Command Level:

1-Wire ROM Function

Commands (see Figure 9)

vailable

Commands:

Read ROM Match ROM Search ROM Skip ROM Resume Overdrive-Skip Overdrive-Match

DS1972: 1024-Bit EEPROM iButton

Data Field

ffected:

64-bit Reg. #, RC-Flag 64-bit Reg. #, RC-Flag 64-bit Reg. #, RC-Flag RC-Flag RC-Flag RC-Flag, OD-Flag 64-bit Reg. #, RC-Flag, OD-Flag

DS1972-specific

Memory Function

Commands (see Figure 7)

Write Scratchpad Read Scratchpad Copy Scratchpad Read Memory

64-bit Scratchpad, Flags 64-bit Scratchpad Data Memory, Register Page Data Memory, Register Page

64-BIT LASERED ROM

Each DS1972 contains a unique ROM code that is 64 bits long. The first 8 bits are a 1-Wire family code. The next 48 bits are a unique serial number. The last 8 bits are a CRC (Cyclic Redundancy Check) of the first 56 bits. See Figure 3 for details. The 1-Wire CRC is generated using a polynomial generator consisting of a shift register and XOR gates as shown in Figure 4. The polynomial is X CRC is available in Application Note 27.

The shift register bits are initialized to 0. Then starting with the least significant bit of the family code, one bit at a time is shifted in. After the 8th bit of the family code has been entered, then the serial number is entered. After the last bit of the serial number has been entered, the shift register contains the CRC value. Shifting in the 8 bits of the CRC returns the shift register to all 0s.

Figure 3. 64-Bit Lasered ROM

MSB LSB

8-Bit

CRC Code

MSB LSB MSB LSB MSB LSB

Figure 4. 1-Wire CRC Generator

Polynomial = X8 + X5 + X4 + 1

+ X5 + X4 + 1. Additional information about the Dallas 1-Wire

48-Bit Serial Number

8-Bit Family Code (2Dh)

STAGE

INPUT DATA

STAGE

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DS1972: 1024-Bit EEPROM iButton

Figure 5. Memory Map

ADDRESS RANGE TYPE DESCRIPTION PROTECTION CODES

0000h to 001Fh R/(W) Data Memory Page 0

0020h to 003Fh R/(W) Data Memory Page 1

0040h to 005Fh R/(W) Data Memory Page 2

0060h to 007Fh R/(W) Data Memory Page 3

0080h1) R/(W) Protection Control Byte

Page 0

0081h1) R/(W) Protection Control Byte

Page 1

0082h1) R/(W) Protection Control Byte

Page 2

0083h1) R/(W) Protection Control Byte

Page 3

0084h1) R/(W) Copy Protection Byte 55h or AAh: Copy Protect 0080:008Fh, and

0085h R Factory byte. Set at

Factory.

0086h R/(W) User Byte/Manufacturer ID

0087h R/(W) User Byte/Manufacturer ID

0088h to 008Fh N/A Reserved

Once programmed to AAh or 55h this address becomes read-only. All other codes can be stored but will neither

write-protect the address nor activate any function.

55h: Write Protect P0; AAh: EPROM mode P0; 55h or AAh: Write Protect 80h

55h: Write Protect P1; AAh: EPROM mode P1; 55h or AAh: Write Protect 81h

55h: Write Protect P2; AAh: EPROM mode P2; 55h or AAh: Write Protect 82h

55h: Write Protect P3; AAh: EPROM mode P3; 55h or AAh: Write Protect 83h

any write-protected Pages

AAh:Write Protect 85h, 86h, 87h; 55h: Write Protect 85h, unprotect 86h, 87h

MEMORY

Data memory and registers are located in a linear address space, as shown in Figure 5. The data memory and the registers have unrestricted read access. The DS1972 EEPROM array consists of 18 rows of 8 bytes each. The first 16 rows are divided equally into 4 memory pages (32 bytes each). These 4 pages are the primary data memory. Each page can be individually set to Open (unprotected), Write-Protected, or EPROM mode by setting the associated protection byte in the register row. The last two rows contain protection registers, and reserved bytes. The register row consists of 4 protection control bytes, a copy protection byte, the factory byte, and two user byte/manufacture ID bytes. The manufacturer ID can be a customer-supplied identification code that assists the application software in identifying the product the DS1972 is associated with. Contact the factory to set up and register a custom manufacturer ID. The last row is reserved for future use. It is undefined in terms of R/W functionality and should not be used.

In addition to the main EEPROM array, an 8-byte volatile scratchpad is included. Writes to the EEPROM array are a two-step process. First, data is written to the scratchpad, and then copied into the main array. This allows the user to first verify the data written to scratchpad prior to copying into the main array. The device only supports full row (8-byte) copy operations. In order for data in the scratchpad to be valid for a copy operation, the address supplied with a Write Scratchpad must start on a row boundary, and 8 full bytes must be written into the scratchpad.

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DS1972: 1024-Bit EEPROM iButton

The protection control registers determine how incoming data on a Write Scratchpad command is loaded into the scratchpad. A protection setting of 55h (Write Protect) causes the incoming data to be ingnored and the target address main memory data to be loaded into the scratchpad. A protection setting of AAh (EPROM mode) causes the logical AND of incoming data and target address main memory data to be loaded into the scratchpad. Any other protection control register setting leaves the associated memory page open for unrestricted write access. Protection control byte settings of 55h or AAh also write protects the protection control byte. The protection-control byte setting of 55h does not block the copy. This allows write-protected data to be refreshed (i. e., reprogrammed with the current data) in the device.

The copy protection byte is used for a higher level of security, and should only be used after all other protection control bytes, user bytes, and write-protected pages are set to their final value. If the copy protection byte is set to 55h or AAh, all copy attempts to the register row and user byte row are blocked. In addition, all copy attempts to write-protected main memory pages (i. e., refresh) are blocked.

ADDRESS REGISTERS AND TRANSFER STATUS

The DS1972 employs three address registers: TA1, TA2, and E/S (Figure 6). These registers are common to many other 1-Wire devices but operate slightly differently with the DS1972. Registers TA1 and TA2 must be loaded with the target address to which the data is written or from which data is read. Register E/S is a read-only transferstatus register, used to verify data integrity with write commands. E/S bits E2:E0 are loaded with the incoming T2:T0 on a Write Scratchpad command, and increment on each subsequent data byte. This is in effect a byteending offset counter within the 8-byte scratchpad. Bit 5 of the E/S register, called PF, is a logic 1 if the data in the scratchpad is not valid due to a loss of power or if the master sends less bytes than needed to reach the end of the scratchpad. For a valid write to the scratchpad, T2:T0 must be 0 and the master must have sent 8 data bytes. Bits 3, 4, and 6 have no function; they always read 0. The highest valued bit of the E/S register, called AA or Authorization Accepted, acts as a flag to indicate that the data stored in the scratchpad has already been copied to the target memory address. Writing data to the scratchpad clears this flag.

Figure 6. Address Registers

Bit # 7 6 5 4 3 2 1 0

Target Address (TA1) T7 T6 T5 T4 T3 T2 T1 T0

Target Address (TA2) T15 T14 T13 T12 T11 T10 T9 T8

Ending Address with

Data Status (E/S)

(Read Only)

AA 0 PF 0 0 E2 E1 E0

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