r
(
)
(
DS18B20-PAR
1-Wire
®
Parasite-Power
Digital Thermomete
FEATURES
• Unique 1-wire interface requires only one
port pin for communication
• Derives power from data line (“parasite
power”)—does not need a local power supply
• Multi-drop capability simplifies distributed
temperature sensing applications
• Requires no external components
• ±0.5°C accuracy from –10°C to +85°C
• Measures temperatures from –55°C to
+100°C (–67°F to +212°F)
• Thermometer resolution is user-selectable
from 9 to 12 bits
• Converts temperature to 12-bit digital word in
750 ms (max.)
• User–definable non-volatile temperature
alarm settings
• Alarm search command identifies and
addresses devices whose temperature is
outside of programmed limits (temperature
alarm condition)
• Software compatible with the DS1822-PAR
• Ideal for use in remote sensing applications
(e.g., temperature probes) that do not have a
local power source
PIN ASSIGNMENT
DALLAS
18B20P
2 3
1
DQ
GND
NC
1
2 3
BOTTOM VIEW)
TO-92
DS18B20-PAR
PIN DESCRIPTION
GND - Ground
DQ - Data In/Out
NC - No Connect
DESCRIPTION
The DS18B20-PAR digital thermometer provides 9 to 12–bit centigrade temperature measurements and
has an alarm function with nonvolatile user-programmable upper and lower trigger points. The
DS18B20-PAR does not need an external power supply because it derives power directl y from the data
line (“parasite power”). The DS18B20-PAR communicates over a 1-wire bus, which by definition
requires only one data line (and ground) for communication with a central microprocessor. It has an
operating temperature range of –55°C to +100°C and is accurate to ±0.5°C over a range of –10°C to
+85°C.
Each DS18B20-PAR has a unique 64-bit identification code, which allows multiple DS18B20-PARs to
function on the same 1–wire bus; thus, it is simple to use one microprocessor to control man y DS18B20PARs distributed over a large area. Applications that can benefit from this feature include HVAC
environmental controls, temperature monitoring systems inside buildings, equipment or machiner y, and
process monitoring and control systems.
1 of 19 043001
DETAILED PIN DESCRIPTIONS Table 1
PIN SYMBOL DESCRIPTION
DS18B20-PAR
1 GND
Ground.
2 DQ Data Input/Output pin. Open-drain 1-wire interface pin. Also provides power
to the device when used in parasite power mode (see “Parasite Power” section.)
3 NC No Connect. Doesn’t connect to internal circuit.
OVERVIEW
The DS18B20-PAR uses Dallas’ exclusive 1-wire bus protocol that implements bus communication using
one control signal. The control line requires a weak pullup resistor since all devices are linked to the bus
via a 3-state or open-drain port (the DQ pin in the case of the DS18 B20-PAR). In this bus system, the
microprocessor (the master device) identifies and addresses devices on the bus using each device’s unique
64-bit code. Because each device has a unique code, the number of devices that can be addressed on one
bus is virtually unlimited. The 1-wire bus protocol, including detailed explanations of the commands and
“time slots,” is covered in the 1-WIRE BUS SYSTEM section of this datasheet.
An important feature of the DS18B20-PAR is its ability to operate without an external power supply.
Power is instead supplied through the 1-wire pullup resistor via the DQ pin when the bus is high. The
high bus signal also charges an internal capacitor (CPP), which then supplies power to the device when the
bus is low. This method of deriving power from the 1-wire bus is referred to as “parasite power.”
Figure 1 shows a block diagram of the DS18B20-PAR, and pin descriptions are given in Table 1. The
64-bit ROM stores the device’s unique serial code. The scratchpad memory contains the 2-byte
temperature register that stores the digital output from the temperature sensor. In addition, the s crat chpad
provides access to the 1-byte upper and lower alarm trigger registers (TH and TL). The TH and T
L
registers are nonvolatile (EEPROM), so they will retain their data when the device is powered down.
DS18B20-PAR BLOCK DIAGRAM Figure 1
4.7K
VPU
DQ
GND
PARASITE POWER
CIRCUIT
INTERNAL VDD
CPP
64-BIT ROM
AND
1-wire PORT
MEMORY CONTROL
LOGIC
SCRATCHPAD
DS18B20-PAR
TEMPERATURE SENSOR
ALARM HIGH TRIGGER (T
REGISTER (EEPROM)
ALARM LOW TRIGGER (TL)
REGISTER (EEPROM)
CONFIGURATION REGISTER
(EEPROM)
8-BIT CRC GENERATOR
)
H
2 of 19
DS18B20-PAR
R
PARASITE POWER
The DS18B20-PAR’s parasite power circuit allows the DS18B20-PAR to operate without a local external
power supply. This ability is especially useful for applications that require remote temper ature s ensing or
that are very space constrained. Fi gure 1 shows the DS18B20-PAR’s parasite-power control cir cuitry,
which “steals” power from the 1-wire bus via the DQ pin when the bus is high. The stolen charge powers
the DS18B20-PAR while the bus is high, and some of the charge is stored on the parasite power capacitor
(CPP) to provide power when the bus is low.
The 1-wire bus and CPP can provide sufficient parasite power to the DS18B20-PAR for most operations
as long as the specified timing and voltage requirements are met (refer to the DC ELECTRICAL
CHARACTERISTICS and the AC ELECTRICAL CHARACTERISTICS sections of this data sheet).
However, when the DS18B20-PAR is performing temperature conversions or copying data from the
scratchpad memory to EEPROM, the operating current can be as high as 1.5 mA. This current can cause
an unacceptable voltage drop across the weak 1-wire pullup resistor and is more current than can be
supplied by C
. To assure that the DS18B20-PAR has sufficient supply current, it is necessary to
PP
provide a strong pullup on the 1-wire bus whenever temperature conversi ons are taking place or data is
being copied from the scratchpad to EEPROM. This can be accomplished by using a MOSFET to pull
the bus directly to the rail as shown in Figure 2. The 1-wire bus must be switched to the strong pullup
within 10 µs (max) after a Convert T [44h] or Copy Scratchpad [48h] command is issued, and the bus
must be held high by the pullup for the duration of the conversion (t
) or data transfer (t
conv
= 10 ms).
wr
No other activity can take place on the 1-wire bus while the pullup is enabled.
SUPPLYING THE DS18B20-PAR DURING TEMPERATURE CONVERSIONS
Figure 2
Micro-
processor
VPU
4.7K
VPU
1-Wire Bus
DS18B20-PA
GND
DQ
To Other
1-Wire Devices
OPERAT ION – ME ASURING TEMPERATURE
The core functionality of the DS18B20-PAR is its direct-to-digital temperature sensor. The resolution of
the temperature sensor is user-configurable to 9, 10, 11, or 12 bits, which corresponds to increments of
0.5°C, 0.25°C, 0.125°C, and 0.0625°C, respectively. The default resolution at power-up is 12-bit.
The DS18B20-PAR powers-up in a low-power idle state; to initiate a temperature measurement and A-to-
D conversion, the master must issue a Convert T [44h] command. Following the conversion, the
resulting thermal data is stored in the 2-byte temperature register in the scratchpad memory and the
DS18B20-PAR returns to its idle state. The DS18B20-PAR output data is calibrated in degrees
centigrade; for Fahrenheit applications, a lookup table or conversion routine must be used. The
temperature data is stored as a 16-bit sign-extended two’s complement number in the temperature register
(see Figure 3). The sign bits (S) indicate if the temperature is positive or negative: for positive numbers S
= 0 and for negative numbers S = 1. If the DS18B20-PAR is configured for 12-bit resolution, all bits in
the temperature register will contain valid data. For 11-bit resolution, bit 0 is undefined. For 10-bit
3 of 19
DS18B20-PAR
resolution, bits 1 and 0 are undefined, and for 9-bit resolution bits 2, 1 and 0 are undefined. Table 2 gives
examples of digital output data and the corresponding temperature reading for 12-bit resolution
conversions.
TEMPERATURE REGISTER FORMAT Figure 3
LS Byte
MS Byte
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
23 2
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8
2
2
S S S S S 26 2
1
2
0
2
-1
2
-2
2
-3
2
5
2
-4
4
TEMPERATURE/DATA RELATIONSHIP Table 2
TEMPERATURE DIGITAL OUTPUT
(Binary)
DIGITAL OUTPUT
(Hex)
+85°C* 0000 0101 0101 0000 0550h
+25.0625°C 0000 0001 1001 0001 0191h
+10.125°C 0000 0000 1010 0010 00A2h
+0.5°C 0000 0000 0000 1000 0008h
0°C 0000 0000 0000 0000 0000h
-0.5°C 1111 1111 1111 1000 FFF8h
-10.125°C 1111 1111 0101 1110 FF5Eh
-25.0625°C 1111 1110 0110 1111 FE6Fh
-55°C 1111 1100 1001 0000 FC90h
*The power-on reset value of the temperature register is +85°C
OPERAT ION – ALARM SIGNALING
After the DS18B20-PAR performs a temperature conversion, the temperature valu e is compared to the
user-defined two’s complement alarm trigger values stored in the 1-byte TH and TL registers (see Figure
4). The sign bit (S) indicates if the value is positive or negative: for positive numbers S = 0 and for
negative numbers S = 1. The T
when the device is powered down. T
explained in the MEMORY section of this datasheet.
and TL registers are nonvolatile (EEPROM) so they will retain data
H
and TL can be accessed through b ytes 2 and 3 of the scratchp ad as
H
TH AND TL REGISTER FORMAT Figure 4
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 b it 0
S 26 2
5
2
Only bits 11 through 4 of the temperature register are used in t he TH and TL comparison since TH and T
are 8-bit registers. If the result of a temperature measurement is higher than TH or lower than TL, an
alarm condition exists and an alarm flag is set inside the DS18B20-PAR. This flag is updated after every
temperature measurement; therefore, if the alarm condition goes away, the flag will be turned off after the
next temperature conversion.
4 of 19
5
2
5
2
2
2
1
2
0
L
DS18B20-PAR
The master device can check th e alarm flag status of all DS DS18B20-PARs on the bus by issui ng an
Alarm Search [ECh] command. Any DS18B20-PARs with a set alarm flag will respond to the command,
so the master can determine exact ly which DS18B20-PARs have experien ced an alarm condition. If an
alarm condition exists and the TH or TL settings have changed, another temperature conversion should be
done to validate the alarm condition.
64-BIT LASERED ROM CODE
Each DS18B20-PAR contains a unique 64–bit code (see Figure 5) stored in ROM. The least significant 8
bits of the ROM code contain the DS18B20-PAR’s 1–wire family code: 28h. The nex t 48 bits contain a
unique serial number. The most significant 8 bits contain a cyclic redundancy check (CRC) byte that is
calculated from the first 56 bits of the ROM code. A detailed explanation of the CRC bits is provided in
the CRC GENERATION section. The 64–bit ROM code and associated ROM function control logic
allow the DS18B20-PAR to operate as a 1–wire device using the protocol detailed in the 1-WIRE BUS
SYSTEM section of this datasheet.
64-BIT LASERED ROM CODE Figure 5
8-BIT CRC 48-BIT SERIAL NUMBER 8-BIT FAMILY CODE (28h)
MSB MSB LSB LSB LSBMSB
MEMORY
The DS18B20-PAR’s memory is organized as shown in Figure 6. The memory consists of an SRAM
scratchpad with nonvolatile EEPROM storage for the high and low alarm trigger registers (TH and TL)
and configuration register. Note that if the DS18B20-PAR alarm function is not used, the TH and TL
registers can serve as general-purpose memory. All memory commands are described in detail in the
DS18B20-PAR FUNCTION COMMANDS section.
Byte 0 and byte 1 of the scratchpad contain the LSB and the MSB of the temperature register,
respectively. These bytes are read-onl y. Bytes 2 and 3 provide access to TH and TL registers. Byte 4
contains the configuration register data, which is explained in detail in the CONFIGURATION
REGISTER section of this datasheet. Bytes 5, 6 and 7 ar e reserved for internal use by the device and
cannot be overwritten; these bytes will return all 1s when read.
Byte 8 of the scratchpad is read-only and contains the cyclic redundancy check (CRC) code for bytes 0
through 7 of the scratchpad. The DS18B20-PAR generates this CRC using the method described in the
CRC GENERATION section.
Data is written to bytes 2, 3, and 4 of the scratchpad using the W rite Scratchpad [4Eh] command, and the
data must be transmitted to the DS18B20-PAR starting with the least significant bit of byte 2. To verify
data integrity, the scratchpad can be read (using the Read Scratchpad [BEh] command) after the data is
written. When reading the scratchpad, data is transferred over the 1-wire bus starting with the least
significant bit of byte 0. To transfer the T
the master must issue the Copy Scratchpad [48h] command.
, TL and configuration data from the scratchpad to EEPROM,
H
Data in the EEPROM registers is retained when the device is powered down; at power-up the EEPROM
data is reloaded into the corresponding scratchpad locations. Data can also be reloaded from EEPROM
to the scratchpad at any time using the Recall E2 [B8h] command. The master can issue “read time slots”
(see the 1-WIRE BUS SYS TEM section) following the R ecall E2 command and the DS18B20-PAR will
indicate the status of the recall by transmitting 0 while the recall is in progress and 1 when the recall is
done.
5 of 19
DS18B20-PAR
DS18B20-PAR MEMORY MAP cбЦмкЙ=S
SCRATCHPAD (Power-up State)
byte 0 Temperature LSB (50h)
(85°C)
byte 1 Temperature MSB (05h)
EEPROM
byte 2 TH Register or User Byte 1* TH Register or User Byte 1
byte 3 TL Register or User Byte 2* TL Register or User Byte 2
byte 4 Configuration Register* Configuration Register
byte 5 Reserved (FFh)
byte 6 Reserved (0Ch)
byte 7 Reserved (10h)
byte 8 CRC*
*Power-up state depends on value(s) stored
in EEPROM
CONFIGURATION REGISTER
Byte 4 of the scratchpad memory contains the configuration register, which is organized as illustrated in
Figure 7. The user can set the conversion resolution of the DS18B20-PAR using the R0 and R1 bits in
this register as shown in Table 3. The power-up default of these bits is R0 = 1 and R1 = 1 (12-bit
resolution). Note that there is a direct tradeoff between resolution and conversion time. Bit 7 and bits 0-4
in the configuration register are reserved for internal use b y the device and cannot be overwritten; these
bits will return 1s when read.
CONFIGURATION REGISTER Figure 7
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
0 R1 R0 1 1 1 1 1
THERMOMETER RESOLUTION CONFIGURATION Table 3
R1 R0 Resolution Max Conversion Time
0 0 9-bit 93.75 ms (t
0 1 10-bit 187.5 ms (t
1 0 11-bit 375 ms (t
1 1 12-bit 750 ms (t
CONV
CONV
CONV
CONV
/8)
/4)
/2)
)
CRC GENERATION
CRC bytes are provided as part of the DS18B20-PAR’s 64-bit ROM code and in the 9th byte of the
scratchpad memory. The ROM code CRC is calculated from the first 56 bits of the ROM code and is
contained in the most significant byte of the ROM. The scratchpad CRC is calculated from the data
stored in the scratchpad, and therefore i t changes when the data in the scratchpad chan ges. The CRCs
provide the bus master with a method of data validation when data is read from the DS18B20-PAR. To
6 of 19
DS18B20-PAR
verify that data has been read correctly, the bus master must re-calculate the CRC from the received data
and then compare this value to either the ROM code CRC (for ROM reads) or to the scratchpad CRC (for
scratchpad reads). If the calculated CRC matches the read CRC, the data has been received error free. The
comparison of CRC values and the decision to continue with an operation are determined entirely by the
bus master. There is no circuitry inside the DS18B20-PAR that prevents a command sequence from
proceeding if the DS18B20-PAR CRC (ROM or scratchpad) does not mat ch the value generated by the
bus master.
The equivalent polynomial function of the CRC (ROM or scratchpad) is: CRC = X8 + X5 + X4 + 1
The bus master can re-calculate the CRC and compare it to the CRC values from the DS18B20-PAR
using the polynomial generator shown in Figure 8. This circuit consists of a shift register and XOR gates,
and the shift register bits are initialized to 0. Starting with the least significant bit of the ROM code or the
least significant bit of byte 0 in the scratchpad, one bit at a time should shifted into the shift register.
After shifting in the 56th bit from the ROM or the most significant bit of byte 7 from the scratchpad, the
polynomial generator will contain the re-calculated CRC. Next, the 8-bit ROM code or scratchpad CRC
from the DS18B20-PAR must be shifted into the circuit. At this point, if the re-calculated CRC was
correct, the shift register will contain all 0s. Additional information about the Dallas 1-wire cyclic
redundancy check is available in Application Note 27 entitled “Understanding and Using Cyclic
Redundancy Checks with Dallas Semiconductor Touch Memory Products.”
CRC GENERATOR Figure 8
(MSB) (LSB)
XOR XOR
INPUT
XOR
1-WIRE BUS SYSTEM
The 1-wire bus system uses a single bus master to control one or more slave devices. The DS18B20-PAR
is always a slave. When there is onl y one slave on the bus, the system is referred to as a “single-drop”
system; the system is “multi-drop” if there are multiple slaves on the bus.
All data and commands are transmitted least significant bit first over the 1-wire bus.
The following discussion of the 1-wire bus system is broken down into three topics: hardware
configuration, transaction sequence, and 1-wire signaling (signal types and timing).
HARDWARE CONFIGURATION
The 1-wire bus has b y definition only a single data line. Each device (master or slave) interfaces to the
data line via an open drain or 3–state port. Thi s allows each device to “release” the data lin e when the
device is not transmitting data so the bus is available for use by another device. The 1-wire port of the
DS18B20-PAR (the DQ pin) is open drain with an internal circuit equivalent to that shown in Figure 9.
The 1-wire bus requires an external pullup resistor of approximately 5 kΩ; thus, the idle state for the 1wire bus is high. If for any reason a transaction needs to be suspended, the bus MUST be left in the idle
state if the transaction is to resume. Infinite recovery time can occur between bits so long as the 1-wire
bus is in the inactive (high) state during the recov ery period. If the bus is held low for more than 480 µs,
all components on the bus will be reset. In addition, to assure that the DS18B20-PAR has sufficient
supply current during temperature conversions, it is necessary to provide a strong pullup (such as a
MOSFET) on the 1-wire bus whenever temperature conv ersions or EEPROM writes are taking place (as
described in the PARASITE POWER section).
7 of 19
HARDWARE CONFIGURATION cбЦмкЙ=V=
OS
Micro-
processor
RX
TX
VPU
Strong
Pullup
VPU
4.7K
1-wire bus
RX = RECEIVE
T
= TRANSMIT
X
DS18B20-PAR 1-WIRE PORT
DQ
Pin
5 µA
Typ.
TRANSACTION SEQUENCE
The transaction sequence for accessing the DS18B20-PAR is as follows:
100 ΩΩΩΩ
M
DS18B20-PAR
R
X
T
X
FET
Step 1. Initialization
Step 2. ROM Command (followed by any required data exchange)
Step 3. DS18B20-PAR Function Command (followed by any required data exchange)
It is very important to follow this sequence every time the DS18B20-PAR is accessed, as the DS18B20-
PAR will not respond if any steps in the sequence are missing or out of order. Exceptions to this rule are
the Search ROM [F0h] and Alarm Search [ECh] commands. After issuing either of these ROM
commands, the master must return to Step 1 in the sequence.
INITIALIZATION
All transactions on the 1-wire bus begin with an initialization sequence. The initialization sequence
consists of a reset pulse transmitted by the bus master followed by presence pulse(s) transmitted by the
slave(s). The presence pulse lets the bus master know that slave devices (such as the DS18B20-PAR) are
on the bus and are ready to operate. Timing for the reset and presence pulses is detailed in the
1-WIRE SIGNALING section.
ROM COMMANDS
After the bus master has detected a presence pulse, it can issue a ROM command. These commands
operate on the unique 64–bit ROM codes of each slave device and allow the master to single out a
specific device if many are present on the 1-wire bus. These commands also allow the master to
determine how many and what types of devices are present on the bus or if any device has experienced an
alarm condition. There are five ROM commands, and each command is 8 bits long. The m aster device
must issue an appropriate ROM command before issuing a DS18B20-PAR function command. A
flowchart for operation of the ROM commands is shown in Figure 10.
SEARCH ROM [F0h]
When a system is initially powered up, the master must identify the ROM codes of all slave devices on
the bus, which allows the master to determine the number of slaves and their device types. The master
learns the ROM codes through a process of elimination that requires the master to perform a Search ROM
8 of 19
DS18B20-PAR
cycle (i.e., Search ROM command followed by data exchange) as many times as necessary to identify all
of the slave devices. If there is only one slave on the bus, the simpler Read ROM comm and (see below)
can be used in place of the Search ROM process. For a detailed explanation of the Search ROM
procedure, refer to the iButton Book of Standards at www.ibutton.com/ibuttons/standard.pdf. After every
Search ROM cycle, the bus master must return to Step 1 (Initialization) in the transaction sequence.
READ ROM [33h]
This command can only be used when there is one slave on the bus. It allows the bus master to re ad the
slave’s 64-bit ROM code without using the Search ROM procedure. If this command is us ed wh en t here
is more than one slave present on the bus, a data collision will occur when all the slaves attempt to
respond at the same time.
MATCH ROM [55h]
The match ROM command followed by a 64–bit ROM code sequence allows the bus master to add ress a
specific slave device on a multi-drop or single-drop bus. Only the slave that exactl y matches the 64–bit
ROM code sequence will respond to the function command issued by the master; all other slaves on the
bus will wait for a reset pulse.
SKIP ROM [CCh]
The master can use this command to address all devices on the bus simultaneously without sending out
any ROM code information. For example, the master can make all DS18B20-PARs on the bus perform
simultaneous temperature conversions by issuing a Skip ROM command followed by a Convert T [44h]
command. Note, however, that the Skip ROM command can only be followed by the Read Scratchpad
[BEh] command when there is one slave on the bus. This sequence saves time by allowing the master to
read from the device without sending its 64–bit ROM code. This sequence will cause a data collision on
the bus if there is more than one slave since multiple devices will attempt to transmit data simultaneously.
ALARM SEARCH [ECh]
The operation of this command is identical to the operation of the Search ROM command except that
only slaves with a set alarm flag will respond. This command allows the master device to deter mine if
any DS18B20-PARs experienced an alarm condition during the most recent temperature conversion.
After every Alarm Searc h c ycle (i.e., Alarm S ea rc h comm and follo wed by data exchange), the bus master
must return to Step 1 (Initialization) in the transaction sequence. Refer to the OPERATION – ALARM
SIGNALING section for an explanation of alarm flag operation.
DS18B20-PAR FUNCTION COMMANDS
After the bus master has used a ROM command to address the DS18B20-PAR with which it wishes to
communicate, the master can issue one of the DS18B20-PAR function commands. These commands
allow the master to write to and read from the DS18B20-PAR’s scratchpad memory, initiate temperature
conversions and determine the power supply mode. The DS18B20-PAR function commands, which are
described below, are summarized in Table 4 and illustrated by the flowchart in Figure 11.
CONVERT T [44h]
This command initiates a single temperature conversion. Following the conversion, the resulting thermal
data is stored in the 2-byte temperature register in the scratchpad memory and the DS18B20-PAR returns
to its low-power idle state. Within 10 µs (max) after this command is issued the master must enable a
strong pullup on the 1-wire bus for the duration of the conversion (t
) as described in the PARASITE
conv
POWER section.
WRITE SCRATCHPAD [4Eh]
This command allows the master to write 3 bytes of data to the DS18B20-PAR’s scratchpad. The first
data byte is written into the TH register (byte 2 of the scratchpad), the second b yte is written into the TL
register (byte 3), and the third byte is written into the configuration register (byte 4). Data must be
9 of 19
DS18B20-PAR
transmitted least significant bit first. All three bytes MUST be written before the master issues a reset, or
the data may be corrupted.
READ SCRATCHPAD [BEh]
This command allows the master to read the contents of the scratchpad. The data transfer starts with the
least significant bit of byte 0 and continues through the scratchpad until the 9th byte (byte 8 – CRC) is
read. If only part of the scratchpad contents is required, the master may issue a reset to terminate reading
at any time.
COPY SCRATCHPAD [48h]
This command copies the contents of the scr atchpad TH, TL and configuration registers (bytes 2, 3 and 4)
to EEPROM. Within 10 µs (max) after this command is issued the master must enable a strong pullup on
the 1-wire bus for at least 10 ms as described in the PARASITE POWER section.
RECALL E2 [B8h]
This command recalls the alarm trigger values (TH and TL) and configuration data from EEPROM and
places the data in bytes 2, 3, and 4, respectivel y, in the scratchpad memory. The mast er device can issue
“read time slots” (see the 1-WIRE BUS SYSTEM section) following the Recall E2 command and the
DS18B20-PAR will indicate the status of the recall by transmitting 0 while the recall is in progress and
1 when the recall is done. The recall operation happens automatically at power-up, so valid data is
available in the scratchpad as soon as power is applied to the device.
DS18B20-PAR Function Command Set Table 4
Command
Convert T Initiates temperature
Read Scratchpad Reads the entire scratchpad
Write Scratchpad Writes data into scratchpad
Copy Scratchpad Copies TH, TL, and
Recall E2
Description
Protocol
TEMPERATURE CONVERSION COMMANDS
44h None 1
conversion.
MEMORY COMMANDS
BEh DS18B20-PAR transmits up
including the CRC byte.
4Eh Master transmits 3 data
bytes 2, 3, and 4 (T
, TL, and
H
configuration registers).
48h None 1
configuration register data from
the scratchpad to EEPROM.
Recalls TH, TL, and
B8h DS18B20-PAR transmits
configuration register data from
EEPROM to the scratchpad.
1-Wire Bus Activity
After Command is Issued Notes
2
to 9 data bytes to master.
3
bytes to DS18B20-PAR.
recall status to master.
NOTES:
1. The master must enable a strong pullup on the 1-wire bus during temperature conversions and copies
from the scratchpad to EEPROM. No other bus activity may take place during this time.
2. The master can interrupt the transmission of data at any time by issuing a reset.
3. All three bytes must be written before a reset is issued.
10 of 19
ROM COMMANDS FLOW CHART Figure 10
A
Initialization
Sequence
33h
READ ROM
COMMAND
Y
N N
MATCH ROM
COMMAND
MASTER T
DS18B20-PAR TX
FAMILY CODE
1 BYTE
DS18B20-PAR TX
SERIAL NUMBER
6 BYTES
MATCH?
DS18B20-PAR TX
CRC BYTE
MASTER TX
MASTER TX
MATCH?
MASTER TX
RESET PULSE
DS18B20-PAR
TX PRESENCE
PULSE
MASTER TX ROM
COMMAND
55h
BIT 0
BIT 0
BIT 1
BIT 1
MATCH?
BIT 63
BIT 63
N
Y Y Y
X
N
Y
N
Y
N
Y
MASTER TX
COMMAND
(FIGURE 11)
F0h
SEARCH ROM
COMMAND
DS18B20-PAR TX BIT 0
DS18B20-PAR TX BIT 0
MASTER TX BIT 0
N
BIT 0
MATCH?
Y
DS18B20-PAR TX BIT 1
DS18B20-PAR TX BIT 1
MASTER TX BIT 1
N
BIT 1
MATCH?
Y
DS18B20-PAR TX BIT 63
BIT 63
MATCH?
Y
BIT 63
X
DS18B20-PAR T
MASTER TX BIT 63
N
FUNCTION
ECh
LARM SEARCH
COMMAND
DS18B20-PAR TX BIT 0
DS18B20-PAR TX BIT 0
MASTER TX BIT 0
DEVICE(S)
WITH ALARM
FLAG SET?
Y
DS18B20-PAR
N
N
CCh
SKIP ROM
COMMAND
Y
N
11 of 19
DS18B20-PAR FUNCTION COMMANDS FLOW CHART Figure 11
DS18B20-PAR
MASTER TX
FUNCTION
COMMAND
N
B8h
RECALL E2
?
Y
44h
CONVERT
TEMPERATURE
?
Y
MASTER ENABLES
STRONG PULLUP ON DQ
DS18B20-PAR CONVERTS
TEMPERATURE
MASTER DISABLES
STRONG PULLUP
N
STRONG PULL-UP ON DQ
SCRATCHPAD TO EEPROM
N
BEh
READ
SCRATCHPAD
?
Y
48h
COPY
SCRATCHPAD
?
Y
MASTER ENABLES
DATA COPIED FROM
MASTER DISABLES
STRONG PULLUP
N
SCRATCHPAD
N
4Eh
WRITE
?
Y
MASTER BEGINS DATA
RECALL FROM E2 PROM
DEVICE
BUSY RECALLING
DATA
?
Y
MASTER
RX “0s”
N
MASTER
RX “1s”
RETURN TO INITIALIZATION
SEQUENCE (FIGURE 10) FOR
NEXT TRANSACTION
MASTER RX DATA BYTE
FROM SCRATCHPAD
MASTER
RESET
T
X
?
N
N
HAVE 8 BYTES
BEEN READ
?
Y
MASTER RX SCRATCHPAD
CRC BYTE
MASTER TX TH BYTE
TO SCRATCHPAD
MASTER TX TL BYTE
TO SCRATCHPAD
Y
MASTER TX CONFIG. BYTE
TO SCRATCHPAD
12 of 19
DS18B20-PAR
p
p
µ
µµ
µ
µµ
R
R
1-WIRE SIGNALING
The DS18B20-PAR uses a strict 1-wire communication protocol to insure data integrity. Several signal
types are defined by this protocol: reset pulse, presence pulse, write 0, writ e 1, read 0, and read 1. All of
these signals, with the exception of the presence pulse, are initiated by the bus master.
INITIALIZATION PROCEDURE: RESET AND PRESENCE PULSES
All communication with the DS18B20-PAR begins with an initialization sequence that consists of a reset
pulse from the master followed by a presence pulse from the DS18B20-PAR. This is illustrated in
Figure 12. When the DS18B20-PAR sends the presence pulse in response to the reset, it is indicating to
the master that it is on the bus and ready to operate.
During the initialization sequence the bus master transmits (T
low for a minimum of 480 µs. The bus master then releases the bus and goes into re ceive mode (R
) the reset pulse by pulling the 1-wire bus
X
).
X
When the bus is released, the 5k pullup resistor pulls the 1-wire bus high. When the DS18B20-PAR
detects this rising edge, it waits 15–60 µs and then transmits a presence pulse by pulling the 1-wire bus
low for 60–240 µs.
INITIALIZATION TIMI NG Figure 12
VPU
1-WIRE BUS
GND
MASTER TX RESET PULSE MASTER
480
480
µs minimum
DS18B20-PA
waits 15-60 µµµµs
LINE TYPE LEGEND
Bus master pulling low
DS18B20-PAR pulling low
Resistor
DS18B20-PAR T
presence pulse
ullu
µs minimum
X
60-240 µµµµs
X
READ/WRITE TIME SLOTS
The bus master writes data to the DS18B20-PAR during write time slots and reads data from the
DS18B20-PAR during read time slots. One bit of data is transmitted over the 1-wire bus per time slot.
WRITE TIME SLOTS
There are two types of write time slots: “Write 1” time slots and “Write 0” time slots. The bus master
uses a Write 1 time slot to write a logic 1 to the DS18B20-PAR and a Write 0 time slot to write a logic 0
to the DS18B20-PAR. All write time slots must be a minimum of 60 µs in duration with a minimum of a
1 µs recovery time between individual write slots. Both types of write time slots are initiated by the
master pulling the 1-wire bus low (see Figure 13).
To generate a Write 1 time slot, after pulling the 1-wire bus low, the bus master must release the 1-wire
bus within 15 µs. When the bus is released, the 5k pullup resistor will pull the bus high. To generate a
Write 0 time slot, after pulling the 1-wire bus low, the bus master must continue to hold the bus low for
the duration of the time slot (at least 60 µs).
13 of 19
DS18B20-PAR
µ
µµ
µ
µµ
µ
µµ
X
µ
µµ
µ
µµ
µ
µµ
X
µ
µµ
µ
µµ
µ
µµ
µ
µµ
µ
µµ
µ
µµ
µ
µµ
The DS18B20-PAR samples the 1-wire bus during a window that lasts from 15 µs to 60 µs after the
master initiates the write time slot. If the bus is high during the sampling window, a 1 is written to the
DS18B20-PAR. If the line is low, a 0 is written to the DS18B20-PAR.
READ/WRITE TIME SLOT TIMING DIAGRAM Figure 13
OF SLOT
VPU
1-WIRE BUS
GND
START
MASTER WRITE “0 ” SL OT MASTER WRITE “1 ” SLO T
60
µs < TX “0” < 120
DS18B20-PAR samples
MIN TYP MA
15
µs
15
µs
30
µs
START
OF SLOT
1 µµµµs < T
15
µs
< ∞
REC
µs
> 1
DS18B20-PAR samples
MIN TYP MA
15
µs
30
µs
VPU
1-WIRE BUS
GND
> 1
µs
15
MASTER READ “0” SLOT MASTER READ “1” SLOT
µs
Master samples
45
µs
> 1
µs
1 µµµµs < T
15
µs
< ∞
REC
Master samples
LINE TYPE LEGEND
Resistor pullup
Bus master pulling low DS18B20-PAR pulling low
READ TIME SLOTS
The DS18B20-PAR can only transmit data to the master when the master issues read time slots.
Therefore, the master must generate read time slots immediately after issuing a Read Scratchpad [BEh]
command, so that the DS18B20-PAR can provide the requested data. In addition, the master can generate
read time slots after issuing a Recall E
DS18B20-PAR FUNCTION COMMAND section.
All read time slots must be a minimum of 60 µs in duration with a minimum of a 1 µs recovery time
between slots. A read time slot is initiated by the master device pulling the 1-wire bus low for a
minimum of 1 µs and then releasing the bus (see Figure 13). After the master initiates the read time slot,
the DS18B20-PAR will begin transmitting a 1 or 0 on bus. The DS18B20-PAR transmits a 1 by leaving
the bus high and transmits a 0 by pulling the bus low. When transmitting a 0, the DS18B20-PAR will
release the bus by the end of the time slot, and the bus will be pulled back to its high idle state by the
pullup resister. Output data from the DS18B20-PAR is valid for 15 µs after the falling edge that initiated
14 of 19
2
[B8h] command to find out the recall status as explained in the
DS18B20-PAR
µ
µµ
V
µ
µµ
µ
µµ
V
the read time slot. Therefore, the master must release the bus and then sample the bus state within 15 µs
from the start of the slot.
Figure 14 illustrates that the sum of T
Figure 15 shows that system timing margin is maximized by keeping T
, TRC, and T
INIT
SAMPLE
must be less t han 15 µs for a read tim e slot.
and TRC as short as possible
INIT
and by locating the master sample time during read time slots towards the end of the 15 µs period.
DETAILED MASTER READ 1 TIMING Figure 14
VPU
1-WIRE BUS
GND
15
T
RC
µs
T
> 1
µs
INT
IH of Master
Master samples
RECOMMENDED MASTER READ 1 TIMING Figure 15
VPU
1-WIRE BUS
GND
T
=
INT
small
T
RC
small
=
IH of Master
15
µs
Master samples
LINE TYPE LEGEND
Bus master pulling low
Resistor pullup
RELATED APPLICATION NOTES
The following Application Notes can be applied to the DS18B20-PAR. These notes can be obtained from
the Dallas Semiconductor “Application Note Book,” via the Dallas website at http://www.dalsemi.com/,
or through our faxback service at (214) 450–0441.
Application Note 27: “Understanding and Using Cyclic Redundanc y Checks with Dallas Semiconductor
Touch Memory Product”
Application Note 55: “Extending the Contact Range of Touch Memories”
Application Note 74: “Reading and Writing Touch Memories via Serial Interfaces”
Application Note 104: “Minimalist Temperature Control Demo”
Application Note 106: “Complex MicroLANs”
Application Note 108: “MicroLAN – In the Long Run”
Sample 1-wire subroutines that can be used in conjunction with AN74 can be downloaded from the
Dallas website or anonymous FTP Site.
15 of 19
DS18B20-PAR
DS18B20-PAR OPERATION EXAMPLE 1
In this example there are multiple DS18B20-PARs on the bus. The bus master initiates a temperature
conversion in a specific DS18B20-PAR and then reads its scratchpad and recalculates the CRC to verify
the data.
MASTER MODE DATA (LSB FIRST) COMMENTS
TX Reset Master issues reset pulse.
RX Presence DS18B20-PARs respond with presence pulse.
TX 55h Master issues Match ROM command.
TX 64-bit ROM code Master sends DS18B20-PAR ROM code.
TX 44h Master issues Convert T command.
TX DQ line held high by
strong pullup
Master applies strong pullup to DQ for the duration of the
conversion (t
conv
).
TX Reset Master issues reset pulse.
RX Presence DS18B20-PARs respond with presence pulse.
TX 55h Master issues Match ROM command.
TX 64-bit ROM code Master sends DS18B20-PAR ROM code.
TX BEh Master issues Read Scratchpad command.
RX 9 data bytes Master reads entire scratchpad including CRC. The master
then recalculates the CRC of the first eight data bytes from the
scratchpad and compares the calculated CRC with the read
CRC (byte 9). If they match, the master continues; if not, the
read operation is repeated.
DS18B20-PAR OPERATION EXAMPLE 2
In this example there is only one DS18B20-PAR on the bus. The master writes to the TH, TL, and
configuration registers in the DS18B20-PAR scratchpad and then reads the scratchpad and recalculates
the CRC to verify the data. The master then copies the scratchpad contents to EEPROM.
MASTER MODE DATA (LSB FIRST) COMMENTS
TX Reset Master issues reset pulse.
RX Presence DS18B20-PAR responds with presence pulse.
TX CCh Master issues Skip ROM command.
TX 4Eh Master issues Write Scratchpad command.
TX 3 data bytes Master sends three data bytes to scratchpad (TH, TL, and config).
TX Reset Master issues reset pulse.
RX Presence DS18B20-PAR responds with presence pulse.
TX CCh Master issues Skip ROM command.
TX BEh Master issues Read Scratchpad command.
RX 9 data bytes Master reads entire scratchpad including CRC. The master then
recalculates the CRC of the first eight data bytes from the
scratchpad and compares the calculated CRC with the read CRC
(byte 9). If they match, the master continues; if not, the read
operation is repeated.
TX Reset Master issues reset pulse.
RX Presence DS18B20-PAR responds with presence pulse.
TX CCh Master issues Skip ROM command.
TX 48h Master issues Copy Scratchpad command.
TX DQ line held high by
strong pullup
Master applies strong pullup to DQ for at least 10 ms while copy
operation is in progress.
16 of 19
DS18B20-PAR
ABSOLUTE MAXIMUM RATINGS*
Voltage on any pin relative to ground –0.5V to +6.0V
Operating temperature –55°C to +100°C
Storage temperature –55°C to +125°C
Soldering temperature See J-STD-020A Specification
*These are stress ratings only and functional operation of the device at these or any other conditions
above those indicated in the operation sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods of time may affect reliability.
DC ELECTRICAL CHARACTERISTICS (-55°C to +100°C; VPU=3.0V to 5.5V)
PARAMETER SYMBOL CONDITION MIN TYP MAX UNITS NOTES
Pullup Supply
VPU 3.0 5.5 V 1,2
Voltage
Thermometer Error t
-10°C to +85°C ±½
ERR
°C
3
-55°C to +100°C ±2
Input Logic Low VIL -0.3 +0.8 V 1,4,5
Input Logic High VIH 3.0 5.5 V 1,6
Sink Current IL V
Active Current I
1 1.5 mA 7
DQA
=0.4V 4.0 mA 1
I/O
DQ Input Current IDQ 5 µA 8
Drift
±0.2 °C 9
NOTES:
1. All voltages are referenced to ground.
2. The Pullup Supply Voltage specification assumes that the pullup device (resistor or transistor) is
ideal, and therefore the high level of the pullup is equal to VPU. In order to meet the VIH spec of the
DS18B20-PAR, the actual supply rail for the strong pullup transistor must include margin for the
voltage drop across the transistor when it is turned on; thus: V
PU_ACTUAL
3. See typical performance curve in Figure 16.
4. Logic low voltages are specified at a sink current of 4 mA.
5. To always guarantee a presence pulse under low voltage parasite power conditions, V
to be reduced to as low as 0.5V.
6. Logic high voltages are specified at a source current of 1 mA.
7. Active current refers to supply current during active temperature conversions or EEPROM writes.
8. DQ line is high (“hi-Z” state).
9. Drift data is based on a 1000 hour stress test at 125°C.
= V
PU_IDEAL
+ V
TRANSISTOR
ILMAX
.
may have
AC ELECTRICAL CHARACTERISTICS: NV MEMORY (-55°C to +100°C; V
PARAMETER SYMBOL CONDITION MIN TYP MAX UNITS
NV Write Cycle Time twr 2 10 ms
EEPROM Writes N
EEPROM Data Retention t
-55°C to +55°C 50k writes
EEWR
-55°C to +55°C 10 years
EEDR
=3.0V to 5.5V)
PU
17 of 19
DS18B20-PAR
AC ELECTRICAL CHARACTERISTICS (-55°C to +100°C; VPU=3.0V to 5.5V)
PARAMETER SYMBOL CONDITION MIN TYP MAX UNITS NOTES
Temperature Conversion t
9-bit resolution 93.75 ms 1
CONV
Time 10-bit resolution 187.5 ms 1
11-bit resolution 375 ms 1
12-bit resolution 750 ms 1
Time to Strong Pullup
On
t
Start Convert T or
SPON
Copy Scratchpad
10 µs
Command Issued
Time Slot t
Recovery Time t
Write 0 Low Time r
Write 1 Low Time t
Read Data Valid t
Reset Time High t
Reset Time Low t
Presence Detect High t
Presence Detect Low t
Capacitance C
60 120 µs 1
SLOT
1 µs 1
REC
60 120 µs 1
LOW0
1 15 µs 1
LOW1
15 µs 1
RDV
480 µs 1
RSTH
480 960 µs 1,2
RSTL
PDHIGH
15 60 µs 1
60 240 µs 1
PDLOW
25 pF
IN/OUT
NOTES:
1. Refer to timing diagrams in Figure 17.
2. If t
> 960 µs, a power on reset may occur.
RSTL
TYPICAL PERFORMANCE CURVE Figure 16
DS18B20-PAR Typical Error Curve
0.5
0.4
0.3
0.2
0.1
0
0 10203040506070
-0.1
Thermometer Error (C)
-0.2
-0.3
-0.4
-0.5
Mean Error
Reference Temp (C)
+3σ Error
-3σ Error
18 of 19
TIMING DIAGRAMS Figure 17
DS18B20-PAR
19 of 19
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