Rainbow Electronics DS18B20-PAR User Manual

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DS18B20-PAR

1-Wire

Parasite-Power

Digital Thermomete

FEATURES

• Unique 1-wire interface requires only one

port pin for communication

• Derives power from data line (“parasite

power”)—does not need a local power supply

• Multi-drop capability simplifies distributed

temperature sensing applications

• Requires no external components

• ±0.5°C accuracy from –10°C to +85°C

• Measures temperatures from –55°C to

+100°C (–67°F to +212°F)

• Thermometer resolution is user-selectable

from 9 to 12 bits

• Converts temperature to 12-bit digital word in

750 ms (max.)

• User–definable non-volatile temperature

alarm settings

• Alarm search command identifies and

addresses devices whose temperature is outside of programmed limits (temperature alarm condition)

• Software compatible with the DS1822-PAR

• Ideal for use in remote sensing applications

(e.g., temperature probes) that do not have a local power source

PIN ASSIGNMENT

DALLAS 18B20P

2 3

GND

2 3

BOTTOM VIEW)

TO-92

DS18B20-PAR

PIN DESCRIPTION

GND - Ground DQ - Data In/Out NC - No Connect

DESCRIPTION

The DS18B20-PAR digital thermometer provides 9 to 12–bit centigrade temperature measurements and has an alarm function with nonvolatile user-programmable upper and lower trigger points. The DS18B20-PAR does not need an external power supply because it derives power directl y from the data line (“parasite power”). The DS18B20-PAR communicates over a 1-wire bus, which by definition requires only one data line (and ground) for communication with a central microprocessor. It has an operating temperature range of –55°C to +100°C and is accurate to ±0.5°C over a range of –10°C to +85°C.

Each DS18B20-PAR has a unique 64-bit identification code, which allows multiple DS18B20-PARs to function on the same 1–wire bus; thus, it is simple to use one microprocessor to control man y DS18B20PARs distributed over a large area. Applications that can benefit from this feature include HVAC environmental controls, temperature monitoring systems inside buildings, equipment or machiner y, and process monitoring and control systems.

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DETAILED PIN DESCRIPTIONS Table 1

PIN SYMBOL DESCRIPTION

DS18B20-PAR

1 GND

Ground.

2 DQ Data Input/Output pin. Open-drain 1-wire interface pin. Also provides power

to the device when used in parasite power mode (see “Parasite Power” section.)

3 NC No Connect. Doesn’t connect to internal circuit.

OVERVIEW

The DS18B20-PAR uses Dallas’ exclusive 1-wire bus protocol that implements bus communication using one control signal. The control line requires a weak pullup resistor since all devices are linked to the bus via a 3-state or open-drain port (the DQ pin in the case of the DS18 B20-PAR). In this bus system, the microprocessor (the master device) identifies and addresses devices on the bus using each device’s unique 64-bit code. Because each device has a unique code, the number of devices that can be addressed on one bus is virtually unlimited. The 1-wire bus protocol, including detailed explanations of the commands and “time slots,” is covered in the 1-WIRE BUS SYSTEM section of this datasheet.

An important feature of the DS18B20-PAR is its ability to operate without an external power supply. Power is instead supplied through the 1-wire pullup resistor via the DQ pin when the bus is high. The high bus signal also charges an internal capacitor (CPP), which then supplies power to the device when the bus is low. This method of deriving power from the 1-wire bus is referred to as “parasite power.”

Figure 1 shows a block diagram of the DS18B20-PAR, and pin descriptions are given in Table 1. The 64-bit ROM stores the device’s unique serial code. The scratchpad memory contains the 2-byte temperature register that stores the digital output from the temperature sensor. In addition, the s crat chpad provides access to the 1-byte upper and lower alarm trigger registers (TH and TL). The TH and T

registers are nonvolatile (EEPROM), so they will retain their data when the device is powered down.

DS18B20-PAR BLOCK DIAGRAM Figure 1

4.7K

VPU

GND

PARASITE POWER

CIRCUIT

INTERNAL VDD

CPP

64-BIT ROM

AND

1-wire PORT

MEMORY CONTROL

LOGIC

SCRATCHPAD

DS18B20-PAR

TEMPERATURE SENSOR

ALARM HIGH TRIGGER (T

ALARM LOW TRIGGER (TL)

CONFIGURATION REGISTER

(EEPROM)

8-BIT CRC GENERATOR

)

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DS18B20-PAR

PARASITE POWER

The DS18B20-PAR’s parasite power circuit allows the DS18B20-PAR to operate without a local external power supply. This ability is especially useful for applications that require remote temper ature s ensing or that are very space constrained. Fi gure 1 shows the DS18B20-PAR’s parasite-power control cir cuitry, which “steals” power from the 1-wire bus via the DQ pin when the bus is high. The stolen charge powers the DS18B20-PAR while the bus is high, and some of the charge is stored on the parasite power capacitor (CPP) to provide power when the bus is low.

The 1-wire bus and CPP can provide sufficient parasite power to the DS18B20-PAR for most operations as long as the specified timing and voltage requirements are met (refer to the DC ELECTRICAL CHARACTERISTICS and the AC ELECTRICAL CHARACTERISTICS sections of this data sheet). However, when the DS18B20-PAR is performing temperature conversions or copying data from the scratchpad memory to EEPROM, the operating current can be as high as 1.5 mA. This current can cause an unacceptable voltage drop across the weak 1-wire pullup resistor and is more current than can be supplied by C

. To assure that the DS18B20-PAR has sufficient supply current, it is necessary to

provide a strong pullup on the 1-wire bus whenever temperature conversi ons are taking place or data is being copied from the scratchpad to EEPROM. This can be accomplished by using a MOSFET to pull the bus directly to the rail as shown in Figure 2. The 1-wire bus must be switched to the strong pullup within 10 µs (max) after a Convert T [44h] or Copy Scratchpad [48h] command is issued, and the bus must be held high by the pullup for the duration of the conversion (t

) or data transfer (t

conv

= 10 ms).

No other activity can take place on the 1-wire bus while the pullup is enabled.

SUPPLYING THE DS18B20-PAR DURING TEMPERATURE CONVERSIONS

Figure 2

Micro-

processor

VPU

4.7K

VPU

1-Wire Bus

DS18B20-PA

GND

To Other 1-Wire Devices

OPERAT ION – ME ASURING TEMPERATURE

The core functionality of the DS18B20-PAR is its direct-to-digital temperature sensor. The resolution of the temperature sensor is user-configurable to 9, 10, 11, or 12 bits, which corresponds to increments of

0.5°C, 0.25°C, 0.125°C, and 0.0625°C, respectively. The default resolution at power-up is 12-bit. The DS18B20-PAR powers-up in a low-power idle state; to initiate a temperature measurement and A-to-

D conversion, the master must issue a Convert T [44h] command. Following the conversion, the resulting thermal data is stored in the 2-byte temperature register in the scratchpad memory and the DS18B20-PAR returns to its idle state. The DS18B20-PAR output data is calibrated in degrees centigrade; for Fahrenheit applications, a lookup table or conversion routine must be used. The temperature data is stored as a 16-bit sign-extended two’s complement number in the temperature register (see Figure 3). The sign bits (S) indicate if the temperature is positive or negative: for positive numbers S = 0 and for negative numbers S = 1. If the DS18B20-PAR is configured for 12-bit resolution, all bits in the temperature register will contain valid data. For 11-bit resolution, bit 0 is undefined. For 10-bit 3 of 19

DS18B20-PAR

resolution, bits 1 and 0 are undefined, and for 9-bit resolution bits 2, 1 and 0 are undefined. Table 2 gives examples of digital output data and the corresponding temperature reading for 12-bit resolution conversions.

TEMPERATURE REGISTER FORMAT Figure 3

LS Byte

MS Byte

bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

23 2

bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8

S S S S S 26 2

-1

-2

-3

-4

TEMPERATURE/DATA RELATIONSHIP Table 2

TEMPERATURE DIGITAL OUTPUT

(Binary)

DIGITAL OUTPUT

(Hex)

+85°C* 0000 0101 0101 0000 0550h

+25.0625°C 0000 0001 1001 0001 0191h

+10.125°C 0000 0000 1010 0010 00A2h

+0.5°C 0000 0000 0000 1000 0008h

0°C 0000 0000 0000 0000 0000h

-0.5°C 1111 1111 1111 1000 FFF8h

-10.125°C 1111 1111 0101 1110 FF5Eh

-25.0625°C 1111 1110 0110 1111 FE6Fh

-55°C 1111 1100 1001 0000 FC90h

*The power-on reset value of the temperature register is +85°C

OPERAT ION – ALARM SIGNALING

After the DS18B20-PAR performs a temperature conversion, the temperature valu e is compared to the user-defined two’s complement alarm trigger values stored in the 1-byte TH and TL registers (see Figure

4). The sign bit (S) indicates if the value is positive or negative: for positive numbers S = 0 and for negative numbers S = 1. The T when the device is powered down. T explained in the MEMORY section of this datasheet.

and TL registers are nonvolatile (EEPROM) so they will retain data

and TL can be accessed through b ytes 2 and 3 of the scratchp ad as

TH AND TL REGISTER FORMAT Figure 4

bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 b it 0

S 26 2

Only bits 11 through 4 of the temperature register are used in t he TH and TL comparison since TH and T are 8-bit registers. If the result of a temperature measurement is higher than TH or lower than TL, an alarm condition exists and an alarm flag is set inside the DS18B20-PAR. This flag is updated after every temperature measurement; therefore, if the alarm condition goes away, the flag will be turned off after the next temperature conversion.

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DS18B20-PAR

The master device can check th e alarm flag status of all DS DS18B20-PARs on the bus by issui ng an Alarm Search [ECh] command. Any DS18B20-PARs with a set alarm flag will respond to the command, so the master can determine exact ly which DS18B20-PARs have experien ced an alarm condition. If an alarm condition exists and the TH or TL settings have changed, another temperature conversion should be done to validate the alarm condition.

64-BIT LASERED ROM CODE

Each DS18B20-PAR contains a unique 64–bit code (see Figure 5) stored in ROM. The least significant 8 bits of the ROM code contain the DS18B20-PAR’s 1–wire family code: 28h. The nex t 48 bits contain a unique serial number. The most significant 8 bits contain a cyclic redundancy check (CRC) byte that is calculated from the first 56 bits of the ROM code. A detailed explanation of the CRC bits is provided in the CRC GENERATION section. The 64–bit ROM code and associated ROM function control logic allow the DS18B20-PAR to operate as a 1–wire device using the protocol detailed in the 1-WIRE BUS SYSTEM section of this datasheet.

64-BIT LASERED ROM CODE Figure 5

8-BIT CRC 48-BIT SERIAL NUMBER 8-BIT FAMILY CODE (28h)

MSB MSB LSB LSB LSBMSB

MEMORY

The DS18B20-PAR’s memory is organized as shown in Figure 6. The memory consists of an SRAM scratchpad with nonvolatile EEPROM storage for the high and low alarm trigger registers (TH and TL) and configuration register. Note that if the DS18B20-PAR alarm function is not used, the TH and TL registers can serve as general-purpose memory. All memory commands are described in detail in the DS18B20-PAR FUNCTION COMMANDS section.

Byte 0 and byte 1 of the scratchpad contain the LSB and the MSB of the temperature register, respectively. These bytes are read-onl y. Bytes 2 and 3 provide access to TH and TL registers. Byte 4 contains the configuration register data, which is explained in detail in the CONFIGURATION REGISTER section of this datasheet. Bytes 5, 6 and 7 ar e reserved for internal use by the device and cannot be overwritten; these bytes will return all 1s when read.

Byte 8 of the scratchpad is read-only and contains the cyclic redundancy check (CRC) code for bytes 0 through 7 of the scratchpad. The DS18B20-PAR generates this CRC using the method described in the CRC GENERATION section.

Data is written to bytes 2, 3, and 4 of the scratchpad using the W rite Scratchpad [4Eh] command, and the data must be transmitted to the DS18B20-PAR starting with the least significant bit of byte 2. To verify data integrity, the scratchpad can be read (using the Read Scratchpad [BEh] command) after the data is written. When reading the scratchpad, data is transferred over the 1-wire bus starting with the least significant bit of byte 0. To transfer the T the master must issue the Copy Scratchpad [48h] command.

, TL and configuration data from the scratchpad to EEPROM,

Data in the EEPROM registers is retained when the device is powered down; at power-up the EEPROM data is reloaded into the corresponding scratchpad locations. Data can also be reloaded from EEPROM to the scratchpad at any time using the Recall E2 [B8h] command. The master can issue “read time slots” (see the 1-WIRE BUS SYS TEM section) following the R ecall E2 command and the DS18B20-PAR will indicate the status of the recall by transmitting 0 while the recall is in progress and 1 when the recall is done.

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DS18B20-PAR

DS18B20-PAR MEMORY MAP cбЦмкЙ=S

SCRATCHPAD (Power-up State)

byte 0 Temperature LSB (50h)

(85°C)

byte 1 Temperature MSB (05h)

EEPROM

byte 2 TH Register or User Byte 1* TH Register or User Byte 1 byte 3 TL Register or User Byte 2* TL Register or User Byte 2 byte 4 Configuration Register* Configuration Register byte 5 Reserved (FFh) byte 6 Reserved (0Ch) byte 7 Reserved (10h) byte 8 CRC*

*Power-up state depends on value(s) stored

in EEPROM

CONFIGURATION REGISTER

Byte 4 of the scratchpad memory contains the configuration register, which is organized as illustrated in Figure 7. The user can set the conversion resolution of the DS18B20-PAR using the R0 and R1 bits in this register as shown in Table 3. The power-up default of these bits is R0 = 1 and R1 = 1 (12-bit resolution). Note that there is a direct tradeoff between resolution and conversion time. Bit 7 and bits 0-4 in the configuration register are reserved for internal use b y the device and cannot be overwritten; these bits will return 1s when read.

CONFIGURATION REGISTER Figure 7

bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

0 R1 R0 1 1 1 1 1

THERMOMETER RESOLUTION CONFIGURATION Table 3

R1 R0 Resolution Max Conversion Time

0 0 9-bit 93.75 ms (t 0 1 10-bit 187.5 ms (t 1 0 11-bit 375 ms (t 1 1 12-bit 750 ms (t

CONV CONV CONV

CONV

/8) /4) /2)

)

CRC GENERATION

CRC bytes are provided as part of the DS18B20-PAR’s 64-bit ROM code and in the 9th byte of the scratchpad memory. The ROM code CRC is calculated from the first 56 bits of the ROM code and is contained in the most significant byte of the ROM. The scratchpad CRC is calculated from the data stored in the scratchpad, and therefore i t changes when the data in the scratchpad chan ges. The CRCs provide the bus master with a method of data validation when data is read from the DS18B20-PAR. To

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