Rainbow Electronics DS1876 User Manual
19-5153; Rev 0; 2/10
SFP Controller with Dual LDD Interface
General Description
The DS1876 controls and monitors all functions for
dual transmitter modules. The memory map is based
on SFF-8472. The DS1876 supports APC and modulation control and eye safety functionality for two laser
drivers. It continually monitors for high output current,
high bias current, and low and high transmit power to
ensure that laser shutdown for eye safety requirements
are met without adding external components. Six ADC
channels monitor VCC, temperature, and four external
monitor inputs that can be used to meet all monitoring
requirements.
Applications
Dual Tx Video SFP Modules
Ordering Information
PART TEMP RANGE PIN-PACKAGE
DS1876T+
DS1876T+T&R
+Denotes a lead(Pb)-free/RoHS-compliant package.
T&R = Tape and reel.
*EP = Exposed pad.
-40NC to +95NC
-40NC to +95NC
28 TQFN-EP*
28 TQFN-EP*
Features
S Meets All SFF-8472 Transmitter Control and
Monitoring Requirements
S Six Analog Monitor Channels: Temperature, V
PMON1, BMON1, PMON2, BMON2
PMON_ and BMON_ Support Internal and
External Calibration
Scalable Dynamic Range
Internal Direct-to-Digital Temperature Sensor
Alarm and Warning Flags for All Monitored
Channels
S Six Quick Trips for Fast Monitoring of Critical
Functions for Laser Safety
S Four 10-Bit Delta-Sigma Outputs
Each Controlled by 72-Entry Temperature
Lookup Table (LUT)
S Digital I/O Pins: Six Inputs, Five Outputs
S Comprehensive Fault Measurement System with
Maskable Laser Shutdown Capability
S Flexible, Two-Level Password Scheme Provides
Three Levels of Security
S 256 Additional Bytes Located at A0h Slave
Address
S Transmitter 1 is Accessed at A2h Slave Address
S Transmitter 2 is Accessed at B2h Slave Address
2
S I
C-Compatible Interface
S +2.85V to +3.9V Operating Voltage Range
S -40NC to +95NC Operating Temperature Range
S 28-Pin TQFN (5mm x 5mm x 0.8mm) Package
CC
DS1876
,
_______________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
SFP Controller with Dual LDD Interface
TABLE OF CONTENTS
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
MOD_, APC_ Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
DS1876
Analog Quick-Trip Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Analog Voltage Monitoring Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Digital Thermometer Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Quick-Trip Timing Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
I2C AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Nonvolatile Memory Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Typical Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Typical Operating Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
DACs During Power-Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
DACs as a Function of Transmit Disable (TXD1, TXD2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Quick-Trip Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Monitors and Fault Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Monitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Six Quick-Trip Monitors and Alarms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Six ADC Monitors and Alarms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
ADC Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Right-Shifting ADC Result . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Low-Voltage Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Delta-Sigma Outputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Digital I/O Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
IN1, RSEL, OUT1, RSELOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
TXF1, TXF2, TXFOUT, TXD1, TXD2, TXDOUT1, TXDOUT2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Transmit Fault (TXFOUT) Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Die Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
I2C Communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
I2C Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
I2C Protocol. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2 ______________________________________________________________________________________
SFP Controller with Dual LDD Interface
TABLE OF CONTENTS (continued)
Memory Organization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Shadowed EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Memory Map Access Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Memory Addresses A0h, A2h, and B2h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Lower Memory Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 01h Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 02h Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 04h Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 05h Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 06h Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Auxiliary Memory A0h Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Lower Memory Register Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 01h Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 02h Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 04h Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Table 06h Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Auxiliary Memory A0h Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Applications Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Power-Supply Decoupling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
SDA and SCL Pullup Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Package Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
DS1876
_______________________________________________________________________________________ 3
SFP Controller with Dual LDD Interface
LIST OF FIGURES
Figure 1. Power-Up Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 2. TXD1, TXD2 Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 3. Quick-Trip Sample Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 4. ADC Round-Robin Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
DS1876
Figure 5. Low-Voltage Hysteresis Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 6. Recommended RC Filter for DAC Outputs in Voltage Mode and Current Sink Mode . . . . . . . . . . . . . . . . . 16
Figure 7. 3-Bit (8-Position) Delta-Sigma Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 8. DAC OFFSET LUTs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 9. Logic Diagram 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 10. Logic Diagram 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 11a. TXFOUT Nonlatched Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 11b. TXFOUT Latched Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 12. I2C Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 13. Example I2C Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 14. Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
LIST OF TABLES
Table 1. Acronyms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 2. ADC Default Monitor Full-Scale Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4 ______________________________________________________________________________________
SFP Controller with Dual LDD Interface
ABSOLUTE MAXIMUM RATINGS
Voltage Range on PMON_, BMON_, RSEL,
IN1, TXF_, and TXD_ Pins
Relative to Ground ...............................-0.5V to (VCC + 0.5V)*
Voltage Range on VCC, SDA, SCL,
OUT1, RSELOUT, and TXFOUT Pins
Relative to Ground ...............................................-0.5V to +6V
*Subject to not exceeding +6V.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
(TA = -40NC to +95NC, unless otherwise noted.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Main Supply Voltage V
High-Level Input Voltage
(SDA, SCL)
Low-Level Input Voltage
(SDA, SCL)
High-Level Input Voltage
(TXD_, TXF_, RSEL, IN1)
Low-Level Input Voltage
(TXD_, TXF_, RSEL, IN1)
V
V
V
V
CC
IH:1
IL:1
IH:2
IL:2
(Note 1) +2.85 +3.9 V
Continuous Power Dissipation
28-Pin TQFN (derate 34.5mW/°C) above +70°C ....2758.6mW
Operating Temperature Range .......................... -40NC to +95NC
Programming Temperature Range ....................... 0NC to +95NC
Storage Temperature Range ............................ -55NC to +125NC
Soldering Temperature .........................Refer to the IPC/JEDEC
J-STD-020 Specification.
0.7 x
V
CC
-0.3
2.0
-0.3 +0.8 V
VCC +
0.3
0.3 x
V
CC
VCC +
0.3
V
V
V
DS1876
DC ELECTRICAL CHARACTERISTICS
(VCC = +2.85V to +3.9V, TA = -40NC to +95NC, unless otherwise noted.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Supply Current I
Output Leakage (SDA, OUT1,
RSELOUT, TXFOUT)
Low-Level Output Voltage
(SDA, OUT1, RSELOUT,
TXDOUT_, MOD_, APC_,
TXFOUT)
High-Level Output Voltage
(MOD_, APC_, TXDOUT_)
TXDOUT_ Before EEPROM
Recall
MOD_, APC_ Before Recall Figure 1 10 100 nA
Input Leakage Current
(SCL, TXD_, RSEL, IN1, TXF_)
Digital Power-On Reset POD 1.0 2.2 V
Analog Power-On Reset POA 2.0 2.75 V
_______________________________________________________________________________________ 5
CC
I
LO
V
OL
V
OH
I
LI
(Notes 1, 2) 2.5 10 mA
1
IOL = 4mA 0.4
IOL = 6mA 0.6
IOH = 4mA
VCC -
0.4
10 100 nA
1
FA
V
V
FA
SFP Controller with Dual LDD Interface
MOD_, APC_ ELECTRICAL CHARACTERISTICS
(VCC = +2.85V to +3.9V, TA = -40NC to +95NC, unless otherwise noted.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Main Oscillator Frequency f
Delta-Sigma Input-Clock
Frequency
DS1876
Reference Voltage Input (REFIN) V
Output Range 0 V
Output Resolution
Output Impedance R
OSC
f
DS
REFIN
DS
Minimum 0.1FF to GND
See the Delta-Sigma Outputs section for
details
2 V
ANALOG QUICK-TRIP CHARACTERISTICS
(VCC = +2.85V to +3.9V, TA = -40NC to +95NC, unless otherwise noted.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
TXP HI, TXP LO Full-Scale
Voltage
HBIAS Full-Scale Voltage 1.25 V
PMON_ Input Resistance 35 50 65
Resolution 8 Bits
Error
Integral Nonlinearity -1 +1 LSB
Differential Nonlinearity -1 +1 LSB
Temperature Drift -2.5 +2.5 %FS
Offset -5 +10 mV
TA = +25°C ±2
5 MHz
f
/2 MHz
OSC
CC
REFIN
10 Bits
35 100
2.507 V
V
V
I
kW
%FS
ANALOG VOLTAGE MONITORING CHARACTERISTICS
(VCC = +2.85V to +3.9V, TA = -40NC to +95NC, unless otherwise noted.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
ADC Resolution 13 Bits
Input/Supply Accuracy
(BMON_, PMON_, VCC)
Update Rate for Temperature,
BMON_, PMON_, VCC
Input/Supply Offset
(BMON_, PMON_, VCC)
Factory Setting (Note 4)
6 ______________________________________________________________________________________
ACC At factory setting 0.25 0.5 %FS
t
RR
V
OS
(Note 3) 0 5 LSB
BMON_, PMON_ 2.5
VCC 6.5536
64 78 ms
V
SFP Controller with Dual LDD Interface
DIGITAL THERMOMETER CHARACTERISTICS
(VCC = +2.85V to +3.9V, TA = -40NC to +95NC, unless otherwise noted.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Thermometer Error T
ERR
AC ELECTRICAL CHARACTERISTICS
(VCC = +2.85V to +3.9V, TA = -40NC to +95NC, unless otherwise noted.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
TXD_ Enable t
Recovery from TXD_ Disable
(Figure 2)
Fault Reset Time (to TXFOUT = 0)
Fault Assert Time (to TXFOUT = 1) t
OFF
t
ON
t
INITR1
t
INITR2
FAULT
QUICK-TRIP TIMING CHARACTERISTICS
(VCC = +2.85V to +3.9V, TA = -40NC to +95NC, unless otherwise noted.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Output-Enable Time Following POA t
Sample Time per Quick-Trip
Comparison
-40NC to +95NC
From ↑ TXD_
From ↓ TXD_
From ↓ TXD_
On power-up or ↓ TXD_, when VCC LO
alarm is detected (Note 5)
After HTXP_, LTXP_, HBATH_ 1.6 10.5
INIT
t
REP
-3 +3
131
161
20 ms
1.6
NC
5
1 ms
Fs
ms
Fs
Fs
DS1876
I2C AC ELECTRICAL CHARACTERISTICS
(VCC = +2.85V to +3.9V, TA = -40NC to +95NC, timing referenced to V
Communication section.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
SCL Clock Frequency f
Clock Pulse-Width Low t
Clock Pulse-Width High t
Bus Free Time Between STOP and
START Condition
START Hold Time t
START Setup Time t
Data Out Hold Time t
Data In Setup Time t
Rise Time of Both SDA and SCL
Signals
Fall Time of Both SDA and SCL
Signals
STOP Setup Time t
Capacitive Load for Each Bus Line C
EEPROM Write Time t
_______________________________________________________________________________________ 7
HIGH
t
HD:STA
SU:STA
HD:DAT
SU:DAT
SU:STO
SCL
LOW
BUF
t
t
WR
(Note 6) 0 400 kHz
0.6
(Note 7)
R
(Note 7)
F
B
(Note 8) 20 ms
IL(MAX)
and V
, unless otherwise noted. See the I2C
IH(MIN)
1.3
0.6
1.3
0.6
0 0.9
100 ns
20 +
0.1C
20 +
0.1C
0.6
B
B
300 ns
300 ns
400 pF
Fs
Fs
Fs
Fs
Fs
Fs
Fs
SFP Controller with Dual LDD Interface
NONVOLATILE MEMORY CHARACTERISTICS
(VCC = +2.85V to +3.9V, unless otherwise noted.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
EEPROM Write Cycles
DS1876
Note 1: All voltages are referenced to ground. Current into the IC is positive, and current out of the IC is negative.
Note 2: Inputs are at supply rail. Outputs are not loaded.
Note 3: This parameter is guaranteed by design.
Note 4: Full scale is user programmable.
Note 5: A temperature conversion is completed and MOD1 DAC, MOD2 DAC, APC1 DAC, and APC2 DAC values are recalled
from the LUT and VCC has been measured to be above VCC LO alarm, if the VCC LO alarm is enabled.
Note 6: I2C interface timing shown is for fast-mode (400kHz) operation. This device is also backward compatible with I2C stan-
dard mode.
Note 7: CB—Total capacitance of one bus line in pF.
Note 8: EEPROM write begins after a STOP condition occurs.
At +25NC
At +85NC
200,000
50,000
8 ______________________________________________________________________________________
SFP Controller with Dual LDD Interface
Typical Operating Characteristics
(V
CC
= 3.3V, T
= +25°C, unless otherwise noted.)
A
DS1876
SUPPLY CURRENT vs. SUPPLY VOLTAGE
2.7
SDA = SCL = V
DACs AT 1FFh
2.6
2.5
2.4
2.3
SUPPLY CURRENT (mA)
2.2
2.1
2.0
2.850
CC
+95°C
+25°C
VCC (V)
APC1/2 AND MOD1/2 DAC DNL
1.0
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
APC1/2 AND MOD1/2 DAC DNL (LSB)
-0.8
-1.0
0
DAC POSITION (DEC)
-40°C
SUPPLY CURRENT vs. TEMPERATURE
3.0
DAC POSITIONS = 1FFh
2.9
DS1876 toc01
3.7503.4503.150
SDA = SCL = V
2.8
2.7
2.6
VCC = 3.3V
2.5
2.4
2.3
SUPPLY CURRENT (mA)
2.2
VCC = 2.85V
2.1
2.0
-40 85
CC
VCC = 3.9V
TEMPERATURE (°C)
DS1876 toc02
603510-15
APC1/2 AND MOD1/2 DAC INL
3
DS1876 toc03
1000500
2
1
0
-1
APC1/2 AND MOD1/2 DAC INL (LSB)
-2
-3
0
DAC POSITION (DEC)
DS1876 toc04
1000500
1.0
PMON1/2 AND BMON1/2 DNL
USING FACTORY-PROGRAMMED FULL-SCALE
0.8
VALUE OF 2.5V
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
PMON1/2 AND BMON1/2 DNL (LSB)
-0.8
-1.0
0 2.5
PMON1/2 AND BMON1/2 INPUT VOLTAGE (V)
1.0
DS1876 toc05
2.01.51.00.5
0.8
0.6
0.4
0.2
-0.2
-0.4
-0.6
PMON1/2 AND BMON1/2 INL (LSB)
-0.8
-1.0
PMON1/2 AND BMON1/2 INL
USING FACTORY-PROGRAMMED FULL-SCALE
VALUE OF 2.5V
0
0 2.5
PMON1/2 AND BMON1/2 INPUT VOLTAGE (V)
2.01.51.00.5
DS1876 toc06
_______________________________________________________________________________________ 9
SFP Controller with Dual LDD Interface
Pin Configuration
TOP VIEW
MOD2
MOD1
GND
2021 19 17 16 15
GND
18
CC
TXDOUT2
V
N.C.
DS1876
IN1
TXD1
14
13
12
11
10
9
8
BMON1
PMON1
BMON2
PMON2
TXDOUT1
RSEL
GND
CC
External Monitor Input BMON1
and HBATH1 Quick Trip
Power-Supply Input
Reference Input for DAC1 and
DAC2
Digital Output. General-purpose
output, AS1 output in SFF-8079,
or RS1 output in SFF-8431.
REFIN
22
TXD2
23
24
APC2
25
APC1
V
TXF2
OUT1
26
CC
27
28
1 2
RSELOUT
DS1876
+
3
SCL
SDA
*EP
4 5 6 7
TXF1
TXFOUT
THIN QFN
(5mm
× 5mm × 0.8mm)
*EXPOSED PAD.
Pin Description
PIN NAME FUNCTION
1 RSELOUT Rate-Select Output
2 SCL I2C Serial-Clock Input
3 SDA I2C Serial-Data Input/Output
4 TXFOUT
Transmit Fault Output, Open
Drain
5 TXF1 Transmit Fault Input 1
Digital Input. General-purpose
6 IN1
input, AS1 in SFF-8079, or RS1
in SFF-8431.
7 TXD1 Transmit Disable Input 1
8, 18, 21 GND Ground Connection
9 RSEL Rate-Select Input
10 TXDOUT1 Transmit Disable Output 1
11 PMON2
12 BMON2
13 PMON1
External Monitor Input PMON2
and HTXP2/LTXP2 Quick Trip
External Monitor Input BMON2
and HBATH2 Quick Trip
External Monitor Input PMON1
and HTXP1/LTXP1 Quick Trip
PIN NAME FUNCTION
14 BMON1
15 N.C. No Connection
16, 26 V
17 TXDOUT2 Transmit Disable Output 2
19 MOD2 MOD2 DAC, Delta-Sigma Output
20 MOD1 MOD1 DAC, Delta-Sigma Output
22 REFIN
23 TXD2 Transmit Disable Input 2
24 APC2 APC2 DAC, Delta-Sigma Output
25 APC1 APC1 DAC, Delta-Sigma Output
27 TXF2 Transmit Fault Input 2
28 OUT1
— EP Exposed Pad (Connect to GND)
10 _____________________________________________________________________________________
SFP Controller with Dual LDD Interface
Block Diagram
DS1876
V
SDA
SCL
V
BMON1
PMON1
BMON2
PMON2
TXD1
TXD2
TXF1
V
CC
CC
I2C
INTERFACE
EEPROM
256 BYTES
AT A0h
CC
ANALOG MUX
TEMPERATURE
SENSOR
MAIN MEMORY
EEPROM/SRAM
A/D CONFIGURATION/RESULTS,
SYSTEM STATUS/CONTROL BITS,
ALARMS/WARNINGS,
LOOKUP TABLES,
USER MEMORY
13-BIT
ADC
8-BIT
QTs
POWER-ON
ANALOG
INTERRUPT
LOGIC
CONTROL
MOD2 DAC
APC2 DAC
MOD1 DAC
APC1 DAC
V
CC
V
CC
10 BITS
10 BITS
10 BITS
10 BITS
REFIN
MOD2
APC2
MOD1
APC1
TXFOUT
TXDOUT1
TXF2
RSEL
LOGIC
CONTROL
IN1
DS1876
TXDOUT2
RSELOUT
OUT1
GND
______________________________________________________________________________________ 11
SFP Controller with Dual LDD Interface
Typical Operating Circuit
TOSA2
DS1876
R
P1
TOSA1
RC FILTERS
(FIGURE 6)
R
B1
LDD2
BMON
APCIN
APCSET
MODSET
LDD1
BMON
APCIN
APCSET
MODSET
MOD1
DAC
APC1
DAC
MOD2
DAC
APC2
DAC
BMON1
PMON1
BMON2
PMON2
R
R
B1
P2
DS1876
EEPROM
QUICK
TRIP
ADC
FAULT
DISABLE
FAULT
DISABLE
TXF1
TXF2
TXFOUT
TXDOUT1
TXDOUT2
TXD1
TXD2
SDA
I2C
SCL
TX_FAULT
TX_DISABLE1
TX_DISABLE2
MODE_DEF2 (SDA)
MODE_DEF1 (SCL)
Detailed Description
The DS1876 integrates the control and monitoring functionality required in a dual transmitter system. Key components of the DS1876 are shown in the Block Diagram
and described in subsequent sections.
DACs During Power-Up
On power-up, the DS1876 sets the DACs to high impedance. After time t
, the DACs are set to an initial condition
INIT
set in EEPROM. After a temperature conversion is completed and if the VCC LO alarm is enabled, an additional
VCC conversion above the customer-defined VCC LO
alarm level is required before the DACs are updated with
the value determined by the temperature conversion and
the DAC LUT.
If a fault is detected, and TXD1 and TXD2 are toggled
to re-enable the outputs, the DS1876 powers up following a similar sequence to an initial power-up. The
12 _____________________________________________________________________________________
SFP Controller with Dual LDD Interface
Table 1. Acronyms
ACRONYM DESCRIPTION
ADC Analog-to-Digital Converter
AGC Automatic Gain Control
APC Automatic Power Control
APD Avalanche Photodiode
ATB Alarm Trap Bytes
DAC Digital-to-Analog Converter
LOS Loss of Signal
LUT Lookup Table
NV Nonvolatile
QT Quick Trip
TE Tracking Error
TIA Transimpedance Amplifier
ROSA Receiver Optical Subassembly
SEE Shadowed EEPROM
SFF Small Form Factor
SFF-8472
SFP Small Form Factor Pluggable
SFP+ Enhanced SFP
TOSA Transmit Optical Subassembly
TXP Transmit Power
Document Defining Register Map of SFPs
and SFFs
only difference is that the DS1876 already has determined the present temperature, so the t
time is not
INIT
required for the DS1876 to recall the APC and MOD
set points from EEPROM. See Figure 1.
DACs as a Function of Transmit Disable
(TXD1, TXD2)
If TXD1 or TXD2 are asserted (logic 1) during normal
operation, the associated outputs are disabled within
t
. When TXD1 or TXD2 are deasserted (logic 0), the
OFF
DS1876 sets the DACs with the value associated with
the present temperature. When asserted, soft TXD1 or
soft TXD2 (TXDC) (Lower Memory, Register 6Eh) would
allow a software control identical to the TXD1 or TXD2 pin
(Figure 2). The POLARITY register (Table 02h, Register
C6h) determines if the off-state value of the DACs is
V
or 0V.
REFIN
Quick-Trip Timing
As shown in Figure 3, the DS1876’s input comparator is shared among the six quick-trip alarms (TXP1
HI, TXP1 LO, TXP2 HI, TXP2 LO, BIAS1 HI, and BIAS2
HI). The comparator polls the alarms in a multiplexed
sequence. The updates are used to compare the HTXP1,
LTXP1, HTXP2, and LTXP2 (monitor diode voltages) and
the HBATH1 and HBATH2 (BMON1, BMON2) signals
against the internal APC and BIAS reference, respectively. Depending on the results of the comparison, the
DS1876
V
CC
DAC
SETTINGS
Figure 1. Power-Up Timing
Figure 2. TXD1, TXD2 Timing
______________________________________________________________________________________ 13
V
POA
500µs
HIGH IMPEDANCE OFF STATE LUT VALUE
TXD_
DAC
SETTINGS
LUT VALUE LUT VALUEOFF STATE
t
INIT
t
OFF
t
ON
SFP Controller with Dual LDD Interface
QT CYCLE
QUICK-TRIP SAMPLE TIMES
DS1876
Figure 3. Quick-Trip Sample Timing
LTXP2
SAMPLE
HBIAS1
SAMPLE
t
REP
HBIAS2
SAMPLE
HTXP1
SAMPLE
HTXP2
SAMPLE
LTXP1
SAMPLE
LTXP2
SAMPLE
HBIAS1
SAMPLE
Table 2. ADC Default Monitor Full-Scale Ranges
SIGNAL (UNITS) +FS SIGNAL +FS HEX -FS SIGNAL -FS HEX
Temperature (NC)
VCC (V) 6.5528 FFF8 0 0000
PMON1, PMON2 and BMON1, BMON2 (V) 2.4997 FFF8 0 0000
corresponding alarms and warnings (TXP HI1, TXP LO1,
TXP HI2, TXP LO2, BIAS HI1, and BIAS HI2) are asserted
or deasserted.
After resetting, the device completes one QT cycle
before making comparisons. The TXP LO quick-trip
alarm updates its alarm bit, but does not create FETG
until after TXD
figured to wait for TXD
. TXP HI and BIAS HI can also be con-
EXT
; however, this can be disabled
EXT
using QTHEXT_ (Table 02h, Register 88h).
Monitors and Fault Detection
Monitoring functions on the DS1876 include six quicktrip comparators and six ADC channels. This monitoring
combined with the alarm enables (Table 01h/05h) determines when/if the DS1876 turns off DACs and triggers
the TXFOUT and TXDOUT1, TXDOUT2 outputs. All the
monitoring levels and interrupt masks are user programmable.
Six Quick-Trip Monitors and Alarms
Six quick-trip monitors are provided to detect potential
laser safety issues and LOS status. These monitor the
following:
1) High Bias Current 1 (HBATH1), causing QT BIAS1 HI
2) Low Transmit Power 1 (LTXP1), causing QT TXP1 LO
3) High Transmit Power 1 (HTXP1), causing QT TXP1 HI
4) High Bias Current 2 (HBATH2), causing QT BIAS2 HI
5) Low Transmit Power 2 (LTXP2), causing QT TXP2 LO
6) High Transmit Power 2 (HTXP2), causing QT TXP2 HI
127.996 7FFF -128 8000
The high and low transmit power quick-trip registers
(HTXP1, HTXP2, LTXP1, and LTXP2) set the thresholds
used to compare against the PMON1 and PMON2 voltages to determine if the transmit power is within specification. The HBATH1 and HBATH2 QTs compare the
BMON1 and BMON2 inputs (generally from the laser
driver’s bias monitor output) against their threshold settings to determine if the present bias current is above
specification. The bias and power QTs are routed to
FETG through interrupt masks to allow combinations
of these alarms to be used to trigger FETG. The bias
Monitors
and power QTs are directly connected to TXFOUT (see
Figure 9). The user can program up to eight different
temperature-indexed threshold levels for HBATH1 and
HBATH2 (Table 06h, Registers E0h-E7h).
Six ADC Monitors and Alarms
The ADC monitors six channels that measure temperature (internal temp sensor), VCC, PMON1, PMON2,
BMON1, and BMON2 using an analog multiplexer to
measure them round-robin with a single ADC (see the
ADC Timing section). The channels have a customerprogrammable full-scale range, and all channels have a
customer-programmable offset value that is factory programmed to a default value (see Table 2). Additionally,
PMON1, PMON2 and BMON1, BMON2 can right-shift
results by up to 7 bits before the results are compared
to alarm thresholds or read over the I2C bus. This allows
customers with specified ADC ranges to calibrate the
ADC full scale to a factor of 1/2n of their specified range
to measure small signals. The DS1876 can then rightshift the results by n bits to maintain the bit weight of their
specification.
14 _____________________________________________________________________________________
SFP Controller with Dual LDD Interface
The ADC results (after right-shifting, if used) are compared to the alarm and warning thresholds after each
conversion, and the corresponding alarms are set that
can be used to trigger the TXFOUT output. These ADC
thresholds are user programmable, as are the masking
registers that can be used to prevent the alarms from triggering the TXFOUT output.
ADC Timing
There are six analog channels that are digitized in a
round-robin fashion in the order as shown in Figure 4.
The total time required to convert all six channels is tRR
(see the Analog Voltage Monitoring Characteristics table
for details).
Right-Shifting ADC Result
If the weighting of the ADC digital reading must conform
to a predetermined full-scale (PFS) value defined by
a standard’s specification (e.g., SFF-8472), then rightshifting can be used to adjust the PFS analog measurement range while maintaining the weighting of the ADC
results. The DS1876’s range is wide enough to cover all
requirements; when the maximum input value is P 1/2
the FS value, right-shifting can be used to obtain greater
accuracy. For instance, the maximum voltage might be
1/8 the specified PFS value, so only 1/8 of the converter’s
range is effective over this range. An alternative is to calibrate the ADC’s full-scale range to 1/8 the readable PFS
value and use a right-shift value of 3. With this implementation, the resolution of the measurement is increased by
a factor of 8, and because the result is digitally divided
by 8 by right-shifting, the bit weight of the measurement
still meets the standard’s specification (i.e., SFF-8472).
The right-shift operation on the ADC result is carried
out based on the contents of right-shift control registers
(Table 02h, Registers 8Eh-8Fh) in EEPROM. Four analog
channels—PMON1, PMON2, BMON1, and BMON2—
each have 3 bits allocated to set the number of right-
shifts. Up to seven right-shift operations are allowed and
DS1876
are executed as a part of every conversion before the
results are compared to the high and low alarm levels, or
loaded into their corresponding measurement registers
(Lower Memory, Registers 64h–6Bh). This is true during
the setup of internal calibration as well as during subsequent data conversions.
Low-Voltage Operation
The DS1876 contains two power-on reset (POR) levels.
The lower level is a digital POR (POD) and the higher
level is an analog POR (POA). At startup, before the supply voltage rises above POA, the outputs are disabled,
all SRAM locations are set to their defaults, shadowed
EEPROM (SEE) locations are zero, and all analog circuitry is disabled. When VCC reaches POA, the SEE is
recalled, and the analog circuitry is enabled. While VCC
remains above POA, the device is in its normal operating
state, and it responds based on its nonvolatile configuration. If during operation VCC falls below POA, but is
still above POD, the SRAM retains the SEE settings from
the first SEE recall, but the device analog is shut down
and the outputs disabled. If the supply voltage recovers
back above POA, the device immediately resumes normal operation. If the supply voltage falls below POD, the
device SRAM is placed in its default state and another
SEE recall is required to reload the nonvolatile settings.
The EEPROM recall occurs the next time VCC next
exceeds POA. Figure 5 shows the sequence of events
as the voltage varies.
Any time VCC is above POD, the I2C interface can be
used to determine if VCC is below the POA level. This
is accomplished by checking the RDYB bit in the status
byte (Lower Memory, Register 6Eh). RDYB is set when
VCC is below POA; when VCC rises above POA, RDYB
is timed (within 500Fs) to go to 0, at which point the part
is fully functional.
ONE ROUND-ROBIN ADC CYCLE
TEMP V
NOTE: IF THE VCC LO ALARM IS ENABLED AT POWER-UP, THE ADC ROUND-ROBIN TIMING CYCLES BETWEEN TEMPERATURE AND VCC ONLY UNTIL VCC IS ABOVE THE VCC LO
ALARM THRESHOLD. THIS ALSO OCCURS IF THERE ARE BOTH A TXD1 EVENT AND A TXD2 EVENT UNDER THE SAME CONDITIONS AS PREVIOUSLY MENTIONED.
Figure 4. ADC Round-Robin Timing
______________________________________________________________________________________ 15
BMON1 BMON2 PMON1 PMON2 TEMP
CC
t
RR
SFP Controller with Dual LDD Interface
SEE RECALL
V
POA
V
CC
SEE RECALL
DS1876
V
POD
PRECHARGED
SEE RECALLED VALUE RECALLED VALUE
TO 0
Figure 5. Low-Voltage Hysteresis Example
3.24kΩ 3.24kΩ
DAC
0.01µF 0.01µF
DS1876
1kΩ 1kΩ
DAC
0.1µF 0.1µF
DS1876
Figure 6. Recommended RC Filter for DAC Outputs in Voltage
Mode and Current Sink Mode
For all device addresses sourced from EEPROM (Table
02h, Register 8Bh), the default device addresses are
A2h and B2h until VCC exceeds POA allowing the device
address to be recalled from the EEPROM.
Delta-Sigma Outputs
Four delta-sigma outputs are provided: MOD1, MOD2,
APC1, and APC2. With the addition of an external RC
filter, these outputs provide 10-bit resolution analog
outputs with the full-scale range set by the input REFIN.
Each output is either manually controlled or controlled
using a temperature-indexed LUT.
PRECHARGED TO 0
VOLTAGE OUTPUT
CURRENT SINK
2kΩ
A delta-sigma DAC has a digital output using pulsedensity modulation. It provides much lower output ripple
than a standard digital PWM output given the same clock
rate and filter components. Before t
are high impedance. The external RC filter components
are chosen based on ripple requirements, output load,
delta-sigma frequency, and desired response time.
Figure 6 shows a recommended filter.
For illustrative purposes, a 3-bit example is provided in
Figure 7.
In LUT mode the DACs are each controlled by an LUT
with high-temperature resolution and an OFFSET LUT
with lower temperature resolution. The high-resolution
LUTs each have 2NC resolutions. The OFFSET LUTs
are located in the upper eight registers (F8h-FFh) of
the table containing each high-resolution LUT. The DAC
values are determined as follows:
DAC value = LUT + 4 x (OFFSET LUT)
An example calculation for MOD1 DAC is as follows:
Assumptions:
1) Temperature is +43NC
2) Table 04h (MOD1 OFFSET LUT), Register FCh = 2Ah
3) Table 04h (MOD1 LUT), Register AAh = 7Bh
Because the temperature is +43NC, the MOD1 LUT index
is AAh and the MOD1 OFFSET LUT index is FCh.
MOD1 DAC = 7Bh + 4 x 2Ah = 123h = 291
PRECHARGED
, the DAC outputs
INIT
TO 0
16 _____________________________________________________________________________________
SFP Controller with Dual LDD Interface
O
1
2
3
4
5
6
7
Figure 7. 3-Bit (8-Position) Delta-Sigma Example
DS1876
DAC OFFSET LUTs (04h/06h)[A2h/B2h]
EIGHT REGISTERS PER DAC
EACH OFFSET REGISTER CAN BE INDEPENDENTLY
1023
SET BETWEEN 0 AND 1020. 1020 = 4 x FFh. THIS
EXAMPLE ILLUSTRATES POSITIVE TEMPCO.
FCh
DAC
LUT
BITS
7:0
FDh
DAC
LUT
BITS
7:0
767
511
DELTA-SIGMA DACs
255
0
-40°C -8°C +8°C +24°C +40°C +56°C +70°C +88°C +104°C
F8h
DAC
LUT
BITS
7:0
F9h
DAC
LUT
BITS
7:0
FAh
DAC
LUT
BITS
7:0
FBh
DAC
LUT
BITS
7:0
FEh
DAC
LUT
BITS
7:0
FFh
DAC
LUT
BITS
7:0
Figure 8. DAC OFFSET LUTs
When temperature controlled, the DACs are updated
after each temperature conversion.
The reference input, REFIN, is the supply voltage for the
output buffer of all four DACs. The voltage connected to
DAC OFFSET LUTs (04h/06h)[A2h/B2h]
EIGHT REGISTERS PER DAC
EACH OFFSET REGISTER CAN BE INDEPENDENTLY SET BETWEEN
1023
0 AND 1020. 1020 = 4 x FFh. THIS EXAMPLE ILLUSTRATES POSITIVE
AND NEGATVE TEMPCO.
767
F8h
DAC
LUT
BITS
7:0
F9h
DAC
LUT
BITS
7:0
511
DELTA-SIGMA DACs
255
0
-40°C -8°C +8°C +24°C +40°C +56°C +70°C +88°C +104°C
FAh
DAC
LUT
BITS
7:0
FBh
DAC
LUT
BITS
7:0
FCh
DAC
LUT
BITS
7:0
FDh
DAC
LUT
BITS
7:0
FEh
DAC
LUT
BITS
7:0
FFh
DAC
LUT
BITS
7:0
REFIN and its decoupling must be able to support the
edge rate requirements of the delta-sigma outputs. In
a typical application, a 0.1FF capacitor should be connected between REFIN and ground.
______________________________________________________________________________________ 17
SFP Controller with Dual LDD Interface
V
CC
R
PU
TXD_
TXDC_
DS1876
TXP_ HI FLAG
TXP HI ENABLE
HBAL_ FLAG
HBAL ENABLE
TXDS_
R
C
Q
C
Q
D
S
SET BIAS_ DAC AND
MOD_ DAC TO HIGH
IMPEDANCE
FETG_
TXD_
TXDIO_
TXDFG_
TXDFLT_
TXDOUT_
TXFOUTS_
QTHEXT_
TXP_ LO FLAG
TXP LO ENABLE
FAULT RESET TIMER
TXD
(t
)
EXT
INITR1
(130ms)
OUT IN
IN
OUT
Figure 9. Logic Diagram 1
IN1S OUT1
INVOUT1
IN1C
IN1
INVRSOUT
RSELS
RSELC
RSEL
= PINS
RSELOUT
Figure 10. Logic Diagram 2
Digital I/O Pins
Six digital input pins and five digital output pins are provided for monitoring and control.
IN1, RSEL, OUT1, RSELOUT
Digital input pins IN1 and RSEL primarily serve to meet
the rate-select requirements of SFP and SFP+. They
can also serve as general-purpose inputs. OUT1 and
RSELOUT are driven by a combination of the IN1, RSEL,
and logic dictated by control registers in the EEPROM
(see Figure 10). The levels of IN1 and RSEL can be
read from the STATUS register (Lower Memory, Register
6Eh). The open-drain output OUT1 can be controlled
and/or inverted using the CNFGB register (Table 02h,
TXFINT
TXFOUTS1
TXFOUTS2
POWER-ON
RESET
INVTXF_
TXF_
NOTE:
_ CAN BE EITHER 1 OR 2 CORRESPONDING TO TRANSMITTERS 1 OR 2.
REFERS TO A PIN.
TXFS_
Register 89h). The open-drain RSELOUT output is
software controlled and/or inverted through the STATUS
register and CNFGA register (Table 02h, Register 88h).
External pullup resistors must be provided on OUT1 and
RSELOUT to realize high logic levels.
TXF1, TXF2, TXFOUT, TXD1, TXD2,
TXDOUT1, TXDOUT2
TXDOUT1 and TXDOUT2 are generated from a combination of TXF1, TXF2, TXD1, TXD2, and the internal
signals FETG1 and FETG2 (Table 02h, Register 8Ah). A
software control identical to TXD1 and TXD2 is also available (TXDC1 and TXDC2, Lower Memory, Register 6Eh).
A TXD1 or TXD2 pulse is internally extended (TXD
by time t
to inhibit the latching of low alarms and
INITR1
warnings related to the APC loop to allow for the loop to
stabilize. The nonlatching alarms and warnings are TXP
LO, BMON1 LO, BMON2 LO, PMON1 LO, and PMON2
LO. In addition, TXP LO is disabled from creating FETG.
See the Transmit Fault (TXFOUT) Output section for a
detailed explanation of TXFOUT. As shown in Figure 9,
the same signals and faults can also be used to generate the internal signal FETG. FETG is used to send a fast
“turn-off” command to the laser driver. The intended use
is a direct connection to the laser driver’s TXD1, TXD2
input if this is desired. When VCC < POA, TXDOUT1 and
TXDOUT2 are high impedance.
TXFOUT
EXT
)
18 _____________________________________________________________________________________
SFP Controller with Dual LDD Interface
DETECTION OF TXFOUT FAULT
TXFOUT
Figure 11a. TXFOUT Nonlatched Operation
DETECTION OF TXFOUT FAULT
TXD_ OR TXFOUT RESET
TXFOUT
Figure 11b. TXFOUT Latched Operation
DS1876
Transmit Fault (TXFOUT) Output
TXFOUT can be triggered by all alarms, warnings, QTs,
TXD1, TXD2, TXF1, and TXF2 (see Figure 9). The six
ADC alarms and warnings are controlled by enable bits
(Table 01h/05h, Registers F8h and FCh). See Figures
11a and 11b for nonlatched and latched operation for
TXFOUT. The CNFGB register (Table 02h, Register 89h)
controls the latching of the alarms.
Die Identification
The DS1876 has an ID hardcoded in its memory. Two
registers (Table 02h, Registers 86h-87h) are assigned
for this feature. Register 86h reads 76h to identify the
part as the DS1876; Register 87h reads the present
device version.
I2C Communication
I2C Definitions
The following terminology is commonly used to describe
I2C data transfers.
Master Device: The master device controls the slave
devices on the bus. The master device generates SCL
clock pulses and START and STOP conditions.
Slave Devices: Slave devices send and receive data
at the master’s request.
Bus Idle or Not Busy: Time between STOP and
START conditions when both SDA and SCL are inactive and in their logic-high states.
START Condition: A START condition is generated
by the master to initiate a new data transfer with a
slave. Transitioning SDA from high to low while SCL
remains high generates a START condition. See
Figure 12 for applicable timing.
STOP Condition: A STOP condition is generated
by the master to end a data transfer with a slave.
Transitioning SDA from low to high while SCL remains
high generates a STOP condition. See Figure 12 for
applicable timing.
Repeated START Condition: The master can use
a repeated START condition at the end of one data
transfer to indicate that it will immediately initiate a
new data transfer following the current one. Repeated
STARTs are commonly used during read operations
to identify a specific memory address to begin a data
transfer. A repeated START condition is issued identically to a normal START condition. See Figure 12 for
applicable timing.
Bit Write: Transitions of SDA must occur during the
low state of SCL. The data on SDA must remain valid
and unchanged during the entire high pulse of SCL
plus the setup and hold time requirements (Figure 12).
Data is shifted into the device during the rising edge
of the SCL.
Bit Read: At the end of a write operation, the master
must release the SDA bus line for the proper amount
of setup time (Figure 12) before the next rising edge
______________________________________________________________________________________ 19
SFP Controller with Dual LDD Interface
of SCL during a bit read. The device shifts out each
bit of data on SDA at the falling edge of the previous
SCL pulse and the data bit is valid at the rising edge
of the current SCL pulse. Remember that the master
generates all SCL clock pulses, including when it is
reading bits from the slave.
DS1876
Acknowledgement (ACK and NACK): An acknowledgement (ACK) or not-acknowledge (NACK) is
always the 9th bit transmitted during a byte transfer.
The device receiving data (the master during a read
or the slave during a write operation) performs an ACK
by transmitting a zero during the 9th bit. A device performs a NACK by transmitting a one during the 9th bit.
Timing (Figure 12) for the ACK and NACK is identical
to all other bit writes. An ACK is the acknowledgment
that the device is properly receiving data. A NACK is
used to terminate a read sequence or as an indication
that the device is not receiving data.
Byte Write: A byte write consists of 8 bits of information transferred from the master to the slave (most
significant bit first) plus a 1-bit acknowledgement from
the slave to the master. The 8 bits transmitted by the
master are done according to the bit write definition
and the acknowledgement is read using the bit read
definition.
Byte Read: A byte read is an 8-bit information transfer
from the slave to the master plus a 1-bit ACK or NACK
from the master to the slave. The 8 bits of information
that are transferred (most significant bit first) from the
slave to the master are read by the master using the
bit read definition, and the master transmits an ACK
using the bit write definition to receive additional data
bytes. The master must NACK the last byte read to
terminate communication so the slave returns control
of SDA to the master.
Slave Address Byte: Each slave on the I2C bus
responds to a slave address byte sent immediately
following a START condition. The slave address byte
contains the slave address in the most significant 7 bits
and the R/W bit in the least significant bit.
The DS1876 responds to three slave addresses. The
auxiliary memory always responds to a fixed I2C slave
address, A0h. (If the main device’s slave address
is programmed to be A0h, access to the auxiliary
memory is disabled.) The Lower Memory and Tables
00h–06h respond to I2C slave addresses whose lower
3 bits are configurable (A0h–AEh, B0h-BEh) using the
DEVICE ADDRESS byte (Table 02h, Register 8Bh). The
user also must set the ASEL bit (Table 02h, Register
88h) for this address to be active. By writing the correct slave address with R/W = 0, the master indicates
it writes data to the slave. If R/W = 1, the master reads
data from the slave. If an incorrect slave address is
written, the DS1876 assumes the master is communicating with another I2C device and ignores the communications until the next START condition is sent.
Memory Address: During an I2C write operation
to the DS1876, the master must transmit a memory
address to identify the memory location where the
slave is to store the data. The memory address is
SDA
t
BUF
t
LOW
SCL
t
HD:STA
STOP START REPEATED
NOTE: TIMING IS REFERENCED TO V
IL(MAX)
AND V
IH(MIN)
t
R
t
HD:DAT
.
t
HIGH
t
F
t
SU:DAT
START
t
SU:STA
t
HD:STA
t
SP
Figure 12. I2C Timing
20 _____________________________________________________________________________________
t
SU:STO
SFP Controller with Dual LDD Interface
always the second byte transmitted during a write
operation following the slave address byte.
I2C Protocol
See Figure 13 for an example of I2C timing.
Writing a Single Byte to a Slave: The master must
generate a START condition, write the slave address
byte (R/W = 0), write the memory address, write
the byte of data, and generate a STOP condition.
Remember that the master must read the slave’s
acknowledgement during all byte write operations.
Writing Multiple Bytes to a Slave: To write multiple
bytes to a slave, the master generates a START condition, writes the slave address byte (R/W = 0), writes
the memory address, writes up to 8 data bytes, and
generates a STOP condition. The DS1876 writes 1 to
8 bytes (one page or row) with a single write transaction. This is internally controlled by an address
counter that allows data to be written to consecutive
addresses without transmitting a memory address
before each data byte is sent. The address counter
limits the write to one 8-byte page (one row of the
memory map). Attempts to write to additional pages
of memory without sending a STOP condition between
pages result in the address counter wrapping around
to the beginning of the present row.
For example: A 3-byte write starts at address 06h and
DS1876
writes three data bytes (11h, 22h, and 33h) to three
“consecutive” addresses. The result is that addresses
06h and 07h would contain 11h and 22h, respectively, and the third data byte, 33h, would be written
to address 00h.
To prevent address wrapping from occurring, the
master must send a STOP condition at the end of
the page, then wait for the bus-free or EEPROM write
time to elapse. Then the master can generate a new
START condition and write the slave address byte
(R/W = 0) and the first memory address of the next
memory row before continuing to write data.
Acknowledge Polling: Any time a EEPROM page is
written, the DS1876 requires the EEPROM write time
(tWR) after the STOP condition to write the contents of
the page to EEPROM. During the EEPROM write time,
the DS1876 does not acknowledge its slave address
because it is busy. It is possible to take advantage
of that phenomenon by repeatedly addressing the
DS1876, which allows the next page to be written
as soon as the DS1876 is ready to receive the data.
The alternative to acknowledge polling is to wait for
maximum period of tWR to elapse before attempting
to write again to the DS1876.
2
TYPICAL I
C WRITE TRANSACTION
MSB LSB
START
X X X X 0 0 1 R/W
SLAVE
ADDRESS*
*IF ASEL IS 0, THE SLAVE ADDRESS IS A0h FOR THE AUXILIARY MEMORY AND A2h/B2h FOR THE MAIN MEMORY.
IF ASEL = 1, THE SLAVE ADDRESS IS DETERMINED BY TABLE 02h, REGISTER 8Bh FOR THE MAIN MEMORY. THE AUXILIARY MEMORY CONTINUES TO BE ADDRESSED AT A0h, EXCEPT WHEN THE PROGRAMMED
ADDRESS FOR THE MAIN MEMORY IS A0h.
2
EXAMPLE I
C TRANSACTIONS WITH A2h AS THE SLAVE ADDRESS
A)
SINGLE-BYTE WRITE
-WRITE 00h TO REGISTER BAh
B)
SINGLE-BYTE READ
-READ REGISTER BAh
C)
TWO-BYTE WRITE
-WRITE 01h AND 75h TO
REGISTERS C8h AND C9h
D)
TWO-BYTE READ
-READ C8h AND C9h
START STOP
START
START
START
READ/
WRITE
A2h
1 0 1 0 0 0 1 0
A2h
1 0 1 0 0 0 1 0
A2h
1 0 1 0 0 0 1 0
A2h
1 0 1 0 0 0 1 0
MSB LSB
SLAVE
b7 b6 b5 b4 b3 b2 b1 b0
ACK
REGISTER ADDRESS
SLAVE
ACK
SLAVE
ACK
SLAVE
ACK
SLAVE
ACK
BAh
1 0 1 1 1 0 1 0
BAh
1 0 1 1 1 0 1 0
C8h
1 1 0 0 1 0 0 0
C8h
1 1 0 0 1 0 0 0
SLAVE
ACK
SLAVE
ACK
SLAVE
ACK
SLAVE
ACK
00h
0 0 0 0 0 0 0 0
REPEATED
START
01h
0 0 0 0 0 0 0 1
REPEATED
START
SLAVE
ACK
A3h
1 0 1 0 0 0 1 1
SLAVE
ACK
A3h
1 0 1 0 0 0 1 1
MSB LSB
SLAVE
b7 b6 b5 b4 b3 b2 b1 b0
ACK
DATA
SLAVE
ACK
75h
0 1 1 1 0 1 0 1
SLAVE
ACK
DATA
DATA IN BAh
SLAVE
ACK
DATA
DATA IN C8h
MASTER
STOP
MASTER
NACK
ACK
STOP
DATA
DATA IN C9h
SLAVE
ACK
MASTER
NACK
Figure 13. Example I2C Timing
______________________________________________________________________________________ 21
STOP
STOP
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