Rainbow Electronics DS1875 User Manual
General Description
The DS1875 controls and monitors all functions for burstmode transmitters, APD receivers, and video receivers.
It also includes a power-supply controller for APD bias
generation, and provides all SFF-8472 diagnostic and
monitoring functionality. The combined solution of the
DS1875 and the MAX3643 laser driver provides APC
loop, modulation current control, and eye safety functionality. Ten ADC channels monitor V
CC
, temperature
(both internal signals), and eight external monitor inputs
(MON1–MON8) that can be used to meet transmitter,
digital receiver, video receiver, and APD receiver-signal
monitoring requirements. Four total DAC outputs are
available. A PWM controller with feedback and compensation pins can be used to generate the bias for an APD
or as a step-down converter. Five I/O pins allow additional monitoring and configuration.
Applications
BPON, GPON, or EPON Optical Triplexers
SFF, SFP, and SFP+ Transceiver Modules
APD Controller
Features
♦ Meets All PON Burst-Timing Requirements for
Burst-Mode Operation
♦ Laser Bias Controlled by APC Loop and
Temperature Lookup Table (LUT)
♦ Laser Modulation Controlled by Temperature LUT
♦ Six Total DACs: Four External, Two Internal
♦ Two 8-Bit DACs, One of Which is Optionally
Controlled by MON4 Voltage
♦ Internal 8-Bit DAC Controlled by a Temperature-
Indexed LUT
♦ PWM Controller
♦ Boost or Buck Mode
♦ Boost Mode: Uses Optional External
Components, Up to 90V Bias Generation
♦ 131kHz, 262kHz, 525kHz, or 1050kHz Selectable-
Switching Frequency
♦ APD Overcurrent Protection Using Optional Fast
Shutdown
♦ 10 Analog Monitor Channels: Temperature, V
CC
,
Eight Monitors
♦ Internal, Factory-Calibrated Temperature Sensor
♦ RSSI with 29dB Electrical Dynamic
♦ Five I/O Pins for Additional Control and
Monitoring Functions, Four of Which are Either
Digital I/O or Analog Monitors
♦ Comprehensive Fault-Measurement System with
Maskable Laser Shutdown Capability
♦ Two-Level Password Access to Protect
Calibration Data
♦ 120 Bytes of Password-1 Protected Memory
♦ 128 Bytes of Password-2 Protected Memory in
Main Device Address
♦ 256 Additional Bytes Located at A0h Slave
Address
♦ I
2
C-Compatible Interface for Calibration and
Monitoring
♦ 2.85V to 3.9V Operating Voltage Range
♦ -40°C to +95°C Operating Temperature Range
♦ 38-Pin TQFN (5mm x 7mm) Package
DS1875
________________________________________________________________
Maxim Integrated Products
1
×
Pin Configuration
Ordering Information
Rev 1; 10/08
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
+
Denotes a lead-free/RoHS-compliant package.
T&R = Tape and reel.
*
EP = Exposed pad.
PON Triplexer and SFP Controller
PART TEMP RANGE PIN-PACKAGE
DS1875T+ -40°C to +95°C 38 TQFN-EP*
DS1875T+T&R -40°C to +95°C 38 TQFN-EP*
TOP VIEW
GND
GND
SW
V
N.C.
N.C.
N.C.
CC
V
31 30 29 28 27 26 25 24 23 22 21 20
32
33
34
35
CC
36
37
38
+
123456789101112
BEN
*EXPOSED PAD.
BMD
SDA
MOD
COMP
SCL
TX-F
(5mm
M4DAC
FB
BIAS
DS1875
N.C.
N.C.
FETG
TQFN
7mm × 0.8mm)
GND
TX-D
DAC1
CC
V
MON3P
GND
MON3N
*EP
N.C.
N.C.
LOSI
19
18
17
16
15
14
13
MON4
MON2
MON1
MON8/D3
MON7/D2
MON6/D1
MON5/D0
DS1875
2 _______________________________________________________________________________________
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Electrical Characteristics (DAC1 and M4DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Analog Input Characteristics (BMD, TXP HI, TXP LO, HBIAS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Analog Output Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
PWM Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Timing Characteristics (Control Loop and Quick Trip) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Analog Voltage Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Digital Thermometer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Nonvolatile Memory Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
I
2
C Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Typical Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Typical Operating Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Bias Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Autodetect Bias Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Open-Loop Bias Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Closed-Loop Bias Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
DC Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Modulation Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
BIAS and MOD Output During Power-Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
BIAS and MOD Output as a Function of Transmit Disable (TX-D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
APC and Quick-Trip Shared Comparator Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Monitors and Fault Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Monitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Power-On Analog (POA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Quick-Trip Monitors and Alarms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
MON3 Quick Trip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
ADC Monitors and Alarms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
ADC Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Right-Shifting ADC Result . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Transmit Fault (TX-F) Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Safety Shutdown (FETG) Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Determining Alarm Causes Using the I
2
C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
TABLE OF CONTENTS
PON Triplexer and SFP Controller
DS1875
_______________________________________________________________________________________ 3
Die Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Low-Voltage Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Enhanced RSSI Monitoring (Dual Range Functionality) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
PWM Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Inductor Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Stability and Compensation Component Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
DAC1 Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
M4DAC Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Digital I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
I
2
C Communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
I2C Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
I2C Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Shadowed EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Lower Memory Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Table 00h Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Table 01h Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Table 02h Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Table 03h Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Table 04h Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Table 05h Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Table 06h Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Table 07h Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Table 08h Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Auxiliary A0h Memory Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Lower Memory Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
Table 00h Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
Table 01h Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
Table 02h Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
Table 03h Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87
Table 04h Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87
Table 05h Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88
Table 06h Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
Table 07h Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
Table 08h Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91
TABLE OF CONTENTS (continued)
PON Triplexer and SFP Controller
DS1875
PON Triplexer and SFP Controller
4 _______________________________________________________________________________________
Auxiliary Memory A0h Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91
Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91
TABLE OF CONTENTS (continued)
Figure 1. Power-Up Timing (BEN is a Long Burst) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Figure 2. TX-D Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Figure 3. APC Loop and Quick-Trip Sample Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Figure 4. M3QT Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Figure 5. ADC Timing with EN5TO8B = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Figure 6. ADC Timing with EN5TO8B = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Figure 7. TX-F Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Figure 8. FETG/Output Disable Timing (Fault Condition Detected) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Figure 9. SEE Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Figure 10. RSSI Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Figure 11. PWM Controller Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Figure 12. PWM Controller Typical APD Bias Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Figure 13. PWM Controller Voltage Output Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Figure 14. PWM Controller Current-Sink Output Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Figure 15. I
2
C Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Figure 16. Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Table 1. DS1875 Acronyms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Table 2. Update Rate Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Table 3. ADC Default Monitor Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Table 4. TX-F as a Function of TX-D and Alarm Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Table 5. FETG, MOD, and BIAS Outputs as a Function of TX-D and Alarm Sources . . . . . . . . . . . . . . . . . . . . . . . . .22
Table 6. MON3 Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Table 7. MON3 Hysteresis Threshold Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
LIST OF FIGURES
LIST OF TABLES
DS1875
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Voltage Range on MON1–MON8,
BEN, BMD, and TX-D Pins
Relative to Ground .................................-0.5V to (V
CC
+ 0.5V)*
Voltage Range on V
CC
, SDA, SCL,
D0–D3, and TX-F Pins Relative to Ground...............-0.5V to 6V
Operating Temperature Range ...........................-40°C to +95°C
Programming Temperature Range .........................0°C to +85°C
Storage Temperature Range .............................-55°C to +125°C
Soldering Temperature...........................Refer to the IPC/JEDEC
J-STD-020 Specification.
AC ELECTRICAL CHARACTERISTICS
(VCC= +2.85V to +3.9V, TA= -40°C to +95°C, unless otherwise noted.)
*
Subject to not exceeding +6V.
RECOMMENDED OPERATING CONDITIONS
(TA= -40°C to +95°C, unless otherwise noted.)
ABSOLUTE MAXIMUM RATINGS
PON Triplexer and SFP Controller
_______________________________________________________________________________________ 5
Main Supply Voltage VCC (Note 1) +2.85 +3.9 V
High-Level Input Voltage
(SDA, SCL, BEN)
Low-Leve l Input Voltage
(SDA, SCL, BEN)
High-Level Input Voltage
(TX-D, LOSI, D0, D1, D2, D3)
Low-Leve l Input Voltage
(TX-D, LOSI, D0, D1, D2, D3)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
V
IH:1
V
-0.3
IL:1
V
2.0
IH:2
V
-0.3 +0.8 V
IL:2
0.7 x
V
CC
V
CC
0.3
0.3 x
V
CC
V
CC
0.3
+
V
V
+
V
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Supply Current ICC (Notes 1, 2) 5.5 10 mA
Output Leakage
(SDA, TX-F, D0, D1, D2, D3)
Low-Leve l Output Voltage
(SDA, TX-F, FETG, D0, D1, D2, D3)
High-Level Output Voltage
(FETG)
FETG Before Recall (Note 3) 10 100 nA
Input Leakage Current
(SCL, BEN, TX-D, LOSI)
Digital Power-On Reset POD 1.0 2.2 V
Analog Power-On Reset POA 2.1 2.75 V
I
(Note 2) 1 μA
LO
V
V
I
OH
LI:1
IOL = 4mA 0.4
OL
IOL = 6mA 0.6
V
-
IOH = 4mA
1 μA
CC
0.4
V
V
DS1875
PON Triplexer and SFP Controller
6 _______________________________________________________________________________________
ANALOG OUTPUT CHARACTERISTICS
(VCC= +2.85V to +3.9V, TA= -40°C to +95°C, unless otherwise noted.)
ANALOG INPUT CHARACTERISTICS (BMD, TXP HI, TXP LO, HBIAS)
(VCC= +2.85V to +3.9V, TA= -40°C to +95°C, unless otherwise noted.)
ELECTRICAL CHARACTERISTICS (DAC1 AND M4DAC)
(VCC= +2.85V to +3.9V, TA= -40°C to +95°C, unless otherwise noted.)
DAC Output Range 2.5 V
DAC Output Resolution 8 Bits
DAC Output Integral Nonlinearity -1 +1 LSB
DAC Output Differential
Nonlinearity
DAC Error TA = +25°C -1.25 +1.25 %FS
DAC Temperature Drift -2 +2 %FS
DAC Offset -12 +12 mV
Max imum Load -500 +500 μA
Maximum Load Capacitance 250 pF
BMD, TXP HI, TXP LO Full-Scale
Voltage
HBIAS Full-Scale Voltage (Note 5) 1.25 V
BMD Input Resistance 35 50 65 k
Resolution 8 Bits
Error TA = +25°C (Note 6) ±2 %FS
Integral Nonlinearity -1 +1 LSB
Differentia l Nonl inearit y -1 +1 LSB
Temperature Drift -2.5 +2.5 %FS
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
-1 +1 LSB
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
(Note 4) 2.5 V
V
APC
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
BIAS Current I
I
Shutdown Current I
BIAS
Voltage at I
MOD Full-Scale Voltage V
MOD Output Impedance (Note 7) 3 k
V
Error TA = +25°C (Note 8) -1.25 +1.25 %FS
MOD
V
Integral Nonlinearity -1 +1 LSB
MOD
V
Differentia l Nonl inearit y -1 +1 LSB
MOD
V
Temperature Drift -2 +2 %FS
MOD
0.7 1.2 1.4 V
BIAS
(Note 1) 1.2 mA
BIAS
BIAS:OFF
10 100 nA
(Note 5) 1.25 V
MOD
DS1875
TIMING CHARACTERISTICS (CONTROL LOOP AND QUICK TRIP)
(VCC= +2.85V to +3.9V, TA= -40°C to +95°C, unless otherwise noted.)
PWM CHARACTERISTICS
(VCC= +2.85V to +3.9V, TA= -40°C to +95°C, unless otherwise noted.)
PON Triplexer and SFP Controller
_______________________________________________________________________________________ 7
PWM-DAC Full-Scale Voltage V
PWM-DAC Resolution 8 Bit s
V
PWM-DAC
Error
V
PWM-DAC
V
PWM-DAC
Nonlinearity
V
PWM-DAC
SW Output Impedance 20
SW Frequency Error f
SW Dut y C ycle D
Error-Amplifier Source Current -10 μA
Error-Amplifier Sink Current +10 μA
COMP High-Voltage Clamp 2.1 V
COMP Low-Voltage Clamp 0.8 V
Error-Amplifier
Transconductance
Error-Amplifier Output
Impedance
FB Pin Capacitance 5 pF
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
PWM-DAC
Full-Scale Voltage
Integral Nonlinearity -1 1 LSB
Differential
Temperature Drift -2 +2 %FS
1.25 V
T
-1 1 LSB
SWER
MAX
G
M
260 M
R
EA
= +25°C 1.25 %
A
(Note 9) -5 +7 %
89 90 91 %
425 μS
First BMD Sample Following BEN t
Remaining Updates During BEN t
BEN High Time t
BEN Low Time t
Output-Enable Time Following POA t
BIAS and MOD Turn-Off Delay t
BIAS and MOD Turn-On Delay tON 5 μs
FETG Turn-On Delay t
FETG Turn-Off Delay t
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
(Note 10)
FIRST
(Note 10)
UPDATE
BEN:HIGH
BEN:LOW
FETG:ON
FETG:OFF
400 ns
96 ns
10 ms
INIT
5 μs
OFF
5 μs
5 μs
DS1875
PON Triplexer and SFP Controller
8 _______________________________________________________________________________________
NONVOLATILE MEMORY CHARACTERISTICS
(VCC= +2.85V to +3.9V, TA= -40°C to +95°C, unless otherwise noted.)
DIGITAL THERMOMETER
(VCC= +2.85V to +3.9V, TA= -40°C to +95°C, unless otherwise noted.)
ANALOG VOLTAGE MONITORING
(VCC= +2.85V to +3.9V, TA= -40°C to +95°C, unless otherwise noted.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
ADC Re solution 13 Bits
Input/Supply Accuracy
(MON1–MON8, V
Update Rate for Temp,
MON1–MON4, and V
Update Rate for MON5–MON8 t
Input/Supply Offset
(MON1–MON8, V
Factor y Setting
)
CC
CC
)
CC
MON1–MON8 2.5
V
CC
MON3 Fine
Thermometer Error T
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
ACC At factory sett ing 0.25 0.50 %FS
t
FRAME:1
FRAME:2
78 95 ms
Bit EN5TO8B is enabled in Table 02h,
Regi ster 89h
V
(Note 11) 0 5 LSB
OS
Ful l sca le s are user programmable
-40°C to +95°C ±3.0 °C
ERR
156 190 ms
6.5536
312.5 μV
V
EEPROM Write Cycles
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
At +85°C (Note 11) 50,000
At +25°C (Note 11) 200,000
DS1875
Note 1: All voltages are referenced to ground. Current into IC is positive, and current out of the IC is negative.
Note 2: Digital inputs are at rail. FETG is disconnected. SDA = SCL = V
CC
. SW, DAC1, and M4DAC are not loaded.
Note 3: See the
Safety Shutdown (FETG) Output
section for details.
Note 4: Eight ranges allow the full scale to change from 625mV to 2.5V.
Note 5: Eight ranges allow the full scale to change from 312.5mV to 1.25V.
Note 6: This specification applies to the expected full-scale value for the selected range. See the COMP RANGING register
description for available full-scale ranges.
Note 7: The output impedance of the DS1875 is proportional to its scale setting. For instance, if using the 1/2 scale, the output
impedance would be approximately 1.56kΩ.
Note 8: This specification applies to the expected full-scale value for the selected range. See the MOD RANGING register
description for available full-scale ranges.
Note 9: The switching frequency is selectable between four values: 131.25kHz, 262.5kHz, 525kHz, and 1050kHz.
Note 10: See the
APC and Quick-Trip Shared Comparator Timing
section for details.
Note 11: Guaranteed by design.
Note 12: I
2
C interface timing shown is for fast-mode (400kHz) operation. This device is also backward compatible with I2C stan-
dard mode.
Note 13: C
B
—Total capacitance of one bus line in pF.
Note 14: EEPROM write begins after a STOP condition occurs.
I2C TIMING SPECIFICATIONS
(VCC= +2.85V to +3.9V, TA= -40°C to +95°C, timing referenced to V
IL(MAX)
and V
IH(MIN)
.) (See Figure 15.)
PON Triplexer and SFP Controller
_______________________________________________________________________________________ 9
SCL Clock Frequency f
Cloc k Pulse-Width Low t
Cloc k Pulse-Width High t
Bus-Free Time Between STOP
and START Condition
START Hold Time t
START Setup Time t
Data in Hold Time t
Data in Setup Time t
Capacitive Load for Each Bus Line CB 400 pF
Rise Time of Both SDA and SCL
Signals
Fal l Time of Both SDA and SCL
Signals
STOP Setup Time t
EEPROM Write Time tW (Note 14) 20 ms
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
(Note 12) 0 400 kH z
SCL
1.3 μs
LOW
0.6 μs
HIGH
t
1.3 μs
BUF
0.6 μs
HD: STA
0.6 μs
SU:STA
0 0.9 μs
HD:DAT
100 ns
SU:DAT
t
(Note 13)
R
t
(Note 13)
F
0.6 μs
SU:STO
20 +
0.1C
20 +
0.1C
300 ns
B
300 ns
B
DS1875
PON Triplexer and SFP Controller
10 ______________________________________________________________________________________
Typical Operating Characteristics
(VCC= +2.85V to +3.9V, TA= +25°C, unless otherwise noted.)
9.0
SDA = SCL = V
8.5
8.0
7.5
7.0
6.5
6.0
SUPPLY CURRENT (mA)
5.5
5.0
4.5
2.85
SUPPLY CURRENT vs. TEMPERATURE
V
CC
SW = 525kHz
SW = 262.5kHz
-40
(mA)
CC
I
8.8
8.6
8.4
8.2
8.0
7.8
7.6
7.4
SUPPLY CURRENT
vs. SUPPLY VOLTAGE
CC
+95°C
+25°C
-40°C
VCC (V)
= 5V, NO BIAS CURRENT
SW = 1050kHz
SW = 131.25kHz
TEMPERATURE (°C)
SUPPLY CURRENT
vs. TEMPERATURE
9.0
SDA = SCL = V
DS1875 toc01
3.853.35
8.5
8.0
7.5
7.0
6.5
6.0
SUPPLY CURRENT (mA)
5.5
5.0
4.5
-40
CC
VCC = 3.9V
VCC = 2.85V
TEMPERATURE (°C)
DS1875 toc02
806020 400-20
DAC1 AND M4DAC DNL
1.0
DS1875 toc04
806040200-20
0.8
0.6
0.4
0.2
0
-0.2
-0.4
DAC1 AND M4DAC DNL (LSB)
-0.6
-0.8
-1.0
0
DAC1 AND M4DAC POSITION (DEC)
DS1875 toc05
25020015010050
SUPPLY CURRENT vs. TEMPERATURE
V
= 3.3V, NO BIAS CURRENT
CC
SW = 1050kHz
SW = 525kHz
SW = 262.5kHz
SW = 131.25kHz
-40
TEMPERATURE (°C)
(mA)
CC
I
7.4
7.3
7.2
7.1
7.0
6.9
6.8
6.7
6.6
6.5
6.4
DAC1 AND M4DAC INL
1.0
0.8
0.6
0.4
0.2
0
-0.2
-0.4
DAC1 AND M4DAC INL (LSB)
-0.6
-0.8
-1.0
0
DAC1 AND M4DAC POSITION (DEC)
DS1875 toc03
806020 400-20
DS1875 toc06
25020015010050
DAC1 AND M4DAC OFFSET vs. V
0.05
TA = -40°C TO +95°C
0.04
LOAD = -0.5mA TO +0.5mA
0.03
0.02
0.01
0
-0.01
-0.02
DAC1 AND M4DAC OFFSET (mV)
-0.03
-0.04
-0.05
2.85
VCC (V)
DAC1 AND M4DAC OFFSET VARIATION
CC
3.853.653.453.253.05
0.0010
0.0008
DS1875 toc07
0.0006
0.0004
0.0002
0
-0.0002
-0.0004
DAC1 AND M4DAC OFFSET (mV)
-0.0006
-0.0008
-0.0010
-0.5 0.5
vs. LOAD CURRENT
VCC = 2.85V
VCC = 3.6V
VCC = 3.9V
LOAD CURRENT (mA)
1.259
DS1875 toc08
1.257
1.255
1.253
1.251
1.249
DAC1 AND M4DAC OUTPUT (V)
1.247
0.30.1-0.1-0.3
1.245
DAC1 AND M4DAC OUTPUT
vs. LOAD CURRENT
OUTPUT WITHOUT OFFSET
VCC = 2.85V
VCC = 3.9V
-0.5 0.5
LOAD CURRENT (mA)
DS1875 toc09
0.30.1-0.3 -0.1
DS1875
Typical Operating Characteristics (continued)
(VCC= +2.85V to +3.9V, TA= +25°C, unless otherwise noted.)
CALCULATED AND DESIRED % CHANGE
IN V
MOD
vs. MOD RANGING
DS1875 toc10
MOD RANGING VALUE (DEC)
CHANGE IN V
MOD
(%)
007006004 005002 003001
10
20
30
40
50
60
70
80
90
100
0
000
CALCULATED
VALUE
DESIRED
VALUE
DESIRED AND CALCULATED CHANGE
IN V
BMD
vs. COMP RANGING
DS1875 toc11
COMP RANGING (DEC)
CHANGE IN V
BMD
(%)
111110100 101010 011001
10
20
30
40
50
60
70
80
90
100
0
000
CALCULATED
VALUE
DESIRED
VALUE
MON1 TO MON8 INL
DS1875 toc12
MON1 TO MON8 INPUT VOLTAGE (V)
MON1 TO MON8 INL (LSB)
2.01.51.00.5
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1.0
-1.0
0 2.5
USING FACTORY-PROGRAMMED
FULL-SCALE VALUE OF 2.5V
MON1 TO MON8 DNL
DS1875 toc13
MON1 TO MON8 INPUT VOLTAGE (V)
MON1 TO MON8 DNL (LSB)
2.01.51.00.5
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1.0
-1.0
0 2.5
USING FACTORY-PROGRAMMED
FULL-SCALE VALUE OF 2.5V
V
BMD
INL vs. APC INDEX
DS1875 toc14
APC INDEX (DEC)
V
BMD
INL (LSB)
25020015010050
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1.0
-1.0
0
V
MOD
INL vs. MOD INDEX
DS1875 toc15
MOD INDEX (DEC)
V
MOD
INL (LSB)
25020015010050
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1.0
-1.0
0
FB VOLTAGE vs. TEMPERATURE
PWM DAC = FFh
DS1875 toc16
TEMPERATURE (°C)
V
OUT
(V)
806040200-20
1.245
1.250
1.255
1.260
1.240
-40
V
OUT
vs. V
CC
VIN = 3.3V
DS1875 toc17
VCC (V)
V
OUT
(V)
3.853.35
75.2
75.4
75.6
75.8
76.0
76.2
76.4
76.6
76.8
77.0
75.0
2.85
DUTY-CYCLE LIMIT vs. TEMPERATURE
DS1875 toc18
TEMPERATURE (°C)
V
OUT
(V)
8060-20 0 20 40
89.25
89.50
89.75
90.00
90.25
90.50
90.75
91.00
89.00
-40
SW FREQUENCY
525kHz
262.5kHz
131.25kHZ
1050kHz
PON Triplexer and SFP Controller
______________________________________________________________________________________
11
DS1875
PON Triplexer and SFP Controller
12 ______________________________________________________________________________________
μ
Typical Operating Characteristics (continued)
(VCC= +2.85V to +3.9V, TA= +25°C, unless otherwise noted.)
1.00
0.75
0.50
0.25
0
DAC DNL (LSB)
-0.25
-0.50
-0.75
-1.00
0 256
PWM DAC DNL
DAC SETTING (DEC)
1.00
0.75
0.50
0.25
0
DAC INL (LSB)
-0.25
-0.50
-0.75
-1.00
0 256
PWM DAC CHANGING FROM 00h TO 80h
20V/div
0V
200mV/div
0V
200mV/div
0V
R
COMP
V
FB
COMP
22419232 64 96 128 160
M3QT DAC INL
DAC SETTING (dec)
= 24.3kΩ, C
OUT
DUTY CYCLE
DS1875 toc19
5ms/div
1.00
PWM DAC INL
0.75
0.50
0.25
0
DAC INL (LSB)
-0.25
-0.50
-0.75
-1.00
0 256
DAC SETTING (DEC)
DS1875 toc22
22419232 64 96 128 160
= 220nF
COMP
DS1875 toc24
10%/div
0%
1V/div
10mA/div
0mA
5V/div
50V/div
100mA/div
0mA
100mV/div
1.00
0.75
DS1875 toc20
0.50
0.25
0
DAC DNL (LSB)
-0.25
-0.50
-0.75
-1.00
22419232 64 96 128 160
0 256
DAC SETTING (DEC)
SW CURRENT INTO BSS123 FET
M3QT DAC DNL
FREQUENCY = 1050kHz 50% DUTY CYCLE
SW
0V
SW
CURRENT
100ns/div
DS1875 toc23
SWITCHING WAVEFORMS
V
0V
0V
0V
= 3.3V, V
IN
V
OUT
RIPPLE (AC-COUPLED)
OUT
C2 = 0.1
INDUCTOR
VOLTAGE
INDUCTOR
CURRENT
~ 90V, I
2μs/div
OUT
F
~ 1.25mA,
DS1875 toc25
SW
DS1875 toc21
22419232 64 96 128 160
DS1875
PON Triplexer and SFP Controller
______________________________________________________________________________________ 13
Pin Description
PIN NAME FUNCTION
1 BEN Burst-Enable Input. Triggers the samp les for the APC and quick-trip monitors.
2 SDA I2C Serial-Data Input/Output
3 SCL I2C Serial-Clock Input
4 TX-F Transm it-Fault Output
5, 7, 11, 20,
36, 37, 38
6 FETG
8 TX-D Transmit-Disable Input. Disables analog outputs.
9, 31, 35 VCC Power-Supply Input (2.85V to 3.9V)
10, 24, 32, 33 GND Ground Connection
12 LOSI
13 MON5/D0
14, 15, 16
17, 18, 19
21, 22
23 DAC1 8-Bit DAC Output. Driven either by I2C interface or temperature-indexed LUT.
25 M4DAC
26 FB
27 BIAS Bias-Current Output. This 13-bit current output generates the bias current reference for the MAX3643.
28 MOD
29 COMP Compensation for Error Amplifier in PWM Controller
30 BMD Back Mon itor Diode Input (Feedback Voltage, Transmit Power Mon itor)
34 SW
— EP Exposed Pad
N.C. No Connection
FET Gate Output. Signals an external n-channel or p-channel MOSFET to enable/disable the
laser’s current.
Loss-of-Signal Input. Open-collector buffer for external loss-of-signal input. This input is
accessible in the statu s regi ster through the I
External Monitor Input 5 or Digita l I/O 0. This signal i s the open-collector output driver for IN. It
can also be control led by the MUX0 and OUT0 bit s. The voltage level of this pin can be read at
IN0. In analog input mode, the voltage at this pin is digitized by the internal 13-bit analog-todigital converter and can be read through the I
assigned to interrupt the processor based on the ADC result.
External Monitor Inputs 6, 7, and 8 or Digital I/O 1, 2, and 3. In digital mode, these open-collector
MON6/D1,
MON7/D2,
MON8/D3
MON1,
MON2,
MON4
MON3N,
MON3P
outputs are controlled by the OUTx bits, and their voltage level s can be read at the INx bits. In
analog input mode, the voltages at these pins are digitized by the internal 13-bit analog-to-digital
converter and can be read through the I
to interrupt the processor based on the ADC result. D2 i s configurable a s a quick-trip output for
MON3.
External Monitor Input 1, 2, and 4. The voltage at these pins is digitized by the internal 13-bit
analog-to-digital converter and can be read through the I
can be ass igned to interrupt the processor based on the ADC result.
External Monitor Input 3. This is a differentia l input that is digitized by the internal 13-bit ADC
and can be read through the I
the processor based on the ADC result. When used as a s ingle-ended input, connect MON3N to
ground.
8-Bit DAC Output for Generating Analog Voltage. Can be controlled by a LUT indexed by the
voltage applied to MON4.
Converter Feedback. Input to error amplifier. The other input to the error amplifier is an 8-bit DAC.
The DAC can be driven by a temperature-indexed LUT. The output of the error amplifier is the
input of the comparator used to create the PWM signal.
Modulation Output Voltage. This 8-bit vo ltage output has eight full-scale ranges from 1.25V to
0.3125V. This pin is connected to the MAX3643’s VMSET input to control the modulation current.
PWM Output. This is typically the switching node of a PWM converter. In conjunction with FB, a
boost converter, buck converter, or analog 8-bit output can be created.
2
C interface.
2
C interface. Alarm and warning values can be
2
C interface. Alarm and warning values can be assigned
2
C interface. Alarm and warning values
2
C interface. Alarm and warning values can be assigned to interrupt
DS1875
PON Triplexer and SFP Controller
14 ______________________________________________________________________________________
Block Diagram
V
CC
SDA
SCL
MON1
MON2
MON3N
MON3P
MON4
BEN
BMD
TX-D
MON5/D0
V
CC
2
C
I
INTERFACE
256 BYTES AT
V
CC
MON[5:8]
TEMP
SENSOR
SAMPLE
CONTROL
HBIAS
QUICK-TRIP LIMIT
HTXP
QUICK-TRIP LIMIT
LTXP
QUICK-TRIP LIMIT
APC SET POINT FROM
TRACKING-ERROR TABLE
MON5
EEPROM
A0h SLAVE
ADDRESS
DS1865 MEMORY ORGANIZATION
ADDITIONAL MONITORS
USER MEMORY, ALARM TRAP
CONFIGURATION AND CALIBRATION
13-BIT
ANALOG MUX
DAC WITH
MUX
SCALING
TTL
0
1
TTL
TABLE 00h (EEPROM)
TABLE 01h (EEPROM)
TABLE 02h (EEPROM)
TABLE 03h (EEPROM)
USER MEMORY
TABLE 04h (EEPROM)
MODULATION LUT
ADC
MUX
8-BIT
LOS STATUS/
D0 IN
D0 OUT
INV0
MAIN MEMORY
EEPROM/SRAM
ALARM/WARNING COMPARISONS
DIGITAL LIMIT
COMPARATOR FOR
ADC RESULTS
LUT CAN BE INDEXED BY
ADC CONFIGURATION/RESULTS
SYSTEM STATUS BITS
TABLE 05h (EEPROM)
ADC TE LUT
TABLE 06h (EEPROM)
M4DAC LUT
TABLE 07h (EEPROM)
PWM LUT
TABLE 08h (EEPROM)
BIAS OL LUT
INTERRUPT
INTERRUPT
BIAS MAX
QUICK TRIP
MUX
TABLE 07h
PWM VOLTAGE
TEMP SENSOR
MASK
MASK
DIGITAL
APC
INTEGRATOR
8-BIT
PWM-DAC
SRAM RESET
LATCH
ENABLE
TX-D INPUT
MOD LUT
POWER-ON ANALOG
> V
V
CC
POA
NONMASKABLE
INTERRUPT
INTERRUPT
LATCH
INTERRUPT
LATCH
TABLE 08h
BIAS OL LUT
TEMP INDEXED
MUX
8-BIT
DAC WITH
SCALING
PWM
13-BIT
DAC
TX-F
FETG
BIAS
MOD
SW
LOSI
MON6/D1
MON7/D2
MON8/D3
GND
MON6
MON7
MON8
TTL
TTL
0
1
TTL
TTL
MUX0
D1 IN
D1 OUT
D2 IN
D2 OUT
INV M3QT
M3QT
MUX2
D3 IN
D3 OUT
I2C CONTROL
DS1875
M4DAC LUT INDEXED BY MON4
TABLE 06h
2
C CONTROL
I
M4DAC
8-BIT, 2.5V
FULL SCALE
DAC1
8-BIT, 2.5V
FULL SCALE
COMP
FB
M4DAC
DAC1
DS1875
Typical Operating Circuit
PON Triplexer and SFP Controller
______________________________________________________________________________________ 15
I2C COMMUNICATION
FAULT OUTPUT
DISABLE INPUT
RECEIVER LOS
OPEN-DRAIN LOS OUTPUT
ADDITIONAL DIGITAL I/O
IN+
IN-
BEN+
BEN-
DIS
IMAX
GND
VMSET
MOD BIAS BEN
SDA
SCL
TX-F
TX-D
LOSI
D0
D3
MAX3643
MODSET
VREF
VBSET
BIASSET
M4DAC
V
CC
OUT+
OUT-
BIAS-
BIAS+
BENOUT
BCMON
BMD
MON1
MON2
MON3
MON4
FETG
D1
3.3V
3.3V
TRANSMIT POWER
RECEIVE POWER
CATV RF POWER
CATV SHUTDOWN CONTROL
MAX4003
MAX3654
FTTH CATV
TIA
RF DETECTOR
CATV
12V
GAIN CONTROL
ADDITIONAL MONITORS
MON[5:7]
COMP
DS1875
V
SW
GND
DAC1
MON8
CC
FB
APD OVERLOAD QUICK TRIP
D2
APD VOLTAGE MONITOR
VOLTAGE REFERENCE
OPTIONAL
R
AGC
MAX4007
CURRENT MONITOR
APD
3.3V
RECEIVE
POWER
(CURRENT)
ROSA
TIA
DS1875
PON Triplexer and SFP Controller
16 ______________________________________________________________________________________
Detailed Description
The DS1875 integrates the control and monitoring functionality required to implement a PON system using
Maxim’s MAX3643 compact burst-mode laser driver.
The compact laser-driver solution offers a considerable
cost benefit by integrating control and monitoring features in the low-power CMOS process, while leaving
only the high-speed portions to the laser driver. Key
components of the DS1875 are shown in the
Block
Diagram
and described in subsequent sections. Table
1 contains a list of acronyms used in this data sheet.
Bias Control
Bias current is controlled by an APC loop. The APC
loop uses digital techniques to overcome the difficulties
associated with controlling burst-mode systems.
Autodetect Bias Control
This is the default mode of operation. In autodetect bias
control, transmit burst length is monitored. A “short
burst” is declared when the burst is shorter than
expected based on the sample rate setting in Table
02h, Register 88h. In the case that 32 consecutive short
bursts are transmitted, the integrator is disabled and
the BIAS DAC is loaded from the BIAS LUT (Table 08h).
Any single burst of adequate burst length re-enables
the APC integrator.
Open-Loop Bias Control
Open-loop control is configured by setting FBOL in
Table 02h, Register C7h. In this mode, the BIAS LUT
(Table 08h) is directly loaded to the BIAS DAC output.
The BIAS LUT can be programmed in 2°C increments
over the 40°C to +102°C range. It is left-shifted so that
the LUT value is loaded to either the DAC MSB or the
DAC MSB-1 (Bit BOLFS, Table 02h, Register 89h).
Closed-Loop Bias Control
The closed-loop control requires a burst length long
enough to satisfy the sample rate settings in Table 02h,
Register 88h (APC_SR[3:0]). Closed-loop control is
configured by setting FBCL in Table 02h, Register C7h.
In this mode, the APC integrator is enabled, which controls the BIAS DAC.
The APC loop begins by loading the value from the
BIAS LUT (Table 08h) indexed by the present temperature conversion. The feedback for the APC loop is the
monitor diode (BMD) current, which is converted to a
voltage using an external resistor. The feedback voltage is compared to an 8-bit scaleable voltage reference, which determines the APC set point of the
system. Scaling of the reference voltage accommodates the wide range in photodiode sensitivities. This
allows the application to take full advantage of the APC
reference’s resolution.
The DS1875 has an LUT to allow the APC set point to
change as a function of temperature to compensate for
TE. The TE LUT (Table 05h) has 36 entries that determine the APC setting in 4°C windows between -40°C to
+100°C. Ranging of the APC DAC is possible by programming a single byte in Table 02h, Register 8Dh.
Table 1. DS1875 Acronyms
ACRONYM DEFINITION
10GEPON 10-Gigabit Ethernet PON
ADC Analog-to-Digital Converter
AGC Automatic Gain Control
APC Automatic Power Control
APD Avalanche Photodiode
BM Burst Mode
BPON Broadband PON
CATV Cable Televis ion
EPON Ethernet PON
ER Extinction Ratio
DAC Digital-to-Analog Converter
FTTH Fiber-to-the-Home
FTTX Fiber-to-the-X
GEPON Gigabit Ethernet PON
GPON Gigabit PON
LOS Loss of Signal
LUT Lookup Table
TE Track ing Error
TIA Transimpedance Amplif ier
ROSA Receiver Optical Subassembly
RSSI Receive Signal Strength Indicator
PON Passive Optical Network
PWM Pulse-Width Modulation
SFF Small Form Factor
SFF-8472
SFP Small Form Factor Pluggable
SFP+ Enhanced SFP
TOSA Transmit Optical Subassembly
Document Defining Register Map of
SFPs and SFFs
DS1875
DC Operation
When using autodetect mode or closed-loop mode,
BEN should be equal to VCCor long burst. In open-loop
mode, BEN should be ground or any burst length.
Modulation Control
The MOD output is an 8-bit scaleable voltage output
that interfaces with the MAX3643’s VMSET input. An
external resistor to ground from the MAX3643’s
MODSET pin sets the maximum current that the voltage
at the VMSET input can produce for a given output
range. This resistor value should be chosen to produce
the maximum modulation current the laser type requires
over temperature. Then the MOD output’s scaling is
used to calibrate the full-scale (FS) modulation output
to a particular laser’s requirements. This allows the
application to take full advantage of the MOD output’s
resolution. The modulation LUT can be programmed in
2°C increments over the -40°C to +102°C range.
Ranging of the MOD DAC is possible by programming
a single byte in Table 02h, Register 8Bh.
BIAS and MOD Output During Power-Up
On power-up the modulation and bias outputs remain off
until VCCis above V
POA
, a temperature conversion has
been completed, and, if the VCCADC alarm is enabled,
a V
CC
conversion above the customer-defined VCClow
alarm level must clear the VCClow alarm (t
INIT
). Once all
these conditions (t
INIT
) are satisfied, the MOD output is
enabled with the value determined by the temperature
conversion and the modulation LUT (Table 04h).
When the MOD output is enabled, the BIAS output is
turned on to a value equal to the temperature-indexed
value in the BIAS LUT (Table 08h). Next, the APC integrator is enabled, and single LSB steps are taken to
tightly control the average power.
If a fault is detected and TX-D is toggled to re-enable
the outputs, the DS1875 powers up following a similar
sequence to an initial power-up. The only difference is
that the DS1875 already determined the present temperature, so the t
INIT
time is not required for the
DS1875 to recall the APC and MOD set points from
EEPROM.
Figure 1. Power-Up Timing (BEN is a Long Burst)
PON Triplexer and SFP Controller
______________________________________________________________________________________ 17
V
V
CC
POA
t
INIT
V
MOD
BIAS LUT
VALUE
I
BIAS
BIAS
SAMPLE
12345678910111213
APC INTEGRATOR ON
DS1875
PON Triplexer and SFP Controller
18 ______________________________________________________________________________________
BIAS and MOD Output as a Function of
Transmit Disable (TX-D)
If the TX-D pin is asserted (logic 1) during normal operation, the outputs are disabled within t
OFF
. When TX-D
is deasserted (logic 0), the DS1875 turns on the MOD
output with the value associated with the present temperature and initializes the BIAS using the same search
algorithm used at startup. When asserted, the SOFT
TX-D bit (Lower Memory, Register 6Eh) offers a software control identical to the TX-D pin (see Figure 2).
APC and Quick-Trip Shared Comparator
Timing
As shown in Figure 3, the DS1875’s input comparator is
shared between the APC control loop and the three
quick-trip alarms (TXP HI, TXP LO, and BIAS HI). The
comparator polls the alarms in a multiplexed sequence.
Six of every eight comparator readings are used for
APC loop-bias current control. The other two updates
are used to check the HTXP/LTXP (monitor diode voltage) and the HBIAS (MON1) signals against the internal APC and BIAS reference. If the last APC
comparison was higher than the APC set point, it
makes an HTXP comparison, and if it is lower, it makes
an LTXP comparison. Depending on the results of the
comparison, the corresponding alarms and warnings
(TXP HI, TXP LO) are asserted or deasserted.
The DS1875 has a programmable comparator sample
time based on an internally generated clock to facilitate
a wide variety of external filtering options suitable for
burst-mode transmitters. The rising edge of BEN triggers the sample to occur, and the Update Rate register
(Table 02h, Register 88h) determines the sampling time.
The first sample occurs (t
FIRST
) after the rising edge of
BEN. The internal clock is asynchronous to BEN, causing a ±50ns uncertainty regarding when the first sample
will occur following BEN. After the first sample occurs,
subsequent samples occur on a regular interval, t
REP
.
Table 2 shows the sample rate options available.
Updates to the TXP HI and TXP LO quick-trip alarms do
not occur during the BEN low time. The BIAS HI quick
trip can be sampled during the burst-low time. Any
*
All codes greater than 1001b (1010b to 1111b) use the
maximum sample time of code 1001b.
Figure 3. APC Loop and Quick-Trip Sample Timing
Table 2. Update Rate Timing
Figure 2. TX-D Timing
TX-D
I
BIAS
V
MOD
t
OFF
t
OFF
t
ON
t
ON
MINIMUM TIME
FROM BEN TO
APC_SR[3:0]
0000b 350 800
0001b 550 1200
0010b 750 1600
0011b 950 2000
0100b 1350 2800
0101b 1550 3200
0110b 1750 3600
0111b 2150 4400
1000b 2950 6000
1001b* 3150 6400
FIRST SAMPLE
(t
) ±50ns
FIRST
(ns)
REPEATED
SAMPLE PERIOD
FOLLOWING FIRST
SAMPLE (t
(ns)
REP
)
t
BEN
APC QUICK-TRIP
SAMPLE TIMES
FIRST
t
REP
APC
SAMPLE
APC
SAMPLE
APC
SAMPLE
APC
SAMPLE
APC
SAMPLE
APC
SAMPLE
HTXP/LTXP
SAMPLE
HBIAS
SAMPLE
APC
SAMPLE
DS1875
quick-trip alarm that is detected by default remains
active until a subsequent comparator sample shows the
condition no longer exists. A second bias-current monitor (BIAS MAX) compares the DS1875’s BIAS DAC’s
code to a digital value stored in the MAX BIAS register.
This comparison is made at every bias-current update
to ensure that a high bias current is quickly detected.
Monitors and Fault Detection
Monitors
Monitoring functions on the DS1875 include a power-on
analog (POA) VCCcomparison, five quick-trip comparators, and ADC channels. This monitoring combined
with the interrupt masks determine if the DS1875 shuts
down its outputs and triggers the TX-F and FETG outputs. All the monitoring levels and interrupt masks are
user programmable with the exception of POA, which
trips at a fixed range and is nonmaskable for safety
reasons.
Power-On Analog (POA)
POA holds the DS1875 in reset until VCCis at a suitable
level (VCC> V
POA
) for the part to accurately measure
with its ADC and compare analog signals with its quicktrip monitors. Because VCCcannot be measured by the
ADC when VCCis less than V
POA
, POA also asserts the
VCClow alarm, which is cleared by a VCCADC conversion greater than the customer-programmable VCClow
ADC limit. This allows a programmable limit to ensure
that the head room requirements of the transceiver are
satisfied during slow power-up. The TX-F and FETG
outputs do not latch until there is a conversion above
the VCClow limit. The POA alarm is nonmaskable. The
TX-F and FETG outputs are asserted when VCCis
below V
POA
. See the
Low-Voltage Operation
section for
more information.
Five Quick-Trip Monitors and Alarms
Five quick-trip monitors are provided to detect potential
laser safety issues. These monitor:
1) High Bias Current (HBIAS)
2) Low Transmit Power (LTXP)
3) High Transmit Power (HTXP)
4) Max Output Current (BIAS MAX)
5) MON3 Quick Trip (M3QT)
The high- and low-transmit power quick-trip registers
(HTXP and LTXP) set the thresholds used to compare
against the BMD voltage to determine if the transmit
power is within specification. The HBIAS quick trip compares the MON1 input (generally from the MAX3643
bias monitor output) against its threshold setting to
determine if the present bias current is above specifica-
tion. The BIAS MAX quick trip is a digital comparison
that determines if the BIAS DAC indicates that the bias
current is above specification. I
BIAS
is not allowed to
exceed the value set in the MAX BIAS register. When
the DS1875 detects that the bias is at the limit, it sets
the BIAS MAX status bit and clamps the bias current at
the MAX BIAS level. In the closed-loop mode, if the
recalled value from the BIAS LUT is greater than MAX
BIAS then, the update is not done and I
BIAS
reverts to
the previous I
BIAS
value. The quick trips are routed to
the TX-F and FETG outputs through interrupt masks to
allow combinations of these alarms to be used to trigger
these outputs. When FETG is triggered, the DS1875 also
disables the MOD and BIAS outputs. See the
BIAS and
MOD Output During Power-Up
section for details.
MON3 Quick Trip
One additional quick trip is used to protect the APD
from overcurrent. MON3P is used to monitor the current
through the APD. When MON3P exceeds a threshold
set by the M3QT DAC register (Table 02h, Register
C3h), the PWM is shut down by blocking SW pulses.
The MON3 comparison is single-ended referenced to
ground. In the case where MON3 is used differentially
and not referenced to ground, this must be considered
when setting the MON3 quick-trip threshold.
Additionally, the D2 pin can be driven either high or low
as determined by INV M3QT and MUX M3QT bits in
Lower Memory, Register 79h. An external switch controlled by pin D2 may be used to clamp the converter’s
output when MON3 quick trip occurs. This external
switch discharges the output voltage much faster than
allowing the load to discharge the rail. The MON3
quick-trip alarm can be latched by enabling M3QT LEN
in Table 02h, Register 89h. The latch is reset by setting
M3QT RESET in Lower Memory, Register 78h. A soft
quick trip is performed by setting SOFT M3QT in Lower
Memory, Register 78h (see Figure 4).
ADC Monitors and Alarms
The ADC monitors six channels that measure temperature (internal temp sensor), VCC, and MON1–MON4
using an analog multiplexer to measure them round
robin with a single ADC. Each channel has a customerprogrammable full-scale range and offset value that is
factory programmed to default value (see Table 3).
Additionally, MON1–MON4 can right-shift results by up
to 7 bits before the results are compared to alarm
thresholds or read over the I2C bus. This allows customers with specified ADC ranges to calibrate the ADC
full scale to a factor of 1/2ntheir specified range to
measure small signals. The DS1875 can then right-shift
the results by n bits to maintain the bit weight of their
specification.
PON Triplexer and SFP Controller
______________________________________________________________________________________ 19
DS1875
PON Triplexer and SFP Controller
20 ______________________________________________________________________________________
The ADC results (after right-shifting, if used) are compared to high and low alarm and warning thresholds
after each conversion. The alarm values can be used to
trigger the TX-F or FETG outputs. These ADC thresholds
are user programmable through the I2C interface, as
well as masking registers that can be used to prevent
the alarms from triggering the TX-F and FETG outputs.
ADC Timing
There are 10 analog channels that are digitized in a
sequential fashion. The MON5–MON8 channels are
sampled depending on the state of the EN5TO8B bit in
Table 02h, Register 89h. If the bit is programmed to
logic 0, the ADC cycles through temperature, VCC, and
MON1–MON4 (Figure 5). If the bit is programmed to
logic 1, all 10 channels are digitized, including channels MON5–MON8 (Figure 6). In this mode (EN5TO8B
= 0), each of MON5–MON8 is sampled on alternate
cycles, as shown in Figure 5. The total time required to
convert one set of channels is the sequential ADC
cycle time, t
FRAME1
or t
FRAME2
(see Figure 6).
Table 3. ADC Default Monitor Ranges
Figure 6. ADC Timing with EN5TO8B = 1
Figure 5. ADC Timing with EN5TO8B = 0
Figure 4. M3QT Timing
TRIP CONDITION
mCLK
(525kHz)
CAPTURE ALARM
M3QT ALARM
(UNLATCHED)
ONE ADC CYCLE
MON4
TEMP
V
CC
MON1
V
CC
MON2 MON3 MON4
t
FRAME2
MON5 MON6TEMP V
SIGNAL
+FS
SIGNAL
Temperature (°C) 127.996 7FFF -128 8000
VCC (V) 6.5528 FFF8 0 0000
MON1–MON8 (V) 2.4997 FFF8 0 0000
+FS
HEX
-FS
SIGNAL
-FS
HEX
MON1 MON2 MON3 MON4 TEMP
t
FRAME1
MON1
CC
MON2 MON3 MON4
t
FRAME2
MON7 MON8TEMP
DS1875
Right-Shifting ADC Result
If the weighting of the ADC digital reading must conform to a predetermined full-scale value defined by a
standard’s specification, then right-shifting can be used
to adjust the predetermined full-scale analog measurement range while maintaining the weighting of the ADC
results. The DS1875’s range is wide enough to cover all
requirements; when the maximum input value is ≤ 1/2
the FS value, right-shifting can be used to obtain
greater accuracy. For instance, the maximum voltage
might be 1/8th the specified predetermined full-scale
value, so only 1/8th the converter’s range is used. An
alternative is to calibrate the ADC’s full-scale range to
1/8th the readable predetermined full-scale value and
use a right-shift value of 3. With this implementation, the
resolution of the measurement is increased by a factor
of 8, and because the result is digitally divided by 8 by
right-shifting, the bit weight of the measurement still
meets the standard’s specification (i.e., SFF-8472).
The right-shift operation on the ADC result is carried out
based on the contents of RIGHT SHIFT1/0 registers
(Table 02h, Registers 8Eh–8Fh). Four analog channels,
MON1–MON4, have 3 bits each allocated to set the
number of right-shifts. Up to seven right-shift operations
are allowed and are executed as a part of every conversion before the results are compared to the high and
low alarm levels, or loaded into their corresponding
measurement registers (Table 01h, Registers
62h–6Bh). This is true during the setup of internal calibration as well as during subsequent data conversions.
Transmit Fault (TX-F) Output
The TX-F output has masking registers for the ADC
alarms and the QT alarms to select which comparisons
cause it to assert. In addition, the FETG alarm is selectable through the TX-F mask to cause TX-F to assert. All
alarms, with the exception of FETG, only cause TX-F to
remain active while the alarm condition persists.
However, the TX-F latch bit can enable the TX-F output
to remain active until it is cleared by the TX-F reset bit,
TX-D, SOFT TX-D, or by power cycling the part. If the
FETG output is configured to trigger TX-F, it indicates
that the DS1875 is in shutdown and requires TX-D,
SOFT TX-D, or cycling power to reset. Only enabled
alarms activate TX-F (see Figure 7). Table 4 shows
TX-F as a function of TX-D and the alarm sources.
Table 4. TX-F as a Function of TX-D and
Alarm Sources
Figure 7. TX-F Timing
PON Triplexer and SFP Controller
______________________________________________________________________________________ 21
VCC > V
POA
No X X 1
Yes 0 0 0
Yes 0 1 1
Yes 1 X 0
TX-D
NONMASKED
TX-F ALARM
TX-F
TX-F LATCHED OPERATION
DETECTION OF
TX-F FAULT
TX-D OR
TX-F RESET
TX-F
TX-F NONLATCHED OPERATION
DETECTION OF
TX-F FAULT
TX-F
DS1875
PON Triplexer and SFP Controller
22 ______________________________________________________________________________________
Safety Shutdown (FETG) Output
The FETG output has masking registers (separate from
TX-F) for the ADC alarms and the QT alarms to select
which comparisons cause it to assert. Unlike TX-F, the
FETG output is always latched. Its output polarity is
programmable to allow an external nMOS or pMOS to
open during alarms to shut off the laser-diode current.
If the FETG output triggers, indicating that the DS1875
is in shutdown, it requires TX-D, SOFT TX-D, or cycling
power to be reset. Under all conditions, when the analog outputs are reinitialized after being disabled, all the
alarms with the exception of the VCClow ADC alarm
are cleared. The VCClow alarm must remain active to
prevent the output from attempting to operate when
inadequate VCCexists to operate the laser driver. Once
adequate VCCis present to clear the VCClow alarm,
the outputs are enabled following the same sequence
as the power-up sequence.
As previously mentioned, the FETG is an output used to
disable the laser current through a series nMOS or
pMOS. This requires that the FETG output can sink or
source current. Because the DS1875 does not know if it
should sink or source current before VCCexceeds
V
POA
, which triggers the EE recall, this output is high
impedance when VCCis below V
POA
(see the
Low-
Voltage Operation
section for details and diagram). The
application circuit should use a pullup or pulldown
resistor on this pin that pulls FETG to the alarm/shutdown state (high for a pMOS, low for a nMOS). Once
VCCis above V
POA
, the DS1875 pulls the FETG output
to the state determined by the FETG DIR bit (Table 02h,
Register 89h). Set FETG DIR to 0 if an nMOS is used
and 1 if a pMOS is used.
Determining Alarm Causes Using the I2C
Interface
To determine the cause of the TX-F or FETG alarm, the
system processor can read the DS1875’s alarm trap bytes
(ATB) through the I2C interface (Table 01h, Registers
F8h–FBh). The ATB has a bit for each alarm. Any time an
alarm occurs, regardless of the mask bit’s state, the
DS1875 sets the corresponding bit in the ATB. Active ATB
bits remain set until written to 0s through the I2C interface.
On power-up, the ATB is 0s until alarms dictate otherwise.
FETG causes additional alarms that make it difficult to
determine the root cause of the problem. Therefore, no
updates are made to the ATB when FETG occurs.
Figure 8. FETG/Output Disable Timing (Fault Condition Detected)
Table 5. FETG, MOD, and BIAS Outputs
as a Function of TX-D and Alarm Sources
DETECTION OF
FETG FAULT
TX-D
I
BIAS
V
MOD
FETG*
*FETG DIR = 0
t
OFF
t
OFF
t
FETG:ON
t
ON
t
ON
t
FETG:OFF
VCC >
V
POA
Yes 0 0
Yes 0 1
Yes 1 X
TX-D
NONMASKED
FETG ALARM
FETG
FETG
DIR
FETG
DIR
FETG
DIR
MOD AND
BIAS
OUTPUTS
Enabled
Disabled
Disabled
DS1875
Die Identification
The DS1875 has an ID hard-coded to its die. Two registers (Table 02h, Registers 86h–87h) are assigned for
this feature. Byte 86h reads 75h to identify the part as
the DS1875; byte 87h reads the die revision.
Low-Voltage Operation
The DS1875 contains two power-on reset (POR) levels.
The lower level is a digital POR (V
POD
) and the higher
level is an analog POR (V
POA
). At startup, before the
supply voltage rises above V
POA
, the outputs are disabled (FETG and BIAS outputs are high impedance,
MOD is low), all SRAM locations are low (including
shadowed EEPROM (SEE)), and all analog circuitry is
disabled. When VCCreaches V
POA
, the SEE is
recalled, and the analog circuitry is enabled. While V
CC
remains above V
POA
, the device is in its normal operating state, and it responds based on its nonvolatile configuration. If during operation VCCfalls below V
POA
but
is still above V
POD
, the SRAM retains the SEE settings
from the first SEE recall, but the device analog is shut
down and the outputs are disabled. FETG is driven to
its alarm state defined by the FETG DIR bit (Table 02h,
Register 89h). If the supply voltage recovers back
above V
POA
, the device immediately resumes normal
functioning. When the supply voltage falls below V
POD
,
the device SRAM is placed in its default state and
another SEE recall is required to reload the nonvolatile
settings. The EEPROM recall occurs the next time V
CC
exceeds V
POA
. Figure 9 shows the sequence of events
as the voltage varies.
Any time V
CC
is above V
POD
, the I2C interface can be
used to determine if VCCis below the V
POA
level. This
is accomplished by checking the RDYB bit in the status
(Lower Memory, Register 6Eh) byte. RDYB is set when
VCCis below V
POA
. When VCCrises above V
POA
,
RDYB is timed (within 500µs) to go to 0, at which point
the part is fully functional.
For all device addresses sourced from EEPROM (Table
02h, Register 8Ch), the default device address is A2h
until VCCexceeds V
POA
, allowing the device address
to be recalled from the EEPROM.
Enhanced RSSI Monitoring (Dual Range
Functionality)
The DS1875 offers a new feature to improve the accuracy and range of MON3, which is most commonly
used for monitoring RSSI. This feature enables rightshifting (along with its gain and offset settings) when
the input signal is below a set threshold (within the
range that benefits using right-shifting) and then automatically disables right-shifting (recalling different gain
and offset settings) when the input signal exceeds the
threshold. Also, to prevent “chattering,” hysteresis prevents excessive switching between modes in addition
to ensuring that continuity is maintained. Dual range
operation is enabled by default (factory programmed in
EEPROM). However, it can easily be disabled through
the RSSI_FF and RSSI_FC bits. When dual range operation is disabled, MON3 operates identically to the
other MON channels, although featuring a differential
input.
Figure 9. SEE Timing
PON Triplexer and SFP Controller
______________________________________________________________________________________ 23
SEE RECALL SEE RECALL
V
POA
V
CC
V
POD
HIGH
FETG
IMPEDANCE
PRECHARGED
SEE
TO 0
HIGH
IMPEDANCE
PRECHARGED
TO 0
RECALLED
VALUE
DRIVEN TO
FETG DIR
NORMAL
OPERATION
NORMAL
OPERATION
DRIVEN TO
FETG DIR
OPERATION
RECALLED
VALUE
NORMAL
DRIVEN TO
FETG DIR
HIGH
IMPEDANCE
PRECHARGED
TO 0
DS1875
24 ______________________________________________________________________________________
Dual-range functionality consists of two modes of operation: fine mode and coarse mode. Each mode is calibrated for a unique transfer function, hence the term, dual
range. Table 6 highlights the registers related to MON3.
Fine mode is equivalent to the other MON channels. Fine
mode is calibrated using the gain, offset, and right-shifting registers at locations shown in Table 6 and is ideal
for relatively small analog input voltages. Coarse mode is
automatically switched to when the input exceeds the
threshold (to be discussed in a subsequent paragraph).
Coarse mode is calibrated using different gain and offset
registers, but lacks right-shifting (since coarse mode is
only used on large input signals). The gain and offset
registers for coarse mode are also shown in Table 6.
With the use of right-shifting, the fine mode full scale is
programmed to (1/2N)th the coarse mode full scale. The
DS1875 will now autorange to choose the range that
gives the best resolution for the measurement. To eliminate chatter, 6.25% of hysteresis is applied when the
input resides at the boundary of the two ranges. See
Figure 10. Additional information for each of the registers
can be found in the
Memory Map
section.
Dual range operation is transparent to the end user. The
results of MON3 analog-to-digital conversions are still
stored/reported in the same memory locations (68–69h,
Lower Memory) regardless of whether the conversion
was performed in fine mode or coarse mode.
When the DS1875 is powered up, analog-to-digital conversions begin in a round-robin fashion. Every MON3
timeslice begins with a fine mode analog-to-digital conversion (using fine mode’s gain, offset, and right-shifting settings). See the flowchart in Figure 10. Then,
depending on whether the last MON3 timeslice resulted
in a coarse-mode conversion and also depending on
the value of the current fine conversion, decisions are
made whether to use the current fine-mode conversion
result or to make an additional conversion (within the
same MON3 timeslice), using coarse mode (using
coarse mode’s gain and offset settings, and no rightshifting) and reporting the coarse-mode result. The
flowchart also illustrates how hysteresis is implemented. The fine-mode conversion is compared to one of
Figure 10. RSSI Flowchart
Table 6. MON3 Configuration Registers
PON Triplexer and SFP Controller
MON3
TIMESLICE
PERFORM FINE-
MODE CONVERSION
DID PRIOR MON3
TIMESLICE RESULT IN A
COARSE CONVERSION?
(LAST RSSI = 1?)
DID CURRENT FINEMODE CONVERSION
REACH MAX?
LAST RSSI = 0
REPORT FINE
CONVERSION RESULT
END OF MON3
TIMESLICE
Y
N
Y
N
N
WAS CURRENT FINE-
MODE CONVERSION
≥ 93.75% OF FS?
Y
PERFORM COARSE-
MODE CONVERSION
LAST RSSI = 1
REPORT COARSE
CONVERSION RESULT
REGISTER FINE MODE COARSE MODE
MON3 FINE SCALE 98h–99h, Table 02h 9Ch –9Dh, Table 02h
MON3 FINE OFFSET A8h–A9h, Table 02h ACh–ADh, Table 02h
RIGHT SHIFT0/1 8Eh–8Fh, Table 02h —
CONFIG (RSSI_FC, RSSI_FF bits) 89h, Table 02h
MON3 VALUE 68h–69h, Lower Memory
DS1875
two thresholds. The actual threshold values are a function of the number of right-shifts being used. Table 7
shows the threshold values for each possible number
of right-shifts.
The RSSI_FF and RSSI_FC (Table 02h, Register 89h)
bits are used to force fine-mode or coarse-mode conversions, or to disable the dual-range functionality.
Dual-range functionality is enabled by default (both
RSSI_FC and RSSI_FF are factory programmed to 0 in
EEPROM). It can be disabled by setting RSSI_FC to 0
and RSSI_FF to 1. These bits are also useful when calibrating MON3. For additional information, see the
Memory Map
section.
PWM Controller
The DS1875 has a PWM controller that, when used with
external components, generates a low-noise, high-voltage output to bias APDs in optical receivers. The
achievable boost voltage is determined by the external
component selection. Figure 12 shows a typical
schematic. Selection of switching frequency, external
inductor, capacitors, resistor network, switching FET,
and switch diode determine the performance of the
DC-DC converter. The PWM controller can be configured in boost or buck mode. Both modes require an
external nMOS or npn transistor.
The DS1875 PWM controller consists of several sections used to create a PWM signal to drive a DC-DC
converter. Figure 11 is a block diagram of the DS1875
PWM controller. Following is a description of each
block in the PWM controller and some guidelines for
selecting components for the DC-DC converter.
The PWM DAC is used to set the desired output voltage
of the DC-DC converter section. The feedback from the
DC-DC converter is compared to the output from the
PWM DAC by an error amplifier. If the FB level is less
Table 7. MON3 Hysteresis Threshold Values
*
This is the minimum reported coarse-mode conversion.
Figure 11. PWM Controller Diagram
PON Triplexer and SFP Controller
______________________________________________________________________________________ 25
NO. OF RIGHT-
SHIFTS
0 FFF8h F000h
1 7FFCh 7800h
2 3FFEh 3C00h
3 1FFFh 1E00h
4 0FFFh 0F00h
5 07FFh 0780h
6 03FFh 03C0h
7 01FFh 01E0h
FINE MODE
(MAX)
COARSE MODE
(MIN*)
PWM EN
PWM DAC TEMPERATURE-
REFERENCED LUT
TABLE 07h
2
MANUAL I
C CONTROL
DS1875
PWM CONTROLLER
MUX
PWM DAC
TABLE 02h
REGISTER FEh
PWM_FR[1:0]
PWM DAC
8-BIT
0 TO 1.25V
RAMP
90% DUTY
CYCLE OSC
10μA
AMPLIFIER
10μA
ERROR
VOLTAGE CLAMP
HIGH = 2.1V
LOW = 0.8V
1.9V
1.0V
M3QT
GATE DRIVER
90% MAX
DUTY CYCLE
COMP
SW
FB
DS1875
PON Triplexer and SFP Controller
26 ______________________________________________________________________________________
than the PWM DAC level, the error amplifier increases
the level on the COMP pin. The level on the COMP pin
is compared to the signal from the oscillator and ramp
generator to set the duty cycle that is input to the gate
driver and maximum duty-cycle limiting block. An
increase on the COMP pin increases the duty cycle.
Conversely, if FB is greater than the PWM DAC, the
level on COMP is decreased, decreasing the duty
cycle. The gate driver and maximum duty-cycle block
is used to limit the maximum duty cycle of the PWM
controller to 90%. This block also disables the PWM driver if an M3QT has resulted from the APD current
exceeding a desired limit.
The output from the PWM DAC is used to control the
output voltage of the DC-DC converter. The values for
the PWM DAC are recalled from the Table 07h, which is
a temperature-indexed LUT. The temperature-indexed
value from the LUT is written to the PWM DAC register
(Table 02h, Register FEh), which updates the setting of
the PWM DAC. The PWM DAC can also be operated in
a manual mode by disabling the automatic updating
from the LUT. This is done by clearing the PWM EN bit
(Table 02h, Register 80h, Bit 5). The PWM DAC fullscale output is 1.25V with 8 bits of resolution. When
designing the feedback for the DC-DC converter section, the user needs to make sure that the desired level
applied to the FB pin is in this range.
The COMP pin is driven by the error amplifier comparing the PWM DAC to the DC-DC converter feedback
signal at the FB pin. The error amplifier can sink and
source 10µA. An external resistor and capacitor connected to the COMP pin determine the rate of change
the COMP pin. The resistor provides an initial step
when the current from the error amplifier changes. The
capacitor determines how quickly the COMP pin
charges to the desired level. The COMP pin has internal voltage clamps that limit the voltage level to a minimum of 0.8V and a maximum of 2.1V.
The oscillator and ramp generator create a ramped signal. The frequency of this signal can be 131.25kHz,
262.5kHz, 525kHz, or 1050kHz and is set by the
PWM_FR[1:0] bits (Table 02h, Register 88h, Bits 5:4).
The low level and high level for the ramped signal are
approximately 1.0V and 1.9V, respectively.
The ramped signal is compared to the voltage level on
the COMP pin to determine the duty cycle that is input
to the gate driver and duty-cycle limiting block. When
COMP is clamped low at 0.8V, below the level of the
ramped signal, the comparator outputs a 0% dutycycle signal to the gate driver block. When COMP is
clamped at 2.1V, above the level of the ramped signal,
the comparator outputs a 100% duty-cycle signal to the
gate driver and duty-cycle limiting block. The dutycycle liming block is used to limit the duty cycle of the
PWM signal from the SW pin to 90%.
The PWM controller is designed to protect expensive
APDs against adverse operating conditions while providing optimal bias. The PWM controller monitors photodiode current to protect APDs under avalanche
conditions using the MON3 quick trip. A voltage level
that is proportional to the APD current can be input to
the MON3 pin. When this voltage exceeds the level set
by the M3QT DAC (Table 02h, Register C3h), pulses
from the PWM controller are blocked until the fault is
cleared. The quick trip can also toggle the digital output
D2. D2 can be connected to an external FET to quickly
discharge the DC-DC converter filter capacitors.
Inductor Selection
Optimum inductor selection depends on input voltage,
output voltage, maximum output current, switching frequency, and inductor size. Inductors are typically specified by their inductance (L), peak current (IPK), and
resistance (LR).
The inductance value is given by:
Where:
VIN= DC-DC converter input voltage
V
OUT
= Output of DC-DC converter
I
OUT(MAX)
= Maximum output current delivered
T = Time period of switching frequency (seconds)
D = Duty cycle
η = Estimated power conversion efficiency
The equation for inductance factors in conversion efficiency. For inductor calculation purposes, an η of 0.5
to 0.75 is usually suitable.
For example, to obtain an output of 80V with a load current of 1.0mA from an input voltage of 5.0V using the
maximum 90% duty cycle and frequency of 1050kHz
(T = 952ns), and assuming an efficiency of 0.5, the previous equation yields an L of 120µH, so a 100µH inductor would be a suitable value.
The peak inductor current is given by:
L
22
VDT
×××
IN
=
2
IV
OUT MAX OUT
()
VDT
××
PK
IN
=
L
I
η
×
DS1875
Stability and Compensation Component Selection
The components connected to the COMP pin (R
COMP
and C
COMP
) introduce a pole and zero that are necessary for stable operation of the PWM controller
(Figure 12).
The dominant pole, POLE1, is formed by the output
impedance of the error amplifier (REA) and C
COMP
. The
zero formed by the components on COMP, ZERO1, is
selected to cancel POLE2 formed by the output filter
cap C3 and output load R
LOAD
. The additional pole,
POLE3, formed by R1 and C3 should be at least a
decade past the crossover frequency to not affect stability. The following formulas can be used to calculate
the poles and zero for the application shown in
Figure 12.
POLE1 (dominant pole) = 1/(2π × REA× C
COMP
)
ZERO1 (compensation zero) = 1/(2π × R
COMP
× C
COMP
)
POLE2 (output load pole) =
POLE3 (output filter pole) = 1/(2π × R1 × C3)
The DC open-loop gain is given by:
Where:
REA= 260MΩ
GM= 425µS
R
LOAD
= Parallel combination of feedback network and
load resistance
V
OUT
= Output of DC-DC converter
VIN= DC-DC converter input voltage
VFB= Feedback voltage at the FB pin
T = Time period of switching frequency (seconds)
L = Inductor value (henries)
DAC1 Output
The DAC1 output has a full-scale 2.5V range with 8 bits
of resolution, and is programmed through the I2C interface. The DAC1 setting is nonvolatile and password-2
(PW2) protected.
M4DAC Output
The M4DAC output has a full-scale 2.5V range with 8
bits of resolution, and is controlled by an LUT indexed
by the MON4 voltage. The M4DAC LUT (Table 06h) is
nonvolatile and PW2 protected. See the
Memory
Organization
section for details. The recalled value is
either 16-bit or 32-bit depending on bits DBL_SB and
UP_LOWB in Table 02h, Register C7h.
Digital I/O Pins
Five digital I/O pins are provided for additional monitoring and control. By default the LOSI pin is used to convert a standard comparator output for loss of signal
(LOSI) to an open-collector output. This means the mux
shown on the block diagram by default selects the LOSI
pin as the source for the D0 output transistor. The level
of the D0 pin can be read in the STATUS byte (Lower
Memory, Register 6Eh) as the LOS STATUS bit. The
LOS STATUS bit reports back the logic level of the D0
pin, so an external pullup resistor must be provided for
this pin to output a high level. The LOSI signal can be
inverted before driving the open-drain output transistor
using the XOR gate provided. The MUX LOS allows the
D0 pin to be used identically to the D1, D2, and D3
pins. However, the mux setting (stored in the EEPROM)
does not take effect until VCC> V
POA
, allowing the EEPROM to recall. This requires the LOSI pin to be grounded for D0 to act identical to the D1, D2, and D3 pins.
Digital pins D1, D2, and D3 can be used as inputs or
outputs. External pullup resistors must be provided to
realize high-logic levels. The DIN byte indicates the
logic levels of these input pins (Lower Memory, Register
79h), and the open-drain outputs can be controlled
using the DOUT byte (Lower Memory, Register 78h).
When VCC< V
POA
, these outputs are high impedance.
Once VCC≥ V
POA
, the outputs go to the power-on
default state stored in the DPU byte (Table 02h, Register
C0h). The EEPROM-determined default state of the pin
can be modified with PW2 access. After the default
state has been recalled, the SRAM registers controlling
outputs can be modified without password access. This
allows the outputs to be used to control serial interfaces
without wearing out the default EEPROM setting.
D2 can be configured as the output of a quick-trip monitor for MON3. The main application is to quickly shut
down the PWM converter and discharge the voltage
created by the converter. This is shown in the typical
application circuit.
PON Triplexer and SFP Controller
______________________________________________________________________________________ 27
2
×−
VV
OUT IN
−
VV R CC
OUT IN LOAD
×
223
××+
π
1
()
AOL G R
=× × ×
MEA
VV
FB IN
08522.
×
VV
×−
OUT IN
×
⎜
⎝
−
VV
OUT IN
VV
OUT
×
×
RT
LOAD
×
2
L
⎛
⎞
⎟
⎠
DS1875
PON Triplexer and SFP Controller
28 ______________________________________________________________________________________
Figure 14. PWM Controller Current-Sink Output Configuration
Figure 13. PWM Controller Voltage Output Configuration
Figure 12. PWM Controller Typical APD Bias Circuit
V
SW
IN
L1
C1
D1
Q1
R1
C2
FB
C
COMP
R
COMP
COMP
V
OUT
C3
R2
R3
R4
MAX4007
3.3V
RMON
DS1875
APD OVERLOAD QUICK TRIP
D2
MON3
VOLTAGE OUTPUT
DS1875
SW
FB
COMP
DS1875
SW
COMP
FB
APD
C4
ROSA
TIA
CURRENT SINK
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