Rainbow Electronics DS1874 User Manual

General Description

The DS1874 controls and monitors all functions for SFF,
SFP, and SFP+ modules including all SFF-8472 func­tionality. The combination of the DS1874 with the
MAX3798/MAX3799 laser driver/limiting amplifier pro­vides APC loop, modulation current control, and eye
safety functionality. The DS1874 continuously monitors
for high output current, high bias current, and low and
high transmit power to ensure that laser shutdown for
eye safety requirements are met without adding external
components. Six ADC channels monitor VCC, tempera­ture, and four external monitor inputs (MON1–MON4)
that can be used to meet all monitoring requirements.
MON3 is differential with support for common mode to
VCC. Two digital-to-analog (DAC) outputs with tempera­ture-indexed lookup tables (LUTs) are available for addi­tional monitoring and control functionality.

Applications

SFF, SFP, and SFP+ Transceiver Modules

Features

♦ Meets All SFF-8472 Control and Monitoring

Requirements

♦ Laser Bias Controlled by APC Loop and

Temperature LUT to Compensate for Tracking
Error

♦ Laser Modulation Controlled by Temperature LUT

♦ Six Analog Monitor Channels: Temperature, V

CC

,

MON1–MON4

MON1–MON4 Support Internal and External

Calibration
Scalable Dynamic Range
Internal Direct-to-Digital Temperature Sensor
Alarm and Warning Flags for All Monitored

Channels

♦ Two 9-Bit Delta-Sigma Outputs with 36 Entry

Temperature LUTs

♦ Digital I/O Pins: Five Inputs, Five Outputs

♦ Comprehensive Fault-Measurement System with

Maskable Laser Shutdown Capability

♦ Flexible, Two-Level Password Scheme Provides

Three Levels of Security

♦ 256 Additional Bytes Located at A0h Slave

Address

♦ I2C-Compatible Interface

♦ 3-Wire Master to Communicate with the MAX3798/

MAX3799 Laser Driver/Limiting Amplifier

♦ +2.85V to +3.9V Operating Voltage Range

♦ -40°C to +95°C Operating Temperature Range

♦ 28-Pin TQFN (5mm x 5mm) Package

DS1874

________________________________________________________________

Maxim Integrated Products

1

Pin Configuration

Ordering Information

19-4691; Rev 0; 6/09

For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.

+

Denotes a lead(Pb)-free/RoHS-compliant package.

T&R = Tape and reel.

*

EP = Exposed pad.

SFP+ Controller with Digital LDD Interface

TOP VIEW

N.C.

V

CC

CSELOUT

SCLOUT

SDAOUT

LOSOUT

OUT1

*EXPOSED PAD.

DAC2

GND

DAC1

2021 19 17 16 15

22

23

24

25

26

27

+

28

12

RSELOUT

(5mm × 5mm × 0.8mm)

DS1874

3

SCL

SDA

THIN QFN

REFIN

GND

18

4567

TXF

LOS

*EP

MON2

IN1

CC

V

TXD

14

MON1

MON3N

13

12

MON3P

MON4

11

10

TXDOUT

RSEL

9

8

GND

PART TEMP RANGE PIN-PACKAGE

DS1874T+ -40°C to +95°C 28 TQFN-EP*

DS1874T+T&R -40°C to +95°C 28 TQFN-EP*

DS1874

2 _______________________________________________________________________________________

Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

DAC1, DAC2 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6

Analog Quick-Trip Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6

Analog Voltage Monitoring Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6

Digital Thermometer Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

Timing Characteristics (Control Loop and Quick Trip) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

3-Wire Digital Interface Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

I

2

C AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

Nonvolatile Memory Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

Typical Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

Typical Operating Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

MAX3798/MAX3799 DAC Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

BIAS Register/APC Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

MODULATION Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

BIAS and MODULATION Control During Power-Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

BIAS and MODULATION Registers as a Function of Transmit Disable (TXD) . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

APC and Quick-Trip Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

Monitors and Fault Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

Monitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

Five Quick-Trip Monitors and Alarms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

Six ADC Monitors and Alarms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

ADC Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

Right-Shifting ADC Result . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

Enhanced RSSI Monitoring (Dual-Range Functionality) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

Low-Voltage Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

Power-On Analog (POA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

Delta-Sigma Outputs (DAC1 and DAC2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

Digital I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

LOS, LOSOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

IN1, RSEL, OUT1, RSELOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

TXF, TXD, TXDOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

TABLE OF CONTENTS

SFP+ Controller with Digital LDD Interface

DS1874

_______________________________________________________________________________________ 3

Transmit Fault (TXF) Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

Die Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

3-Wire Master for Controlling the MAX3798/MAX3799 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

3-Wire Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

DS1874 and MAX3798/MAX3799 Communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

Normal Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

Manual Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

MAX3798/MAX3799 Register Map and DS1874 Corresponding Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

I

2

C Communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

I2C Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

I

2

C Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

Shadowed EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

Lower Memory Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

Table 01h Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

Table 02h Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

Table 04h Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

Table 05h Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

Table 06h Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

Table 07h Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

Table 08h Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

Auxiliary A0h Memory Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

Lower Memory Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

Table 01h Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48

Table 02h Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55

Table 04h Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84

Table 06h Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85

Table 07h Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86

Table 08h Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87

Auxiliary Memory A0h Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87

Applications Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88

Power-Supply Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88

SDA and SCL Pullup Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88

Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88

TABLE OF CONTENTS (continued)

SFP+ Controller with Digital LDD Interface

DS1874

SFP+ Controller with Digital LDD Interface

4 _______________________________________________________________________________________

Figure 1. Modulation LUT Loading to MAX3798/MAX3799 MOD DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

Figure 2. Power-Up Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

Figure 3. TXD Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

Figure 4. APC Loop and Quick-Trip Sample Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

Figure 5. ADC Round-Robin Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

Figure 6. MON3 Differential Input for High-Side RSSI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

Figure 7. RSSI Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

Figure 8. Low-Voltage Hysteresis Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

Figure 9. Recommended RC Filter for DAC1/DAC2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

Figure 10. Delta-Sigma Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

Figure 11. DAC1/DAC2 LUT Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

Figure 12. Logic Diagram 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

Figure 13. Logic Diagram 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

Figure 14a. TXF Nonlatched Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

Figure 14b. TXF Latched Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

Figure 15. 3-Wire Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

Figure 16. 3-Wire State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

Figure 17. I

2

C Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

Figure 18. Example I2C Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

Figure 19. Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

Table 1. Acronyms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

Table 2. Update Rate Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

Table 3. ADC Default Monitor Full-Scale Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

Table 4. MON3 Hysteresis Threshold Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

Table 5. MON3 Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

LIST OF FIGURES

LIST OF TABLES

DS1874

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.

Voltage Range on MON1–MON4, RSEL,

IN1, LOS, TXF, and TXD Pins

Relative to Ground .................................-0.5V to (V

CC

+ 0.5V)*

Voltage Range on V

CC

, SDA, SCL, OUT1,
RSELOUT, and LOSOUT Pins

Relative to Ground.................................................-0.5V to +6V

Operating Temperature Range ...........................-40°C to +95°C

Programming Temperature Range .........................0°C to +95°C

Storage Temperature Range .............................-55°C to +125°C

Soldering Temperature...........................Refer to the IPC/JEDEC

J-STD-020 Specification.

DC ELECTRICAL CHARACTERISTICS

(VCC= +2.85V to +3.9V, TA= -40°C to +95°C, unless otherwise noted.)

*

Subject to not exceeding +6V.

RECOMMENDED OPERATING CONDITIONS

(TA= -40°C to +95°C, unless otherwise noted.)

ABSOLUTE MAXIMUM RATINGS

SFP+ Controller with Digital LDD Interface

_______________________________________________________________________________________ 5

Main Supply Voltage VCC (Note 1) +2.85 +3.9 V

High-Level Input Voltage
(SDA, SCL, SDAOUT)

Low-Level Input Voltage
(SDA, SCL, SDAOUT)

High-Level Input Voltage
(TXD, TXF, RSEL, IN1, LOS)

Low-Level Input Voltage
(TXD, TXF, RSEL, IN1, LOS)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

V

IH:1

V

-0.3

IL:1

V

2.0

IH:2

V

-0.3 +0.8 V

IL:2

0.7 x
V

CC

VCC+

0.3

0.3 x
V

CC

V

CC

0.3

V

V

+

V

Supply Current ICC (Notes 1, 2) 2.5 10 mA

Output Leakage
(SDA, SDAOUT, OUT1,
RSELOUT, LOSOUT, TXF)

Low-Leve l Output Voltage (SDA,
SDAOUT, SCLOUT, CSELOUT,
OUT1, RSELOUT, LOSOUT,
TXDOUT, DAC1, DAC2, TXF)

High-Level Output Voltage
(DAC1, DAC2, SCLOUT,
SDAOUT, CSELOUT, TXDOUT)

TXDOUT Before EEPROM Reca ll 10 100 nA

DAC1 and DAC2 Before LUT
Recall

Input Leakage Current
(SCL, TXD, LOS, RSEL, IN1)

Digital Power-On Reset POD 1.0 2.2 V

Analog Power-On Reset POA 2.0 2.75 V

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

I

1 μA

LO

IOL = 4mA 0.4

V

OL

IOL = 6mA 0.6

-

V

V

IOH = 4mA

OH

Figure 11 10 100 nA

I

1 μA

LI

CC

0.4

V

V

DS1874

SFP+ Controller with Digital LDD Interface

6 _______________________________________________________________________________________

ANALOG VOLTAGE MONITORING CHARACTERISTICS

(VCC= +2.85V to +3.9V, TA= -40°C to +95°C, unless otherwise noted.)

ANALOG QUICK-TRIP CHARACTERISTICS

(VCC= +2.85V to +3.9V, TA= -40°C to +95°C, unless otherwise noted.)

DAC1, DAC2 ELECTRICAL CHARACTERISTICS

(VCC= +2.85V to +3.9V, TA= -40°C to +95°C, unless otherwise noted.)

Main Oscillator Frequency f

Delta-Sigma Input-Clock
Frequency

Reference Voltage Input (REFIN) V

Output Range 0 V

Output Resolution

Output Impedance RDS 35 100 

MON2, TXP HI, TXP LO Full­Scale Voltage

HBIAS, LOS Full-Scale Voltage 1.25 V

MON2 Input Resistance 35 50 65 k

Resolution 8 Bits

Error TA = +25°C ±2 %FS

Integral Nonlinearity -1 +1 LSB

Differentia l Nonl inearit y -1 +1 LSB

Temperature Drift -2.5 +2.5 %FS

LOS Offset -5 mV

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

5 MHz

OSC

f

f

DS

Minimum 0.1μF to GND 2 VCC V

REFIN

See the Delta-Sigma Outputs (DAC1 and
DAC2) section for details.

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

V

2.5 V

APC

9 Bits

/2 MHz

OSC

REFIN

V

ADC Resolution 13 Bit s

Input/Supply Accuracy
(MON1–MON4, V

Update Rate for Temperature,
MON1–MON4, and V

Input/Supply Offset
(MON1–MON4, V

Factor y Setting

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

)

CC

CC

)

CC

MON1–MON4 2.5

V

CC

MON3 Fine

ACC At factor y setting 0.25 0.50 %FS

tRR 64 75 m s

V

(Note 3) 0 5 LSB

OS

(Note 4)

6.5536

312.5 μV

V

DS1874

3-WIRE DIGITAL INTERFACE SPECIFICATION

(VCC= +2.85V to +3.9V, TA= -40°C to +95°C, timing referenced to V

IL(MAX)

and V

IH(MIN)

, unless otherwise noted. See Figure 15.)

SFP+ Controller with Digital LDD Interface

_______________________________________________________________________________________ 7

TIMING CHARACTERISTICS (CONTROL LOOP AND QUICK TRIP)

(VCC= +2.85V to +3.9V, TA= -40°C to +95°C, unless otherwise noted.)

AC ELECTRICAL CHARACTERISTICS

(VCC= +2.85V to +3.9V, TA= -40°C to +95°C, unless otherwise noted.)

DIGITAL THERMOMETER CHARACTERISTICS

(VCC= +2.85V to +3.9V, TA= -40°C to +95°C, unless otherwise noted.)

Thermometer Error T

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

-40°C to +95°C -3 +3 °C

ERR

TXD Enable t

Recovery from TXD Disable
(Figure 14)

Recovery After Power-Up t

Fault Reset Time (to TXF = 0)

Fault A ss ert Time (to TXF = 1) t

LOSOUT Assert Time t

LOSOUT Deassert Time t

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

From  TXD (Notes 5, 6) 5 μs

OFF

t

From  TXD (Notes 5, 7) 1 m s

ON

INIT_DAC

LOSS_ON

LOSS_OFF

From  V

t

From  TXD 131

INITR1

From  V

t

INITR2

FAULT

After HTXP, LTXP, HBATH, IBIASMAX
(Note 9)

LLOS (Notes 9, 10) 6.4 55 μs

HLOS (Notes 9, 11) 6.4 55 μs

> VCC LO alarm (Notes 5, 8) 20 ms

CC

> VCC LO alarm (Note 8) 161

CC

Output-Enable Time Following POA t

Binary Search Time t

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

(Note 8) 20 ms

INIT

(Note 12) 8 10

SEARCH

ms

6.4 55 μs

BIAS

Samples

SCLOUT Clock Frequency f

SCLOUT Duty Cycle t

SDAOUT Setup Time tDS 100 ns

SDAOUT Hold Time tDH 100 ns

CSELOUT Pulse-Width Low t

CSELOUT Leading Time Before
the First SCLOUT Edge

CSELOUT Trailing Time After the
Last SCLOUT Edge

SDAOUT, SCLOUT Load C

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

(Note 13) 833 kHz

SCLOUT

50 %

3WDC

500 ns

CSW

t

500 ns

L

t

(Note 14) 500 ns

T

Total bus capacitance on one line (Note 14) 10 pF

B3W

Note 1: All voltages are referenced to ground. Current into the IC is positive, and current out of the IC is negative.
Note 2: Inputs are at supply rail. Outputs are not loaded.
Note 3: This parameter is guaranteed by design.
Note 4: Full-scale is user programmable.
Note 5: The DACs are the bias and modulation DACs found in the MAX3798/MAX3799 that are controlled by the DS1874.
Note 6: The DS1874 is configured with TXDOUT connected to the MAX3798/MAX3799 DISABLE input.
Note 7: This includes writing to the modulation DAC and the initial step written to the bias DAC.
Note 8: A temperature conversion is completed and the modulation register value is recalled from the LUT and V

CC

has been

measured to be above V

CC

LO alarm.

Note 9: The timing is determined by the choice of the update rate setting (see Table 02h, Register 88h).
Note 10: This specification is the time it takes from MON3 voltage falling below the LLOS trip threshold to LOSOUT asserted high.
Note 11: This specification is the time it takes from MON3 voltage rising above the HLOS trip threshold to LOSOUT asserted low.
Note 12: Assuming an appropriate initial step is programmed that would cause the power to exceed the APC set point within four

steps, the bias current will be within 3% within the time specified by the binary search time. See the

BIAS and MODULA-

TION Control During Power-Up

section.

Note 13: I

2

C interface timing shown is for fast mode (400kHz). This device is also backward compatible with I2C standard mode

timing.

Note 14: C

B

—the total capacitance of one bus line in pF.

Note 15: EEPROM write begins after a STOP condition occurs.

DS1874

SFP+ Controller with Digital LDD Interface

8 _______________________________________________________________________________________

NONVOLATILE MEMORY CHARACTERISTICS

(VCC= +2.85V to +3.9V, unless otherwise noted.)

I2C AC ELECTRICAL CHARACTERISTICS

(VCC= +2.85V to +3.9V, TA= -40°C to +95°C, timing referenced to V

IL(MAX)

and V

IH(MIN)

, unless otherwise noted. See Figure 17.)

SCL Clock Frequency f
Cloc k Pulse-Width Low t
Cloc k Pulse-Width High t
Bus-Free Time Between STOP and START

Condition
START Hold Time t
START Setup Time t
Data Out Hold T ime t
Data In Setup Time t
Rise Time of Both SDA and SCL Signals tR (Note 14) 20 + 0.1CB 300 ns

Fal l Time of Both SDA and SCL Signals tF (Note 14) 20 + 0.1CB 300 ns
STOP Setup Time t
EEPROM Write Time tW (Note 15) 20 ms
Capacitive Load for Each Bus Line CB 400 pF

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

(Note 13) 0 400 kHz

SCL

1.3 μs

LOW

0.6 μs

HIGH

t

1.3 μs

BUF

0.6 μs

HD: STA

0.6 μs

SU:STA

0 0.9 μs

HD:DAT

100 ns

SU:DAT

0.6 μs

SU:STO

EEPROM Write Cycles

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

At +25°C 200,000

At +85°C 50,000

DS1874

SFP+ Controller with Digital LDD Interface

_______________________________________________________________________________________

9

Typical Operating Characteristics

(VCC= +2.85V to +3.9V, TA= +25°C, unless otherwise noted.)

SUPPLY CURRENT vs. SUPPLY VOLTAGE

SDA = SCL = V

2.9

2.7

2.5

2.3

2.1

SUPPLY CURRENT (mA)

1.9

1.7

1.5

2.85

CC

+25°C

+95°C

-40°C

VCC (V)

DS1874 toc01

3.853.603.10 3.35

SUPPLY CURRENT vs. TEMPERATURE

2.7
SDA = SCL = V

2.6

2.5

2.4

2.3

SUPPLY CURRENT (mA)

2.2

2.1

2.0

-40

MON1–MON4 DNL

1.0
USING FACTORY-PROGRAMMED

0.8
FULL-SCALE VALUE OF 2.5V

0.6

0.4

0.2

0

-0.2

-0.4

MON1–MON4 DNL (LSB)

-0.6

-0.8

-1.0
0 2.5

MON1–MON4 INPUT VOLTAGE (V)

2.01.51.00.5

1.0

0.8

DS1874 toc04

0.6

0.4

0.2

0

-0.2

-0.4

DAC1 AND DAC2 DNL (LSB)

-0.6

-0.8

-1.0
0

DAC1 AND DAC2 POSITION (DEC)

CC

VCC = 3.9V

VCC = 2.85V

VCC = 3.3V

TEMPERATURE (°C)

DAC1 AND DAC2 DNL

MON1–MON4 INL

1.0
USING FACTORY-PROGRAMMED

0.8

DS1874 toc02

806040200-20

DS1874 toc05

500400300200100

FULL-SCALE VALUE OF 2.5V

0.6

0.4

0.2

0

-0.2

-0.4

MON1–MON4 INL (LSB)

-0.6

-0.8

-1.0
0 2.5

MON1–MON4 INPUT VOLTAGE (V)

DAC1 AND DAC2 INL

2.0

1.5

1.0

0.5

0

-0.5

DAC1 AND DAC2 INL (LSB)

-1.0

-1.5

-2.0
0

DAC1 AND DAC2 POSITION (DEC)

DS1874 toc03

2.01.51.00.5

DS1874 toc06

500400100 200 300

DS1874

SFP+ Controller with Digital LDD Interface

10 ______________________________________________________________________________________

Pin Description

PIN NAME FUNCTION

1 RSELOUT Rate-Select Output

2 SCL I2C Serial-Clock Input

3 SDA I2C Serial-Data Input/Output

4 TXF Transmit-Fault Input and Output. The output is open drain.

5 LOS Loss-of-Signal Input

6 IN1 Digital Input. General-purpose input with AS1 in SFF-8079 or RS1 in SFF-8431.

7 TXD Transm it-Disab le Input

8, 17, 21 GND Ground Connection

9 RSEL Rate-Select Input

10 TXDOUT Transmit-Disable Output

11 MON4 External Monitor Input 4

12, 13

14 MON1 External Monitor Input 1 and HBATH Quick Trip

15, 23 VCC Power-Supply Input

16 MON2 External Monitor Input 2. Feedback vo ltage for APC loop and HTXP/LTXP quick trip.

18 REFIN Reference Input for DAC1 and DAC2

19, 20 DAC1, DAC2 Delta-Sigma Output 1/2

22 N.C. No Connect ion

24 CSELOUT

25 SCLOUT

26 SDAOUT

27 LOSOUT Open-Drain Receive Loss-of-Signal Output

28 OUT1 Digital Output. General-purpose output with AS1 output in SFF-8079 or RS1 output in SFF-8431.

— EP Exposed Pad

MON3P,

MON3N

Differentia l External Monitor Input 3 and LOS Quick Trip

Chip-Select Output. Part of the 3-wire interface to the MAX3798/MAX3799 laser driver/l imiting
amplifier.

Serial-Clock Output. Part of the 3-wire interface to the MAX3798/MAX3799 laser driver/limiting
amplifier.

Serial-Data Input/Output. Part of the 3-wire interface to the MAX3798/MAX3799 laser driver/limiting
amplifier.

DS1874

SFP+ Controller with Digital LDD Interface

______________________________________________________________________________________ 11

Block Diagram

V

SDA

SCL

V

MON1

MON2

MON3P

MON3N

MON4

V

CC

CC

I2C

INTERFACE

EEPROM

256 BYTES

AT A0h

CC

ANALOG MUX

TEMPERATURE

SENSOR

MAIN MEMORY
EEPROM/SRAM

ADC CONFIGURATION/RESULTS,

SYSTEM STATUS/CONTROL BITS,

ALARMS/WARNINGS,

LOOKUP TABLES,

USER MEMORY

13-BIT

ADC

INTEGRATOR

8-BIT

QTs

POWER-ON

ANALOG

INTERRUPT

APC

9-BIT

DELTA-SIGMA

9-BIT

DELTA-SIGMA

3-WIRE

INTERFACE

V

CC

REFIN

DAC1

DAC2

SDAOUT

SCLOUT

CSELOUT

TXF

TXD

RSEL

IN1

LOS

SEE

FIGURE 13

SEE

FIGURE 12

DS1874

TXDOUT

RSELOUT

OUT1

LOSOUT

GND

DS1874

SFP+ Controller with Digital LDD Interface

12 ______________________________________________________________________________________

Detailed Description

The DS1874 integrates the control and monitoring func­tionality required to implement a VCSEL-based SFP or
SFP+ system using Maxim’s MAX3798/MAX3799 com­bined limiting amplifier and laser driver. Key compo­nents of the DS1874 are shown in the

Block Diagram

and described in subsequent sections.

MAX3798/MAX3799 DAC Control

The DS1874 controls two 9-bit DACs inside the
MAX3798/MAX3799. One DAC is used for laser bias

control while the other is used for laser modulation con­trol. The DS1874 communicates with the MAX3798/
MAX3799 over a 3-wire digital interface (see the

3-Wire

Master for Controlling the MAX3798/MAX3799

section).
The communication between the DS1874 and
MAX3798/MAX3799 is transparent to the end user.

BIAS Register/APC Control

The MAX3798/MAX3799 control their laser bias current
DAC using the APC loop within the DS1874. The APC
loop’s feedback to the DS1874 is the monitor diode
(MON2) current, which is converted to a voltage using

Typical Operating Circuit

+3.3V

100Ω

PIN-ROSA

3W

VCSEL-TOSA

BMON

LA

LDD

MAX3798/MAX3799

MODE

DAC

BIAS
DAC

DISABLE

LOS

RSEL

FAULT

3W

MON1
MON2

MON3

R

BD

R

MON

DS1874

EEPROM

QUICK

TRIP

ADC

LOS

TXF

TXD

TXDOUT

SDA

I2C

SCL

RSEL

RSELOUT

LOS

LOSOUT

TX_FAULT

TX_DISABLE

MODE_DEF2 (SDA)
MODE_DEF1 (SCL)

RATE SELECT

LOS

an external resistor. The feedback is sampled by a com­parator and compared to a digital set-point value. The
output of the comparator has three states: up, down, or
no-operation. The no-operation state prevents the output
from excessive toggling once steady state is reached.
As long as the comparator output is in either the up or
down states, the bias is adjusted by writing increment
and decrement values to the MAX3798/MAX3799
through the BIASINC register (3-wire address 13h).

The DS1874 has an LUT to allow the APC set point to
change as a function of temperature to compensate for
tracking error (TE). The TE LUT has 36 entries that
determine the APC setting in 4°C windows between

-40°C to +100°C.

MODULATION Control

The MAX3798/MAX3799 control the laser modulation
using the internal temperature-indexed LUT within the
DS1874. The modulation LUT is programmed in 2°C
increments over the -40°C to +102°C range to provide
temperature compensation for the laser’s modulation.
The modulation is updated after each temperature con­version using the 3-wire interface that connects to the
MAX3798/MAX3799. The MAX3798/MAX3799 include a
9-bit DAC. The modulation LUT is 8 bits.

Figure 1 demonstrates how the 8-bit LUT controls the
9-bit DAC with the use of a temperature control bit
(MODTC, Table 02h, Register C6h) and a temperature
index register (MODTI, Table 02h, Register C2h).

DS1874

______________________________________________________________________________________ 13

Table 1. Acronyms

SFP+ Controller with Digital LDD Interface

Figure 1. Modulation LUT Loading to MAX3798/MAX3799 MOD DAC

ACRONYM DEFINITION

ADC Analog-to-Digital Converter

AGC Automatic Gain Control

APC Automatic Power Control

APD Avalanche Photodiode

ATB Alarm Trap Bytes

BM Burst Mode

DAC Digital-to-Analog Converter

LOS Loss of Signal

LUT Lookup Table

NV Nonvolatile

QT Quic k Trip

TE Track ing Error

TIA Transimpedance Amplif ier

ROSA Receiver Optical Subassembly

SEE Shadowed EEPROM

SFF Small Form Factor

SFF-8472

SFP Small Form Factor Pluggable

SFP+ Enhanced SFP

TOSA Transmit Optical Subassembly

TXP Transm it Power

Document Defining Register Map of SFPs
and SFFs

MODTI

8

7

6

5

4

3

MAX3798/MAX3799 DAC BIT

2

1

0

MODTC = 0

MOD LUT

LOADED TO [8:1]

MOD LUT

LOADED TO [7:0]

-40 +102
TEMPERATURE (°C)

(DAC BIT 0 = 0)

MODTI

8

7

6

5

4

3

MAX3798/MAX3799 DAC BIT

2

1

0

-40 +102

MOD LUT

LOADED TO [8:1]

(DAC BIT 0 = 0)

TEMPERATURE (°C)

MODTC = 1

MOD LUT

LOADED TO [7:0]

DS1874

SFP+ Controller with Digital LDD Interface

14 ______________________________________________________________________________________

BIAS and MODULATION Control

During Power-Up

The DS1874 has two internal registers, MODULATION
and BIAS, that represent the values written to the
MAX3798/MAX3799’s modulation DAC and bias DAC
through the 3-wire interface. On power-up, the DS1874
sets the MODULATION and BIAS registers to 0. When
VCCis above POA, the DS1874 initializes the MAX3798/
MAX3799. After a temperature conversion is completed
and if the VCC LO alarm is enabled, an additional V

CC

conversion above the customer-defined VCC LO alarm
level is required before the MAX3798/MAX3799 MODU­LATION register is updated with the value determined
by the temperature conversion and the modulation LUT.

When the MODULATION register is set, the BIAS regis­ter is set to a value equal to ISTEP (see Figure 2). The
startup algorithm checks if this bias current causes a
feedback voltage above the APC set point, and if not, it
continues increasing the BIAS register by ISTEP until the
APC set point is exceeded. When the APC set point is
exceeded, the device begins a binary search to quickly
reach the bias current corresponding to the proper
power level. After the binary search is completed, the
APC integrator is enabled and single LSB steps are
used to tightly control the average power.

The TXP HI, TXP LO, HBAL, and BIAS MAX QT alarms
are masked until the binary search is completed.

However, the BIAS MAX alarm is monitored during this
time to prevent the BIAS register from exceeding
IBIASMAX. During the bias current initialization, the
BIAS register is not allowed to exceed IBIASMAX. If this
occurs during the ISTEP sequence, then the binary
search routine is enabled. If IBIASMAX is exceeded
during the binary search, the next smaller step is acti­vated. ISTEP or binary increments that would cause the
BIAS register to exceed IBIASMAX are not taken.
Masking the alarms until the completion of the binary
search prevents false positive alarms during startup.

ISTEP is programmed by the customer using Table
02h, Register BBh. During the first steps, the MAX3798/
MAX3799’s bias DAC is directly written using
SET_IBIAS (3-wire address 09h). ISTEP should be pro­grammed to the maximum safe increase that is allow­able during startup. If this value is programmed too
low, the DS1874 still operates, but it could take signifi­cantly longer for the algorithm to converge and hence
to control the average power.

If a fault is detected, and TXD is toggled to reenable
the outputs, the DS1874 powers up following a similar
sequence to an initial power-up. The only difference is
that the DS1874 already has determined the present
temperature, so the t

INIT

time is not required for the
DS1874 to recall the APC and MOD set points from
EEPROM.

Figure 2. Power-Up Timing

V

V

CC

MODULATION REGISTER

BIAS REGISTER

BIAS SAMPLE

POA

t

INIT

ISTEP

t

SEARCH

4x ISTEP

3x ISTEP

2x ISTEP

12345678910111213

BINARY SEARCH

APC INTEGRATOR ON

BIAS and MODULATION Registers as a

Function of Transmit Disable (TXD)

If TXD is asserted (logic 1) during normal operation, the
outputs are disabled within t

OFF

. When TXD is deassert­ed (logic 0), the DS1874 sets the MODULATION regis­ter with the value associated with the present
temperature, and initializes the BIAS register using the
same search algorithm as done at startup. When
asserted, soft TXD (TXDC) (Lower Memory, Register
6Eh) would allow a software control identical to the TXD
pin (see Figure 3).

APC and Quick-Trip Timing

As shown in Figure 4, the DS1874’s input comparator is
shared between the APC control loop and the quick­trip alarms (TXP HI, TXP LO, LOS, and BIAS HI). The
comparator polls the alarms in a multiplexed sequence.
Five of every eight comparator readings are used for
APC loop bias-current control. The other three updates
are used to check the HTXP/LTXP (monitor diode volt­age), the HBATH (MON1), and LOS (MON3) signals
against the internal APC, BIAS, and MON3 reference,
respectively. If the last APC comparison was higher
than the APC set point, it makes an HTXP comparison,
and if it is lower, it makes an LTXP comparison.
Depending on the results of the comparison, the corre­sponding alarms and warnings (TXP HI, TXP LO) are
asserted or deasserted.

The DS1874 has a programmable comparator sample
time based on an internally generated clock to facilitate

a wide variety of external filtering options and time
delays resulting from writing values to the MAX3798/
MAX3799’s bias DAC. The UPDATE RATE register
(Table 02h, Register 88h) determines the sampling
time. Samples occur at a regular interval, t

REP

. Table 2
shows the sample rate options available. Any quick-trip
alarm that is detected by default remains active until a
subsequent comparator sample shows the condition no
longer exists. A second bias current monitor (BIAS
MAX) compares the MAX3798/MAX3799’s BIAS DAC’s
code to a digital value stored in the IBIASMAX register.
This comparison is made at every bias current update
to ensure that a high-bias current is quickly detected.

An APC sample that requires an update of the BIAS
register causes subsequent APC samples to be

DS1874

SFP+ Controller with Digital LDD Interface

______________________________________________________________________________________ 15

Figure 4. APC Loop and Quick-Trip Sample Timing

Table 2. Update Rate Timing

Figure 3. TXD Timing

APC_SR[2:0]

000b 800

001b 1200

010b 1600

011b 2000

100b 2800

101b 3200

110b 4400

111b 6400

SAMPLE PERIOD (t

(ns)

REP

)

TXD

BIAS REGISTER

MODULATION REGISTER

APC QUICK-TRIP SAMPLE TIMES

HBIAS

SAMPLE

APC

SAMPLE

t

REP

APC

SAMPLE

t

OFF

t

OFF

APC

SAMPLE

APC

SAMPLE

t

ON

t

ON

APC

SAMPLE

HTXP/LTXP

SAMPLE

LOS

SAMPLE

HBIAS

SAMPLE

APC

SAMPLE

DS1874

SFP+ Controller with Digital LDD Interface

16 ______________________________________________________________________________________

ignored until the end of the 3-wire communication that
updates the MAX3798/MAX3799’s BIAS DAC, plus an
additional 16 sample periods (t

REP

).

Monitors and Fault Detection

Monitors

Monitoring functions on the DS1874 include five quick-trip
comparators and six ADC channels. This monitoring
combined with the alarm enables (Table 01h/05h) deter­mines when/if the DS1874 turns off the MAX3798/
MAX3799 DACs and triggers the TXF and TXDOUT out­puts. All the monitoring levels and interrupt masks are
user programmable.

Five Quick-Trip Monitors and Alarms

Five quick-trip monitors are provided to detect potential
laser safety issues and LOS status. These monitor the
following:

1) High Bias Current (HBATH)

2) Low Transmit Power (LTXP)

3) High Transmit Power (HTXP)

4) Max Output Current (IBIASMAX)

5) Loss-of-Signal (LOS LO)

The high-transmit and low-transmit power quick-trip reg­isters (HTXP and LTXP) set the thresholds used to com­pare against the MON2 voltage to determine if the
transmit power is within specification. The HBATH quick
trip compares the MON1 input (generally from the
MAX3798/MAX3799 bias monitor output) against its
threshold setting to determine if the present bias current
is above specification. The BIAS MAX quick trip deter­mines if the BIAS register is above specification. The
BIAS register is not allowed to exceed the value set in
the IBIASMAX register. When the DS1874 detects that
the bias is at the limit it sets the BIAS MAX status bit
and holds the BIAS register setting at the IBIASMAX
level. The bias and power quick trips are routed to the
TXF through interrupt masks to allow combinations of
these alarms to be used to trigger these outputs. The
user can program up to eight different temperature­indexed threshold levels for MON1 (Table 02h,
Registers D0h–D7h). The LOS LO quick trip compares
the MON3 input against its threshold setting to deter­mine if the present received power is below the specifi­cation. The LOS LO quick trip can be used to set the
LOSOUT pin. These alarms can be latched using Table
02h, Register 8Ah.

Six ADC Monitors and Alarms

The ADC monitors six channels that measure tempera­ture (internal temp sensor), VCC, and MON1–MON4
using an analog multiplexer to measure them round

robin with a single ADC (see the

ADC Timing

section).
The five voltage channels have a customer-programma­ble full-scale range and all channels have a customer­programmable offset value that is factory programmed to
default value (see Table 3). Additionally, MON1–MON4
can right-shift results by up to 7 bits before the results
are compared to alarm thresholds or read over the I2C
bus. This allows customers with specified ADC ranges to
calibrate the ADC full scale to a factor of 1/2nof their
specified range to measure small signals. The DS1874
can then right-shift the results by n bits to maintain the bit
weight of their specification (see the

Right-Shifting ADC

Result

and

Enhanced RSSI Monitoring (Dual-Range

Functionality)

sections).

The ADC results (after right-shifting, if used) are com­pared to the alarm and warning thresholds after each
conversion, and the corresponding alarms are set,
which can be used to trigger the TXF output. These
ADC thresholds are user programmable, as are the
masking registers that can be used to prevent the
alarms from triggering the TXF output.

ADC Timing

There are six analog channels that are digitized in a
round-robin fashion in the order shown in Figure 5. The
total time required to convert all six channels is tRR(see
the

Electrical Characteristics

for details).

Right-Shifting ADC Result

If the weighting of the ADC digital reading must con­form to a predetermined full-scale (PFS) value defined
by a standard’s specification (e.g., SFF-8472), then
right-shifting can be used to adjust the PFS analog
measurement range while maintaining the weighting of
the ADC results. The DS1874’s range is wide enough to
cover all requirements; when the maximum input value
is ≤ 1/2 of the FS value, right-shifting can be used to
obtain greater accuracy. For instance, the maximum
voltage might be 1/8 the specified PFS value, so only
1/8 the converter’s range is effective over this range.
An alternative is to calibrate the ADC’s full-scale range
to 1/8 the readable PFS value and use a right-shift
value of 3. With this implementation, the resolution of

Table 3. ADC Default Monitor Full-Scale
Ranges

SIGNAL

Temperature (°C) 127.996 7FFF -128 8000

VCC (V) 6.5528 FFF8 0 0000

MON1–MON4 (V) 2.4997 FFF8 0 0000

+FS

SIGNAL

+FS

hex

-FS

SIGNAL

-FS

hex

DS1874

SFP+ Controller with Digital LDD Interface

______________________________________________________________________________________ 17

the measurement is increased by a factor of 8, and
because the result is digitally divided by 8 by right­shifting, the bit weight of the measurement still meets
the standard’s specification (i.e., SFF-8472).

The right-shift operation on the ADC result is carried out
based on the contents of right-shift control registers (Table
02h, Registers 8Eh–8Fh) in EEPROM. Four analog chan­nels, MON1–MON4, each have 3 bits allocated to set the
number of right-shifts. Up to seven right-shift operations
are allowed and are executed as a part of every conver­sion before the results are compared to the high-alarm
and low-alarm levels, or loaded into their corresponding
measurement registers (Lower Memory, Registers
64h–6Bh). This is true during the setup of internal calibra­tion as well as during subsequent data conversions.

Enhanced RSSI Monitoring (Dual-Range

Functionality)

The DS1874 offers a feature to improve the accuracy
and range of MON3, which is most commonly used for
monitoring RSSI. The accuracy of the RSSI measure­ments is increased at the small cost of reduced range
(of input signal swing). The DS1874 eliminates this
trade-off by offering “dual range” calibration on the
MON3 channel (see Figure 6). This feature enables
right-shifting (along with its gain and offset settings)
when the input signal is below a set threshold (within the

range that benefits using right-shifting) and then automat­ically disables right-shifting (recalling different gain and
offset settings) when the input signal exceeds the thresh­old. Also, to prevent “chattering,” hysteresis prevents
excessive switching between modes in addition to ensur­ing that continuity is maintained. Dual-range operation is
enabled by default (factory programmed in EEPROM).
However, it can easily be disabled through the RSSI_FC
and RSSI_FF bits, which are described in the

Register
Descriptions

section. When dual-range operation is dis­abled, MON3 operates identically to the other MON
channels, although featuring a differential input.

Dual-range functionality consists of two modes of opera­tion: fine mode and coarse mode. Each mode is calibrat­ed for a unique transfer function, hence the term, dual
range. Table 5 highlights the registers related to MON3.
Fine mode is equivalent to the other MON channels. Fine
mode is calibrated using the gain, offset, and right-shift­ing registers at locations shown in Table 5 and is ideal
for relatively small analog input voltages. Coarse mode is
automatically switched to when the input exceeds a
threshold (to be discussed in a subsequent paragraph).
Coarse mode is calibrated using different gain and offset
registers, but lacks right-shifting (since coarse mode is
only used on large input signals). The gain and offset
registers for coarse mode are also shown in Table 5.
Additional information for each of the registers can be
found in the

Register Descriptions

section.

Dual-range operation is transparent to the end user.
The results of MON3 analog-to-digital conversions are
still stored/reported in the same memory locations
(68h–69h, Lower Memory) regardless of whether the
conversion was performed in fine mode or coarse
mode. The only way to tell which mode generated the
digital result is by reading the RSSIS bit.

When the DS1874 is powered up, analog-to-digital con­versions begin in a round-robin fashion. Every MON3
timeslice begins with a fine mode analog-to-digital con­version (using fine mode’s gain, offset, and right-shifting
settings). See the flowchart in Figure 7 for more details.

Figure 6. MON3 Differential Input for High-Side RSSI

Figure 5. ADC Round-Robin Timing

ONE ROUND-ROBIN ADC CYCLE

TEMP V

NOTE: IF THE VCC LO ALARM IS ENABLED AT POWER-UP, THE ADC ROUND-ROBIN TIMING CYCLES BETWEEN TEMPERATURE AND VCC ONLY UNTIL VCC
IS ABOVE THE V

100Ω

ROSA

ALARM LOW THRESHOLD.

CC

V

CC

MON3P

MON3N

DS1874

MON1 MON2 MON3 MON4 TEMP

CC

ADC

t

RR

DS1874

SFP+ Controller with Digital LDD Interface

18 ______________________________________________________________________________________

Then, depending on whether the last MON3 timeslice
resulted in a coarse-mode conversion and also depend­ing on the value of the current fine conversion, decisions
are made whether to use the current fine-mode conver­sion result or to make an additional conversion (within
the same MON3 timeslice), using coarse mode (using
coarse mode’s gain and offset settings and no right­shifting) and reporting the coarse-mode result. The flow­chart in Figure 7 also illustrates how hysteresis is

implemented. The fine-mode conversion is compared to
one of two thresholds. The actual threshold values are a
function of the number of right-shifts being used. With
the use of right-shifting, the fine mode full-scale is pro­grammed to (1/2

N

th) of the coarse mode full-scale. The
DS1874 now auto ranges to choose the range that gives
the best resolution for the measurement. Hysteresis is
applied to eliminate chatter when the input resides at
the boundary of the two ranges. See Figure 7 for details.
Table 4 shows the threshold values for each possible
number of right-shifts.

The RSSI_FF and RSSI_FC bits are used to force fine­mode or coarse-mode conversions, or to disable the
dual-range functionality. Dual-range functionality is
enabled by default (both RSSI_FC and RSSI_FF are
factory programmed to 0 in EEPROM). It can be dis­abled by setting RSSI_FC to 0 and RSSI_FF to 1. These
bits are also useful when calibrating MON3. For addi­tional information, see Figure 19.

Table 5. MON3 Configuration Registers

Figure 7. RSSI Flowchart

Table 4. MON3 Hysteresis Threshold
Values

*

This is the minimum reported coarse-mode conversion.

MON3

TIMESLICE

PERFORM FINE-

MODE CONVERSION

DID PRIOR MON3

TIMESLICE RESULT IN A

COARSE CONVERSION?

(LAST RSSI = 1?)

DID CURRENT FINE-

MODE CONVERSION

REACH MAX?

LAST RSSI = 0

REPORT FINE

CONVERSION RESULT

NUMBER OF

RIGHT-SHIFTS

0 FFF8 F000

1 7FFC 7800

2 3FFE 3C00

3 1FFF 1E00

Y

N

Y

N

N

WAS CURRENT FINE-

MODE CONVERSION

≥ 93.75% OF FS?

Y

PERFORM COARSE­MODE CONVERSION

LAST RSSI = 1

REPORT COARSE

CONVERSION RESULT

RIGHT-SHIFT

MON3 VALUE 68h–69h, Lower Memory

4 0FFF 0F00

5 07FF 0780

6 03FF 03C0

7 01FF 01E0

REGISTER FINE MODE COARSE MODE

GAIN 98h–99h, Table 02h 9Ch–9Dh, Table 04h

OFFSET A8h–A9h, Table 02h ADh–ACh, Table 04h

0

CNFGC 8Bh, Table 02h

CONFIG

(RSSIS BIT)

FINE MODE

MAX (hex)

8Fh, Table 04h —

77h, Lower Memory

COARSE MODE

MIN* (hex)

END OF MON3

TIMESLICE

DS1874

Low-Voltage Operation

The DS1874 contains two power-on reset (POR) levels.
The lower level is a digital POR (POD) and the higher
level is an analog POR (POA). At startup, before the
supply voltage rises above POA, the outputs are dis­abled, all SRAM locations are set to their defaults,
shadowed EEPROM (SEE) locations are zero, and all
analog circuitry is disabled. When VCCreaches POA,
the SEE is recalled, and the analog circuitry is enabled.
While V

CC

remains above POA, the device is in its nor­mal operating state, and it responds based on its non­volatile configuration. If during operation V

CC

falls
below POA, but is still above POD, then the SRAM
retains the SEE settings from the first SEE recall, but the
device analog is shut down and the outputs disabled. If
the supply voltage recovers back above POA, then the
device immediately resumes normal operation. If the
supply voltage falls below POD, then the device SRAM
is placed in its default state and another SEE recall is
required to reload the nonvolatile settings. The EEPROM
recall occurs the next time V

CC

exceeds POA. Figure 8

shows the sequence of events as the voltage varies.

Any time VCCis above POD, the I2C interface can be
used to determine if VCCis below the POA level. This is
accomplished by checking the RDYB bit in the STATUS
(Lower Memory, Register 6Eh) byte. RDYB is set when
VCCis below POA; when VCCrises above POA, RDYB

is timed (within 500µs) to go to 0, at which point the
part is fully functional.

For all device addresses sourced from EEPROM (Table
02h, Register 8Ch), the default device address is A2h
until V

CC

exceeds POA, allowing the device address to

be recalled from the EEPROM.

Power-On Analog (POA)

POA holds the DS1874 in reset until VCCis at a suitable
level (V

CC

> POA) for the device to accurately measure
with its ADC and compare analog signals with its quick­trip monitors. Because VCCcannot be measured by the
ADC when VCCis less than POA, POA also asserts the
VCC LO alarm, which is cleared by a VCCADC conver­sion greater than the customer-programmable V

CC

alarm low ADC limit. This allows a programmable limit
to ensure that the headroom requirements of the trans­ceiver are satisfied during a slow power-up. The TXF
output does not latch until there is a conversion above
VCClow limit. The POA alarm is nonmaskable. The TXF
output is asserted when VCCis below POA. See the

Low-Voltage Operation

section for more information.

Delta-Sigma Outputs (DAC1 and DAC2)

Two delta-sigma outputs are provided, DAC1 and
DAC2. With the addition of an external RC filter, these
outputs provide two 9-bit resolution analog outputs with
the full-scale range set by the input REFIN. Each output

SFP+ Controller with Digital LDD Interface

______________________________________________________________________________________ 19

Figure 8. Low-Voltage Hysteresis Example

SEE RECALL

V

POA

V

CC

V

POD

PRECHARGED

SEE RECALLED VALUE RECALLED VALUE

TO 0

SEE RECALL

PRECHARGED TO 0

PRECHARGED

TO 0

DS1874

is either manually controlled or controlled using a tem­perature-indexed LUT. A delta-sigma is a digital output
using pulse-density modulation. It provides much lower
output ripple than a standard digital PWM output given
the same clock rate and filter components. Before t

INIT

,

the DAC1 and DAC2 outputs are high impedance.

The external RC filter components are chosen based
on ripple requirements, output load, delta-sigma fre­quency, and desired response time. A recommended
filter is shown in Figure 9.

The DS1874’s delta-sigma outputs are 9 bits. For illus­trative purposes, a 3-bit example is provided. Each
possible output of this 3-bit delta-sigma DAC is given in
Figure 10.

In LUT mode, DAC1 and DAC2 are each controlled by a
separate 8-bit, 4°C-resolution, temperature-addressed
LUT. The delta-sigma outputs use a 9-bit structure. The
8-bit LUTs are either loaded directly into the MSBs (8:1)
or the LSBs (7:0). This is determined by DAC1TI (Table
02h, Register C3h), DAC2TI (Table 02h, Register C4h),
DAC1TC (Table 02h, Register C6h, bit 6), and DAC2TC
(Table 02h, Register C6h, bit 5). See Figure 11 for more
details. The DAC1 LUT (Table 07h) and DAC2 LUT
(Table 08h) are nonvolatile and password-2 protected.

The reference input, REFIN, is the supply voltage for
the output buffer of DAC1 and DAC2. The voltage con­nected to REFIN must be able to support the edge rate
requirements of the delta-sigma outputs. In a typical
application, a 0.1µF capacitor should be connected
between REFIN and ground.

20 ______________________________________________________________________________________

Figure 11. DAC1/DAC2 LUT Assignments

SFP+ Controller with Digital LDD Interface

Figure 10. Delta-Sigma Outputs

Figure 9. Recommended RC Filter for DAC1/DAC2

DAC1/DAC2

3.24kΩ 3.24kΩ

0.01μF 0.01μF

DS1874

0

1

2

3

4

5

6

7

OUTPUT

DAC[1/2]TI

8

7

6

5

4

3

DELTA-SIGMA DACA OR DACB

2

1

0

DAC[1/2]TC = 0

LUT LOADED TO [8:1]

(DAC BIT 0 = 0)

LUT LOADED TO [7:0]

-40 +102
TEMPERATURE (°C)

8

7

6

5

LUT LOADED TO [8:1]

4

3

DELTA-SIGMA DACA OR DACB

2

1

0

(DAC BIT 0 = 0)

-40 +102

DAC[1/2]TI

DAC[1/2]TC = 1

LUT LOADED TO [7:0]

TEMPERATURE (°C)

DS1874

SFP+ Controller with Digital LDD Interface

______________________________________________________________________________________ 21

Digital I/O Pins

Five digital input and five digital output pins are provid­ed for monitoring and control.

LOS, LOSOUT

By default (LOSC = 1, Table 02h, Register 89h), the
LOS pin is used to convert a standard comparator out­put for loss of signal (LOS) to an open-collector output.
This means the mux shown in the

Block Diagram

by
default selects the LOS pin as the source for the
LOSOUT output transistor. The output of the mux can
be read in the STATUS byte (Table 01h, Register 6Eh)
as the RXL bit. The RXL signal can be inverted (INV
LOS = 1) before driving the open-drain output transistor
using the XOR gate provided. Setting LOSC = 0 config­ures the mux to be controlled by LOS LO, which is dri­ven by the output of the LOS quick trip (Table 02h,
Registers BEh and BFh). The mux setting (stored in
EEPROM) does not take effect until V

CC

> POA, allow-

ing the EEPROM to recall.

IN1, RSEL, OUT1, RSELOUT

The digital input IN1 and RSEL pins primarily serve to
meet the rate-select requirements of SFP and SFP+.
They also serve as general-purpose inputs. OUT1 and

RSELOUT are driven by a combination of the IN1,
RSEL, and logic dictated by control registers in the
EEPROM (Figure 13). The levels of IN1 and RSEL can
be read using the STATUS register (Lower Memory,
Register 6Eh). The open-drain output OUT1 can be
controlled and/or inverted using the CNFGB register
(Table 02h, Register 8Ah). The open-drain RSELOUT
output is software-controlled and/or inverted through
the Status register and CNFGA register (Table 02h,
Register 89h). External pullup resistors must be provid­ed on OUT1 and RSELOUT to realize high logic levels.

TXF, TXD, TXDOUT

TXDOUT is generated from a combination of TXF, TXD,
and the internal signal FETG. A software control identi­cal to TXD is available (TXDC, Lower Memory, Register
6Eh). A TXD pulse is internally extended (TXD

EXT

) by

time t

INITR1

to inhibit the latching of low alarms and
warnings related to the APC loop to allow for the loop to
stabilize. The nonlatching alarms and warnings are TXP
LO, LOS LO, and MON1–MON4 LO alarms and warn­ings. In addition, TXP LO is disabled from creating
FETG. TXF is both an input and an output (Figure 12).
See the

Transmit Fault (TXF) Output

section for a

detailed explanation of TXF. Figure 12 shows that the

Figure 12. Logic Diagram 1

V

CC

R

PU

TXD

TXDC

TXP HI FLAG

TXP HI ENABLE

BIAS MAX

BIAS MAX ENABLE

HBAL FLAG

HBAL ENABLE

TXP LO FLAG

TXP LO ENABLE

TXDS

TXD

EXT

FAULT RESET TIMER

(130ms)

OUT IN

IN

OUT

SET BIAS REGISTER TO 0 AND
MAX3798/MAX3799
SET_IMOD TO 0

R

C

Q

C

Q

D

S

POWER-ON

FETG

MINT

HBAL FLAG

TXP LO FLAG
TXP LO FLAG

BIAS MAX FLAG

RESET

TXD

TXDIO

TXDFG

TXDFLT

TXDOUT

TXF

TXF

DS1874

same signals and faults can also be used to generate
the internal signal FETG (Table 01h/05h, Registers FAh
and FBh). FETG is used to send a fast “turn-off” com­mand to the laser driver. The intended use is a direct
connection to the MAX3798/MAX3799’s TXD input if
this is desired. When V

CC

< POA, TXDOUT is high

impedance.

Transmit Fault (TXF) Output

TXF can be triggered by all alarms, warnings, and
quick trips (Figure 12). The six ADC alarms, warnings,
and the LOS quick trips require enabling (Table
01h/05h, Registers F8h and FDh). See Figures 14a and
14b for nonlatched and latched operation. Latching of
the alarms is controlled by the CNFGB and CNFGC
registers (Table 02h, Registers 8Ah–8Bh).

Die Identification

The DS1874 has an ID hardcoded in its die. Two regis­ters (Table 02h, Registers CEh–CFh) are assigned for
this feature. The CEh register reads 74h to identify the
part as the DS1874, while the CFh register reads the
current device version.

3-Wire Master for Controlling

the MAX3798/MAX3799

The DS1874 controls the MAX3798/MAX3799 over a
proprietary 3-wire interface. The DS1874 acts as the
master, initiating communication with and generating
the clock for the MAX3798/MAX3799. It is a 3-pin inter­face consisting of SDAOUT (a bidirectional data line),
an SCLOUT clock signal, and a CSELOUT chip-select
output (active high).

Protocol

The DS1874 initiates a data transfer by asserting the
CSELOUT pin. It then starts to generate a clock signal

22 ______________________________________________________________________________________

Figure 14b. TXF Latched Operation

SFP+ Controller with Digital LDD Interface

Figure 14a. TXF Nonlatched Operation

Figure 13. Logic Diagram 2

IN1S OUT1

INVOUT1

IN1C

IN1

RSEL

LOS

LOS LO

RSELS

RSELC

INV LOSLOSC

MUX

RXL

RSELOUT

LOSOUT

DETECTION OF TXF FAULT

TXF

DETECTION OF TXF FAULT

TXD

TXF

after the CSELOUT has been set to 1. Each operation
consists of 16-bit transfers (15-bit address/data, 1-bit
RWN). All data transfers are MSB first.

Write Mode (RWN = 0): The master generates 16 clock
cycles at SCLOUT in total. It outputs 16 bits (MSB first)
to the SDAOUT line at the falling edge of the clock. The
master closes the transmission by setting the
CSELOUT to 0.

Read Mode (RWN = 1): The master generates 16 clock
cycles at SCLOUT in total. It outputs 8 bits (MSB first)
to the SDAOUT line at the falling edge of the clock. The
SDAOUT line is released after the RWN bit has been
transmitted. The slave outputs 8 bits of data (MSB first)
at the rising edge of the clock. The master samples
SDAOUT at the falling edge of SCLOUT. The master
closes the transmission by setting the CSELOUT to 0.

3-Wire Interface Timing

Figure 15 shows the 3-wire interface timing. Figure 16
shows the 3-wire state machine. See the

3-Wire Digital

Interface Specification

table for more information.

DS1874 and MAX3798/MAX3799

Communication

Normal Operation

The majority of the communication between the two
devices consists of bias adjustments for the APC loop.
After each temperature conversion, the laser modula­tion setting must be updated. Status registers TXSTAT1
and TXSTAT2 are read between temperature updates
at a regular interval: tRR(see the

Electrical Characteristics

table). The results are stored in TXSTAT1 and TXSTAT2
(Table 02h, F4h–F5h).

Manual Operation

The MAX3798/MAX3799 are manually controllable
using four registers in the DS1874: 3WCTRL,
ADDRESS, WRITE, and READ. Commands can be
manually issued while the DS1874 is in normal opera­tion mode. It is also possible to suspend normal 3-wire
commands so that only manual operation commands
are sent (3WCTRL, Table 02h, Register F8h).

DS1874

SFP+ Controller with Digital LDD Interface

______________________________________________________________________________________ 23

Figure 15. 3-Wire Timing

BIT NAME DESCRIPTION

15:9 Address 7-bit internal register address

8 RWN 0: write; 1: read

7:0 Data 8-bit read or write data

WRITE MODE

CSELOUT

SCLOUT

SDAOUT

READ MODE

CSELOUT

SCLOUT

SDAOUT

t

L

t

L

A6 A5 A4 A3 A2 A1 A0

12345678A69 1011121314150

t

DS

A5 A4 A3 A2 A1 RWN D7 D6 D5 D4 D3 D2 D1 D0

t

DH

1234567891011121314150

t

DS

t

DH

A0

D7 D6 D5 D4 D3 D2 D1 D0RWN

t

T

t

T

DS1874

24 ______________________________________________________________________________________

Figure 16. 3-Wire State Machine

SFP+ Controller with Digital LDD Interface

RESET FLAGS HERE

POR

YES

SET TXD FLAG HERE

TXD_LATCHED = 1

SET RTXPOR2_FLAG HERE

READ TXPOR1

TX_POR = 1?

NO

WRITE MOD, BIAS = 00

UPDATE CTRL

TXD = = 0?

YES

READ TXPOR2

UPDATE

MODULATION

YES

NO

TXD HIGH_STDBY

1011

YES

TXD = = 0?

NO

NO

READ TXPOR3

TX_POR = = 1?

START APC

LOOP

APC_BINARY = = 1?

YES

BIASINC = = 1?

YES

TXDIS = 1?

STROBE

NO

NO

READ TXPOR4

TX_POR = = 1?

NO

MAN_MODE_RDWR = 1?

TXD_FLAG = = 1
OR TXDIS = 1 OR

RTXPOR2 FLAG

NO

MODINC = = 1?

NO

YES

YES

READ/WRITE

MANMODE

INCREMENT

MODULATION

NO

TX_POR = = 1?

NO

MODINC = 1?

MAN_MODE_RDWR = 1?

YES

BIASINC = = 1?

YES YES

UPDATE BIAS

APC_BINARY = = 1?

NO

STANDBY

NO

TXD_FLAG = = 1? OR

RTXPOR2 FLAG = 1

NO

BIASINC = = 1?

NO

TEMP_CONV_START = = 1?

AND TXDIS = 0

UPDATE

TXSTAT, BIAS, MOD

YES YES

Initialization

During initialization, the DS1874 transfers all its 3-wire
EEPROM control registers to the MAX3798/MAX3799.

The 3-wire control registers include the following:

• RXCTRL1

• RXCTRL2

• SET_CML

• SET_LOS

• TXCTRL

• IMODMAX

• IBIASMAX

• SET_PWCTRL

• SET_TXDE

The control registers are first written when V

CC

exceeds
POA. They are also written if the MAX3798/MAX3799
TX_POR bit is set high (visible in 3W TXSTAT1, bit 7). In
the MAX3798/MAX3799, this bit is “sticky” (latches high
and is cleared on a read). They are also updated on a
rising edge of TXD. Any time one of these events
occurs, the DS1874 reads and updates TXSTAT1 and
TXSTAT2 and sets SET_IBIAS and SET_IMOD in the
MAX3798/MAX3799 to 0.

DS1874

SFP+ Controller with Digital LDD Interface

______________________________________________________________________________________ 25

MAX3798/MAX3799 Register Map and DS1874 Corresponding Location

Note: This register is not present in the DS1874. To access this register, use manual operation (see the

Manual Operation

section).

MAX3798/MAX3799 REGISTER FUNCTION REGISTER NAME DS1874 LOCATION

Receiver Control 1 RXCTRL1 Table 02h, E8h

Receiver Control 2 RXCTRL2 Table 02h, E9h

Receiver Status RXSTAT Lower Memory, 6Eh, Bit1

Output CML Level Setting SET_CML Table 02h, EAh

LOS Threshold Level Setting SET_LOS Table 02h, EBh

Transm itter Control TXCTRL Table 02h, ECh

Transm itter Status 1 TXSTAT1 Table 02h, FCh

Transm itter Status 2 TXSTAT2 Table 02h, FDh

Bias Current Setting SET_IBIAS/BIAS Table 02h, CBh –CCh

Modulation Current Setting SET_IMOD/MODULATION Table 02h, 8Ah–8Bh

Maximum Modulation Current Setting IMODMAX Table 02h, EDh

Max imum Bias Current Setting IBIASMAX Table 02h, EEh

Modulation Current Increment Setting MODINC (see Note)

Automatical ly performed by APC loop. Disable

Bias Current Increment Setting BIASINC

Mode Control MODECTRL (see Note)

Transm itter Pulse-Width Control SET_PWCTRL Table 02h, EFh

Transm itter Deemphasis Control SET_TXDE Table 02h, F0h

APC before using 3-wire manual mode. Manual
Mode: Table 02h, F8h–FAh

DS1874

SFP+ Controller with Digital LDD Interface

26 ______________________________________________________________________________________

Figure 17. I2C Timing

I2C Communication

I2C Definitions

The following terminology is commonly used to
describe I2C data transfers.

Master device: The master device controls the
slave devices on the bus. The master device gen­erates SCL clock pulses and START and STOP
conditions.

Slave devices: Slave devices send and receive
data at the master’s request.

Bus idle or not busy: Time between STOP and
START conditions when both SDA and SCL are inac­tive and in their logic-high states.

START condition: A START condition is generated
by the master to initiate a new data transfer with a
slave. Transitioning SDA from high to low while SCL
remains high generates a START condition. See
Figure 17 for applicable timing.

STOP condition: A STOP condition is generated by
the master to end a data transfer with a slave.
Transitioning SDA from low to high while SCL
remains high generates a STOP condition. See
Figure 17 for applicable timing.

Repeated START condition: The master can use a
repeated START condition at the end of one data
transfer to indicate that it will immediately initiate a
new data transfer following the current one.
Repeated STARTs are commonly used during read

operations to identify a specific memory address to
begin a data transfer. A repeated START condition
is issued identically to a normal START condition.
See Figure 17 for applicable timing.

Bit write: Transitions of SDA must occur during the
low state of SCL. The data on SDA must remain valid
and unchanged during the entire high pulse of SCL
plus the setup and hold time requirements (Figure

17). Data is shifted into the device during the rising
edge of the SCL.

Bit read: At the end a write operation, the master
must release the SDA bus line for the proper amount
of setup time (Figure 17) before the next rising edge
of SCL during a bit read. The device shifts out each
bit of data on SDA at the falling edge of the previous
SCL pulse and the data bit is valid at the rising edge
of the current SCL pulse. Remember that the master
generates all SCL clock pulses, including when it is
reading bits from the slave.

Acknowledgement (ACK and NACK): An acknowl­edgement (ACK) or not acknowledge (NACK) is
always the ninth bit transmitted during a byte trans­fer. The device receiving data (the master during a
read or the slave during a write operation) performs
an ACK by transmitting a zero during the ninth bit. A
device performs a NACK by transmitting a one dur­ing the 9th bit. Timing (Figure 17) for the ACK and
NACK is identical to all other bit writes. An ACK is
the acknowledgment that the device is properly
receiving data. A NACK is used to terminate a read

SDA

t

BUF

t

LOW

SCL

t

HD:STA

STOP START REPEATED

NOTE: TIMING IS REFERENCED TO V

IL(MAX)

AND V

IH(MIN)

t

R

t

HD:DAT

.

t

HIGH

t

F

t

SU:DAT

START

t

SU:STA

t

HD:STA

t

SP

t

SU:STO

sequence or as an indication that the device is not
receiving data.

Byte write: A byte write consists of 8 bits of informa­tion transferred from the master to the slave (most
significant bit first) plus a 1-bit acknowledgement
from the slave to the master. The 8 bits transmitted
by the master are done according to the bit-write
definition and the acknowledgement is read using
the bit-read definition.

Byte read: A byte read is an 8-bit information trans­fer from the slave to the master plus a 1-bit ACK or
NACK from the master to the slave. The 8 bits of
information that are transferred (most significant bit
first) from the slave to the master are read by the
master using the bit-read definition, and the master
transmits an ACK using the bit-write definition to
receive additional data bytes. The master must
NACK the last byte read to terminate communication
so the slave returns control of SDA to the master.

Slave address byte: Each slave on the I2C bus
responds to a slave address byte sent immediately
following a START condition. The slave address byte
contains the slave address in the most significant 7
bits and the R/W bit in the least significant bit.

The DS1874 responds to two slave addresses. The
auxiliary memory always responds to a fixed I2C
slave address, A0h. The Lower Memory and Tables
00h–08h respond to I2C slave addresses that can
be configured to any value between 00h–FEh using
the DEVICE ADDRESS byte (Table 02h, Register
8Ch). The user also must set the ASEL bit (Table
02h, Register 89h) for this address to be active. By
writing the correct slave address with R/W = 0, the
master indicates it will write data to the slave. If R/W
= 1, the master reads data from the slave. If an
incorrect slave address is written, the DS1874
assumes the master is communicating with another
I2C device and ignores the communications until the
next START condition is sent. If the main device’s
slave address is programmed to be A0h, access to
the auxiliary memory is disabled.

Memory address: During an I2C write operation to
the DS1874, the master must transmit a memory
address to identify the memory location where the
slave is to store the data. The memory address is
always the second byte transmitted during a write
operation following the slave address byte.

I2C Protocol

Writing a single byte to a slave: The master must
generate a START condition, write the slave address
byte (R/W = 0), write the memory address, write the

byte of data, and generate a STOP condition.
Remember the master must read the slave’s
acknowledgement during all byte-write operations.

Writing multiple bytes to a slave: To write multiple
bytes to a slave, the master generates a START con­dition, writes the slave address byte (R/W = 0),
writes the memory address, writes up to 8 data
bytes, and generates a STOP condition. The
DS1874 writes 1 to 8 bytes (one page or row) with a
single write transaction. This is internally controlled
by an address counter that allows data to be written
to consecutive addresses without transmitting a
memory address before each data byte is sent. The
address counter limits the write to one 8-byte page
(one row of the memory map). Attempts to write to
additional pages of memory without sending a STOP
condition between pages results in the address
counter wrapping around to the beginning of the
present row.

For example, a 3-byte write starts at address 06h
and writes 3 data bytes (11h, 22h, and 33h) to three
“consecutive” addresses. The result is that address­es 06h and 07h would contain 11h and 22h, respec­tively, and the third data byte, 33h, would be written
to address 00h.

To prevent address wrapping from occurring, the
master must send a STOP condition at the end of
the page, then wait for the bus-free or EEPROM
write time to elapse. Then the master can generate a
new START condition and write the slave address
byte (R/W = 0) and the first memory address of the
next memory row before continuing to write data.

Acknowledge polling: Any time a EEPROM page is
written, the DS1874 requires the EEPROM write time
(t

W

) after the STOP condition to write the contents of
the page to EEPROM. During the EEPROM write
time, the DS1874 will not acknowledge its slave
address because it is busy. It is possible to take
advantage of that phenomenon by repeatedly
addressing the DS1874, which allows the next page
to be written as soon as the DS1874 is ready to
receive the data. The alternative to acknowledge
polling is to wait for maximum period of tWto elapse
before attempting to write again to the DS1874.

EEPROM write cycles: When EEPROM writes occur,
the DS1874 writes the whole EEPROM memory page,
even if only a single byte on the page was modified.
Writes that do not modify all 8 bytes on the page are
allowed and do not corrupt the remaining bytes of
memory on the same page. Because the whole page
is written, bytes on the page that were not modified
during the transaction are still subject to a write

DS1874

______________________________________________________________________________________ 27

SFP+ Controller with Digital LDD Interface