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817
DS1868
Dual Digital Potentiometer Chip
FEATURES
Ultra-lowpower consumption, quiet, pumpless
design
Two digitally controlled, 256-position
potentiometers
Serial port provides means for setting and
reading both potentiometers
Resistors can be connected in series to
provide increased total resistance
20-pin TSSOP, 16-pin SOIC, and 14-pin DIP
packages are available.
Resistive elements are temperature
compensated to ±0.3 LSB relative linearity
Standard resistance values:
- DS1868-10 ∼10 kΩ
- DS1868-50 ∼50 kΩ
- DS1868-100 ∼100 kΩ
+5V or ±3V operation
Operating Temperature Range:
- Industrial: -40°C to 85°C
PIN ASSIGNMENT
V
B
DNC
H1
L1
W1
RST
CLK
DNC
DNC
GND
20-Pin TSSOP (173-mil)
V
NC
H1
L1
W1
RST
CLK
GND
DS1868S 16-Pin SOIC (300-mil)
1
B
16
2
15
3
14
4
13
5
12
6
11
7
10
8
V
DNC
DNC
S
W0
H0
L0
C
DNC
DQ
V
NC
S
W0
H0
L0
C
DQ
9
CC
OUT
OUT
CC
OUT
OUT
V
B
H1
L1
W1
RST
CLK
GND
14-Pin DIP (300-mil)
14
V
S
W0
H0
L0
C
DQ
CC
OUT
OUT
PIN DESCRIPTION
L0, L1 - Low End of Resistor
H0, H1 - High End of Resistor
W0, W1 - Wiper Terminal of Resistor
S
OUT
RST - Serial Port Reset Input
- Stacked Configuration Output
DQ - Serial Port Data Input
CLK - Serial Port Clock Input
C
V
OUT
CC
- Cascade Port Output
- +5 Volt Supply
GND - Ground Connections
NC - No Internal Connection
V
B
- Substrate Bias Voltage
DNC - Do Not Connect
*All GND pins must be connected to ground.
DESCRIPTION
The DS1868 Dual Digital Potentiometer Chip consists of two digitally controlled solid-state
potentiometers. Each potentiometer is composed of 256 resistive sections. Between each resistive section
and both ends of the potentiometer are tap points which are accessible to the wiper. The position of the
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DS1868
wiper on the resistor array is set by an 8-bit value that controls which tap point is connected to the wiper
output. Communication and control of the device is accomplished via a 3-wire serial port interface. This
interface allows the device wiper position to be read or written.
Both potentiometers can be connected in series (or stacked) for an increased total resistance with the same
resolution. For multiple-device, single-processor environments, the DS1868 can be cascaded or daisy
chained. This feature provides for control of multiple devices over a single 3-wire bus.
The DS1868 is offered in three standard resistance values which include 10, 50, and 100 kohm versions.
The part is available in 16-pin SOIC (300-mil), 14-pin DIP, and 20-pin (173-mil) TSSOP packages.
OPERATION
The DS1868 contains two 256-position potentiometers whose wiper positions are set by an 8-bit value.
These two 8-bit values are written to a 17-bit I/O shift register which is used to store the two wiper
positions and the stack select bit when the device is powered. A block diagram of the DS1868 is
presented in Figure 1.
Communication and control of the DS1868 is accomplished through a 3-wire serial port interface that
drives an internal control logic unit. The 3-wire serial interface consists of the three input signals: RST ,
CLK, and DQ.
The RST control signal is used to enable the 3-wire serial port operation of the device. The RST signal is
an active high input and is required to begin any communication to the DS1868. The CLK signal input is
used to provide timing synchronization for data input and output. The DQ signal line is used to transmit
potentiometer wiper settings and the stack select bit configuration to the 17-bit I/O shift register of the
DS1868.
Figure 9(a) presents the 3-wire serial port protocol. As shown, the 3-wire port is inactive when the RST
signal input is low. Communication with the DS1868 requires the transition of the RST input from a low
state to a high state. Once the 3-wire port has been activated, data is entered into the part on the low to
high transition of the CLK signal inputs. Three-wire serial timing requirements are provided in the timing
diagrams of Figure 9(b),(c).
Data written to the DS1868 over the 3-wire serial interface is stored in the 17-bit I/O shift register (see
Figure 2). The 17-bit I/O shift register contains both 8-bit potentiometer wiper position values and the
stack select bit. The composition of the I/O shift register is presented in Figure 2. Bit 0 of the I/O shift
register contains the stack select bit. This bit will be discussed in the section entitled Stacked
Configuration. Bits 1 through 8 of the I/O shift register contain the potentiometer-1 wiper position value.
Bit 1 will contain the MSB of the wiper setting for potentiometer-1 and bit 8 the LSB for the wiper
setting. Bits 9 through 16 of the I/O shift register contain the value of the potentiometer-0 wiper position
with the MSB for the wiper position occupying bit 9 and the LSB bit 16.
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DS1868 BLOCK DIAGRAM Figure 1
I/O SHIFT REGISTER Figure 2
DS1868
Transmission of data always begins with the stack select bit followed by the potentiometer-1 wiper
position value and lastly the potentiometer-0 wiper position value.
When wiper position data is to be written to the DS1868, 17 bits (or some integer multiple) of data should
always be transmitted. Transactions which do not send a complete 17 bits (or multiple) will leave the
register incomplete and possibly an error in the desired wiper positions.
After a communication transaction has been completed the RST signal input should be taken to a low
state to prevent any inadvertent changes to the device shift register. Once RST has reached a low state,
the contents of the I/O shift register are loaded into the respective multiplexers for setting wiper position.
A new wiper position will only engage after a RST transition to the inactive state. On device power-up,
wiper position will be random.
STACKED CONFIGURATION
The potentiometers of the DS1868 can be connected in series as shown in Figure 3. This is referred to as
the stacked configuration and allows the user to double the total end-to-end resistance of the part. The
resolution of the combined potentiometers will remain the same as a single potentiometer but with a total
of 512 wiper positions available. Device resolution is defined as R
R
equals the total potentiometer resistance.
TOT
The wiper output for the combined stacked potentiometer will be taken at the S
multiplexed output of the wiper of potentiometer-0 (W0) or potentiometer-1 (W1). The potentiometer
wiper selected at the S
output is governed by the setting of the stack select bit (bit 0) of the 17-bit I/O
OUT
shift register. If the stack select bit has value 0, the multiplexed output, S
/256 (per potentiometer); where
TOT
pin, which is the
OUT
, will be that of the
OUT
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potentiometer-0 wiper. If the stack select bit has value 1, the multiplexed output, S
potentiometer-1 wiper.
, will be that of the
OUT
DS1868
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DS1868
STACKED CONFIGURATION Figure 3
CASCADE OPERATION
A feature of the DS1868 is the ability to control multiple devices from a single processor. Multiple
DS1868s can be linked or daisy chained as shown in Figure 4. As a data bit is entered into the I/O shift
register of the DS1868 a bit will appear at the C
stack select bit of the DS1868 will always be the first out the part at the beginning of a transaction. The
C
pin will always have the value of the stack select bit (b0) when RST is inactive.
OUT
output after a minimum delay of 50 nanoseconds. The
OUT
CASCADING MULTIPLE DEVICES Figure 4
The C
multiple devices, the total number of bits transmitted is always 17 times the number of DS1868s in the
daisy chain.
An optional feedback resistor can be placed between the C
DS1868 DQ, input thus allowing the controlling processor to read, as well as, write data, or circularly
clock data through the daisy chain. The value of the feedback or isolation resistor should be in the range
from 2 to 10 kohms.
When reading data via the C
device. When RST is driven high, bit 17 is present on the C
pin through the isolation resistor. When the CLK input transitions low to high, bit 17 is loaded into the
first position of the I/O shift register and bit 16 becomes present on C
17 bits (or 17 times the number of DS1868s in the daisy chain), the data has shifted completely around
and back to its original position. When RST transitions to the low state to end data transfer, the value (the
same as before the read occurred) is loaded into the wiper-0, wiper-1, and stack select bit I/O register.
output of the DS1868 can be used to drive the DQ input of another DS1868. When connecting
OUT
terminal of the last device and the first
OUT
pin and isolation resistor, the DQ line is left floating by the reading
OUT
pin, which is fed back to the input DQ
OUT
and DQ of the next device. After
OUT
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DS1868
ABSOLUTE AND RELATIVE LINEARITY
Absolute linearity is defined as the difference between the actual measured output voltage and the
expected output voltage. Figure 5 presents the test circuit used to measure absolute linearity. Absolute
linearity is given in terms of a minimum increment or expected output when the wiper is moved one
position. In the case of the test circuit, a minimum increment (MI) or one LSB would equal 5/256 volts.
The equation for absolute linearity is given as follows:
(1) ABSOLUTE LINEARITY
AL={VO(actual) - VO(expected)}/MI
Relative linearity is a measure of error between two adjacent wiper position points and is given in terms
of MI by equation (2).
(2) RELATIVE LINEARITY
RL={VO(n+1) - VO(n)}/MI
Figure 6 is a plot of absolute linearity and relative linearity versus wiper position for the DS1868 at 25°C.
The specification for absolute linearity of the DS1868 is ±0.75 MI typical. The specification for relative
linearity of the DS1868 is ±0.3 MI typical.
LINEARITY MEASUREMENT CONFIGURATION Figure 5
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DS1868 ABSOLUTE AND RELATIVE LINEARITY Figure 6
DS1868
TYPICAL APPLICATION CONFIGURATIONS
Figures 7 and 8 show two typical application configurations for the DS1868. By connecting the wiper
terminal of the part to a high impedance load, the effects of the wiper resistance is minimized, since the
wiper resistance can vary from 400 to 1000 ohms, depending on wiper voltage. Figure 7 presents the
device connected in a variable gain amplifier. The gain of the circuit on Figure 7 is given by the following
equation:
AV =
Figure 8 shows the device operating in a fixed gain attenuator where the potentiometer is used to
attenuate an incoming signal. Note the resistance R1 is chosen to be much greater than the wiper
resistance to minimize its effect on circuit gain.
256+
where n = 0 to 255
n-256
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VARIABLE GAIN AMPLIFIER Figure 7
FIXED GAIN ATTENUATOR Figure 8
DS1868
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DS1868
ABSOLUTE MAXIMUM RATINGS*
Voltage on Any Pin Relative to Ground (VB=GND) -1.0V to +7.0V
Voltage on Any Pin when VB=-3.3V -3.3V to +4.7V
Operating Temperature -40°C to +85°C
Storage Temperature -55°C to +125°C
Soldering Temperature 260°C for 10 seconds
* This is a stress rating only and functional operation of the device at these or any other conditions
above those indicated in the operation sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods of time may affect reliability.
RECOMMENDED DC
OPERATING CONDITIONS (-40°C to +85°C; V
=5.0V ± 10%)
CC
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Supply Voltage V
Input Logic 1 V
Input Logic 0 V
CC
IH
IL
4.5
2.7
5.5
3.3
V1
15
2.0 VCC+0.5 V 1, 2
-0.5 +0.8 V 1, 2
Ground GND GND GND V 1
Resistor Inputs L, H, W VB-0.5 VCC+0.5 V 2, 15
Substrate Bias V
B
-3.3 GND V 1, 15
DC ELECTRICAL CHARACTERISTICS (-40°C to +85°C; VCC=5.0V ± 10%)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Supply Current I
Input Leakage I
Wiper Resistance R
Wiper Current I
Logic 1 Output @ 2.4 Volts I
Logic 0 Output @ 0.4 Volts I
Standby Current I
STBY
CC
LI
W
OH
OL
-1 +1
W
400 1000
-1 mA 8, 9
400
µA
µA
Ω
1mA
4 mA 8, 9
1
µA
12
14
ANALOG RESISTOR CHARACTERISTICS (-40°C to +85°C; VCC=5.0V ± 10%)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
End-to-End Resistor Tolerance -20 +20 % 16
Absolute Linearity
Relative Linearity
-3 dB Cutoff Frequency F
CUTOFF
±0.75
±0.3
Noise Figure 11
Temperature Coefficient 750 ppm/C
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LSB 4
LSB 5
Hz 7
DS1868
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DS1868
CAPACITANCE (tA=25°C)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Input Capacitance C
Output Capacitance C
IN
OUT
5 pF 3, 6
7 pF 3, 6
AC ELECTRICAL CHARACTERISTICS (-40°C to +85°C; VCC=5.0V ± 10%)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
CLK Frequency f
Width of CLK Pulse t
Data Setup Time t
Data Hold Time t
Propagation Delay Time Low to High Level
Clock to Output
Propagation Delay Time High to Low Level t
RST High to Clock Input High
RST Low from Clock Input High
RST Inactive
Clock Low to Data Valid on a Read t
CLK Rise Time, CLK Fall Time t
CLK
CH
DC
CDH
t
PLH
PLH
t
CC
t
HLT
t
RLT
CDD
CR
DC 10 MHz 10
50 ns 10
30 ns 10
10 ns 10
50 ns 10, 13
50 ns 10, 13
50 ns 10
50 ns 10
125 ns 10
30 ns 10
50 ns 10
NOTES:
1. All voltages are referenced to ground.
2. Resistor inputs cannot exceed VB - 0.5V in the negative direction.
3. Capacitance values apply at 25°C.
4. Absolute linearity is used to determine wiper voltage versus expected voltage as determined by wiper
position. Device test limits ±1.6 LSB.
5. Relative linearity is used to determine the change in voltage between successive tap positions. Device
test limits ±0.5 LSB.
6. Typical values are for tA = 25°C and nominal supply voltage.
7. -3 dB cutoff frequency characteristics for the DS1868 depend on potentiometer total resistance:
DS1868-010; 1 MHz, DS1868-050; 200 kHz; and DS1868-100; 80 kHz.
8. Cout is active regardless of the state of RST .
9. V
10. See Figure 9(a), (b), and (c).
11. Noise < -120 dB/ Hz . Reference 1 volt (thermal).
12. Supply current is dependent on clock rate (see Figure 11).
13. See Figure 10.
14. Standby currents apply when RST , LLIC, DQ are in the low-state.
15. When biasing the substrate minimum VB = -3.0V ± 10% and maximum VCC = 3.0V ± 10%.
16. Valid at 25°C only.
= 1.5 volts.
REF
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TIMING DIAGRAMS Figure 9
(a) 3-Wire Serial Interface General Overview
(b) Start of Communication Transaction
DS1868
(c) End of Communication Transaction
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DIGITAL OUTPUT LOAD SCHEMATIC Figure 10
TYPICAL SUPPLY CURRENT VS. SERIAL CLOCK RATE Figure 11
DS1868
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DS1868 20-PIN TSSOP
DS1868
DIM MIN MAX
A MM
A1 MM
A2 MM
C MM
L MM
e1 MM
B MM
D MM
E MM
G MM
H MM
phi
-1.10
0.05 -
0.75 1.05
0.09 0.18
0.50 0.70
0.65 BSC
0.18 0.30
6.40 6.90
4.40 NOM
0.25 REF
6.25 6.55
0° 8°
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