Rainbow Electronics DS1846 User Manual
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DS1846
NV Tri-Potentiometer,
Memory and MicroMonito
FEATURES
Three linear taper potentiometers
− Two 10 kΩ, 100 position
− One 100 kΩ, 256 position
256 bytes of EEPROM memory
Monitors microprocessor power supply,
voltage sense, and external override
Access to data and potentiometer control via
a 2-wire interface
External Write Protect pin to protect data and
potentiometer settings
Nonvolatile wiper storage
Operates from 3V or 5V supplies
Packaging: 20-pin TSSOP
Industrial operating temperature:
-40ºC to +85ºC
Programming temperature: 0ºC to +70ºC
PIN ASSIGNMENT
SDA
SCL
A0
WP
NMI
L0
W1
L1
L2
GND
20-
in TSSOP
V
CC
IN
PBRST
RST
RST
H0
W0
H1
W2
H2
PIN DESCRIPTION
VCC - 3V or 5V Power Supply Input
GND - Ground
SDA - 2-wire Serial Data
Input/Output
SCL - 2-wire Serial Clock Input
WP - Write Protect Input
A0 - Address Input
H0, H1, H2 - High-End of Potentiometer
L 0, L1, L2 - Low-End of Potentiometer
W0, W1, W2 - Wiper Terminal of
Potentiometer
PBRST - Push Button Reset Button
NMI - Non-maskable Interrupt
IN - Voltage Input
RST - Active Low Reset Output
RST - Active High Reset Output
OVERVIEW
The DS1846 NV Tri-Potentiometer, Memory and MicroMonitor consists of two 10 kΩ,=100-position
linear taper potentiometer, one 100 kΩ,=256-position linear taper potentiometer, 256 bytes of EEPROM
memory, and a MicroMonitor. The device provides an ideal method for setting bias voltages and currents
in control applications using a minimum of circuitry.
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The EEPROM memory allows a user to store configuration or calibration data for a specific system or
device as well as provide control of the potentiometer wiper settings. Any type of user information may
reside in the first 248 bytes of this memory. The next three bytes of memory are for potentiometer
settings and the top five addresses of EEPROM memory are reserved. These reserved and potentiometer
registers should not be used for data storage. Access to this EEPROM is via an industry stand ard 2-wire
bus. The interface I/O pins consist of SDA and SCL. The wiper positions of the DS1846, as w ell as
EEPROM data, can be hardware write-protected using the Write Protect (WP) input pin.
The MicroMonitor is a precision temperature-compensated reference and comparator that monitors
certain vital status conditions for a microprocessor. When a sense input detects an out-of-tolerance Vcc
condition, a non-maskable interrupt is generated. As the voltage at the device degrades, an internal power
fail signal is generated that can be used to res et the proc essor. When Vc c returns t o an in-tol erance lev el,
the reset signal is kept in the active state for a minimum of 130 ms to allow for the stabilization of the
power supply and the microprocessor. The MicroMonitor also functions as a pushbutton r eset control.
The pushbutton input is debounced internally and is generated with an active pulse width of 130 ms
minimum.
Additionally, the DS1846 will operate from 3 volt or 5 volt supplies. One package option is available:
20-pin TSSOP.
DS1846 BLOCK DIAGRAM Figure 1
248 BYTES
VCC
GND
SDA
SCL
WP
A0
PBRST
NMI
IN
RST
2-WIRE
INTERFACE
CONTROL
DATA
EEPROM
MEMORY
5 RESERVED
BYTES
1 BYTE WIPER
SETTING
POT 0
1 BYTE WIPER
SETTING
POT 1
1 BYTE WIPER
SETTING
POT 2
POTENTIOMETER 0
H0
W0
L0
POTENTIOMETER 1
H1
W1
L1
POTENTIOMETER 2
RST
MICROMONITOR
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H2
W2
L2
DS1846
PIN DESCRIPTIONS
VCC - Power Supply Terminal. The DS1846 will support supply voltages ranging from +2.7 to
+5.5 volts.
GND - Ground Terminal.
SDA - 2-wire serial dat a interface. The serial data pin is for se rial data transfe r to and from the DS1846.
The pin is open drain and may be wire-ORed with other open drain or open collector interfaces.
SCL - 2-wire serial clock interface. The serial clock input is used to clock data into the DS1846 on rising
edges and clock data out on falling edges.
WP - Write Protect. Write Protect must be connected to GND before either the data in memory or
potentiometer wiper settings may be changed. Write Protect is pulled high internally and must be either
left open or connected to Vcc if write protection is desired.
A0 - Address Input. This input pin specifies the address of the device when used in a multi-dropped
configuration. Up to two individual DS1846s may be addressed on a single 2-wire bus.
H0, H1, H2 – These are the high-end terminals of the potentiometers. For the three potentiometers, it is
not required that these terminals be connected to a potential greater than the low-end terminal of the
potentiometer. Voltage applied to the high end of the potentiometers cannot exceed the power supply
voltage, VCC, or go below ground.
L0, L1, L2 – These are the low-end terminals of the potentiometers. It is not required that these
terminals be connected to a potential less than the high-end terminals of the pot. Voltage applied to the
low end of the potentiometers cannot exceed the power-supply voltage, VCC, or go below ground.
W0, W1, W2 - Wiper of the potentiometer. This pin is the wiper terminal of the potentiometer. Three
bytes in EEPROM memory locations F8h, F9h and FAh determine each wiper’s setting. Voltage applied
to either wiper terminal cannot exceed the power-supply voltage, VCC, or go below ground.
PBRST
– Push button reset. This input pin is active low. It acts as the push button reset pin for the
MicroMonitor.
NMI – Non-maskable interrupt. Active low signal that is generated in order to provide for an early power
fail warning.
IN – NMI voltage input.
RST - Active Low Reset Output. This signal provides an output that can be used to reset a
microprocessor.
RST - Active High Reset Output. This signal provides an output that can be used to reset a
microprocessor.
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MEMORY ORGANIZATION
The DS1846’s serial EEPROM is internally organized with 32 pages. Each page contains 8 bytes. Each
byte requires an 8-bit address for random byte addressing. The address bytes, starting at F8h, contain the
wiper setting for the three potentiometers. The byte at address F8h determines the wiper setting for
potentiometer 1, which contains 256 positions. The byte at address F9h determines the wiper setting for
potentiometer 0, which contains 100 positions (00h to 63h). The byte at address FAh determines the
wiper setting for potentiometer 2, which contains 100 positions (00h to 63h). If a value greater than 63h
is written to either address F9h or FAh, the wiper is set according to the value in the seven least
significant bits and the MSB is ignored. Address locations FBh though FFh are reserved and should not
be written.
DEVICE OPERATION
Clock and Data Transitions: The SDA pin is normally pulled high with an external resistor or device.
Data on the SDA pin may only change during SCL low time periods. Data changes during SCL high
periods will indicate a start or stop conditions depending on the conditions discussed below. Refer to the
timing diagram Fig 2 for further details.
Start Condition: A high-to-low transition of SDA with SCL high is a start condition which must
precede any other command. Refer to the timing diagram Fig 2 for further details.
Stop Condition: A low-to-high transition of SDA with SCL high is a stop condition. After a read
sequence, the stop command places the DS1846 into a low-power mode. Ref er to the timing diagram
Figure 2 for further details.
Acknowledge: All address and data bytes are transmitted via a serial protocol. The DS1846 pulls the
SDA line low during the ninth clock pulse to acknowledge that it has received each word.
Standby Mode: The DS1846 features a low-power mode that is automatically enabled after power-on,
after a stop command, and after the completion of all internal operations.
Memory Reset: After any interruption in protocol, power loss, or system reset, the following steps reset
the DS1846.
1. Clock up to nine cycles.
2. Look for SDA high in each cycle while SCL is high.
3. Create a start condition while SDA is high.
Device Addressing: The DS1846 must receive an 8-bit device address word following a start condition
to enable a specific device for a read or write operation. The address word is clocked into the DS1846
MSB to LSB. The address word consists of 101000 binary followed by A0 then the R/W
(READ/WRITE) bit. If the R/W bit is high, a read operation is initiated. The R/W is low, a write
operation is initiated. For a device to become active, the value of A0 must be the same as the hard-wired
address pins on the DS1846. Upon a match of written and hard-wired addresses, the DS1846 will output
a zero for one clock cycle as an acknowledge. If the address does not match the DS1846 returns to a
low-power mode.
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Write Operations: After recei ving a matching devic e address byte with the R/W bit set low, the device
goes into the write mode of operation. The master must transmit an 8-bit EEPROM memory address to
the device to define the address where the data is to be written. After the reception of this byte, the
DS1846 will transmit a zero for one clock cycle to acknowledge the receipt of the memor y address. The
master must then transmit an 8-bit data word to be written into this memory address. The DS1846 will
again transmit a zero for one clock cycle to acknowledge the receipt of the data b yte. At this point the
master must terminate the write operation with a stop condition. The DS1846 then enters an internally
timed write process Tw to the EEPROM memory. All inputs other than those controlling the
MicroMonitor are disabled during this write cycle.
The DS1846 is capable of an 8-byte page write. A page write is initiated the same wa y as a byte write,
but the master does not send a stop condition after the first data byte. Instead, after the slave
acknowledges receipt of the data byte, the master can send up to seven more data b ytes using the same
nine-clock sequence. After a write to the last byte in the page, the address returns to the beginning of the
page. The master must terminate the write cycle with a stop condition or the data clocked into the
DS1846 will not be latched into permanent memory.
Acknowledge Polling: Once the internally-timed write has started and the DS1846 inputs are disabled,
acknowledge polling can be initiated. The process involves transmitting a start condition followed by the
device address. The R/W bit signifies the type of operation that is desired. The read or write sequence
will only be allowed to proceed if the internal write cycle has completed and the DS1846 responds with a
zero.
Read Operations: After receiving a matching address byte with the R/W bit set high, the device goes
into the read mode of operation. There are three read operations: current address read, random read and
sequential address read.
CURRENT ADDRESS READ
The DS1846 has an internal address register that maintains the address used during the last read or write
operation, incremented by one. This data is maintained as long as VCC is valid. If the most recent
address was the last byte in memory, then the register resets to the first address. This address stays valid
between operations as long as power is available.
Once the device address is clocked in and acknowledged by the DS1846 with the R/W bit set to high, the
current address data word is clocked out. The master does not respond with a zero, but does generate a
stop condition afterwards.
RANDOM READ
A random read requires a dummy byte write sequence to load in the data word address. Once the device
address and data bytes are clocked in by the master, and acknowledged by the DS1846, the master must
generate another start condition. The master now initiates a current address read b y sending the device
address with the read/write bit set high. The DS1846 will ackno wledge the device address and serially
clocks out the data byte.
SEQUENTIAL ADDRESS READ
Sequential reads are initiated by either a current address read o r a random address read. After the master
receives the first data byte, the master responds with an acknowledge. As long as the DS1846 receives
this acknowledge after a byte is read, the master may clock out additional data words from the DS1846.
After reaching address FFh, it resets to address 00h.
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