Rainbow Electronics DS1747P User Manual

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A17A

A11A

A13A8A9A

DS1747/DS1747P

Y2KC Nonvolatile Timekeeping RAM

FEATURES

§ Integrated NV SRAM, real-time clock,

crystal, power-fail control circuit and lithium energy source

§ Clock registers are accessed identical to the

static RAM. These registers are resident in the eight top RAM locations.

§ Century byte register (Y2K compliant)

§ Totally nonvolatile with over 10 years of

operation in the absence of power

§ BCD coded century, year, month, date, day,

hours, minutes, and seconds with automatic leap year compensation valid up to the year 2100

§ Battery voltage level indicator flag

§ Power-fail write protection allows for ±10%

power supply tolerance

§ Lithium energy source is electrically

disconnected to retain freshness until power is applied for the first time

§ DIP Module only

- Standard JEDEC bytewide 512k x 8 static RAM pinout

§ PowerCapÒ Module Board only

- Surface mountable package for direct connection to PowerCap containing battery and crystal

- Replaceable battery (PowerCap)

- Power-On Reset Output

- Pin for pin compatible with other densities of DS174XP Timekeeping RAM

PIN ASSIGNMENT

NC A15 A16

RST

DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0

GND

A18

A16 A14 A12

DQ0

DQ1 DQ2

GND

3 4 5

6 7 8 9 10 11 12 13 14 15 16 17

34-Pin PowerCap Module Board

(Uses DS9034PCX PowerCap)

2 3 4

5 6

A6 A5

11 12

32-Pin Encapsulated Package

X1 GND

512k X 8

BAT

32 31

30 29

28 27

26 25

24 23

22 21

34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18

15 17

DQ7

DQ6

DQ5

DQ4

DQ3

14 13 12

10 9 8 7 6 5 4 3 2 1 0

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PIN DESCRIPTION

A0–A18 – Address Input

CE – Chip Enable

OE – Output Enable

WE – Write Enable

– Power Supply Input GND – Ground DQ0–DQ7 – Data Input/Output NC – No Connection

RST – Power–on Reset Output(Power– Cap Module board only) X1, X2 – Crystal Connection V

BAT – Battery Connection

ORDERING INFORMATION

DS1747P (5V)

blank 32-pin DIP Module P 34-pin PowerCap Module board*

DS1747/DS1747P

DS1747WP (3.3V)

blank 32-pin DIP Module P 34-pin PowerCap Module board*

*DS9034PCX (PowerCap) Required:

(must be ordered separately)

DESCRIPTION

The DS1747 is a full function, year 2000 compliant (Y2KC), real–time clock/calendar (RTC) and 512k x 8 non–volatile static RAM. User access to all registers within the DS1747 is accomplished with a bytewide interface as shown in Figure 1. The Real-time clock (RTC) information and control bits reside in the eight upper most RAM locations. The RTC registers contain century, year, month, date, day, hours, minutes, and seconds data in 24-hour BCD format. Corrections for the date of each month and leap year are made automatically. The RTC clock registers are double buffered to avoid access of incorrect data that can occur during clock update cycles. The double buffered system also prevents time loss as the timekeeping countdown continues unabated by access to time register data. The DS1747 also contains its own power–fail circuitry which deselects the device when the V tolerance condition. This feature prevents loss of data from unpredictable system operation brought on by low V

as errant access and update cycles are avoided.

supply is in an out of

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DS1747/DS1747P

DS1747 BLOCK DIAGRAM Figure 1

PACKAGES

The DS1747 is available in two packages (32–pin DIP and 34–pin PowerCap module). The 32–pin DIP style module integrates the crystal, lithium energy source, and silicon all in one package. The 34–pin PowerCap Module Board is designed with contacts for connection to a separate PowerCap (DS9034PCX) that contains the crystal and battery. This design allows the Power-Cap to be mounted on top of the DS1747P after the completion of the surface mount process. Mounting the PowerCap after the surface mount process prevents damage to the crystal and battery due to the high temperatures required for solder reflow. The PowerCap is keyed to prevent reverse insertion. The PowerCap Module Board and PowerCap are ordered separately and shipped in separate containers. The part number for the PowerCap is DS9034PCX.

CLOCK OPERATIONS-READING THE CLOCK

While the double buffered register structure reduces the chance of reading incorrect data, internal updates to the DS1747 clock registers should be halted before clock data is read to prevent reading of data in transition. However, halting the internal clock register updating process does not affect clock accuracy. Updating is halted when a one is written into the read bit, bit 6 of the century register, see Table 2. As long as a one remains in that position, updating is halted. After a halt is issued, the registers reflect the count, that is day, date, and time that was current at the moment the halt command was issued. However, the internal clock registers of the double buffered system continue to update so that the clock accuracy is not affected by the access of data. All of the DS1747 registers are updated simultaneously after the internal clock register updating process has been re–enabled. Updating is within a second after the read bit is written to zero. The READ bit must be set to a zero for a minimum of 500

ms to ensure the external registers will be updated.

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DS1747 TRUTH TABLE Table 1

DS1747/DS1747P

VCC>V

VSO<VCC<V VCC<VSO<V

CE OE WE

V V V V

X X DESELECT HIGH-Z STANDBY XVILWRITE DATA IN ACTIVE V V

V V

X X X DESELECT HIGH-Z CMOS STANDBY X X X DESELECT HIGH-Z DATA

MODE DQ POWER

READ DATA OUT ACTIVE READ HIGH-Z ACTIVE

RETENTION MODE

SETTING THE CLOCK

As shown in Table 2, bit 7 of the century register is the write bit. Setting the write bit to a one, like the read bit, halts updates to the DS1747 registers. The user can then load them with the correct day, date and time data in 24 hour BCD format. Resetting the write bit to a zero then transfers those values to the actual clock counters and allows normal operation to resume.

STOPPING AND STARTING THE CLOCK OSCILLATOR

The clock oscillator may be stopped at any time. To increase the shelf life, the oscillator can be turned

off to minimize current drain from the battery. The see Table 2. Setting it to a one stops the oscillator.

OSC bit is the MSB (bit 7) of the seconds registers,

FREQUENCY TEST BIT

As shown in Table 2, bit 6 of the day byte is the frequency test bit. When the frequency test bit is set to logic “1” and the oscillator is running, the LSB of the seconds register will toggle at 512 Hz. When the seconds register is being read, the DQ0 line will toggle at the 512 Hz frequency as long as conditions for

access remain valid (i.e.,

CE low, OE low, WE high, and address for seconds register remain valid

and stable).

CLOCK ACCURACY (DIP MODULE)

The DS1747 is guaranteed to keep time accuracy to within ±1 minute per month at 25°C. The RTC is calibrated at the factory by Dallas Semiconductor using nonvolatile tuning elements, and does not require additional calibration. For this reason, methods of field clock calibration are not available and not necessary. Clock accuracy is also effected by the electrical environment and caution should be taken to place the RTC in the lowest level EMI section of the PCB layout. For additional information please see application note 58.

CLOCK ACCURACY (POWERCAP MODULE)

The DS1747 and DS9034PCX are each individually tested for accuracy. Once mounted together, the module will typically keep time accuracy to within accuracy is also effected by the electrical environment and caution should be taken to place the RTC in the lowest level EMI section of the PCB layout. For additional information please see application note

58.

±1.53 minutes per month (35 ppm) at 25°C. Clock

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DS1747/DS1747P

DS1746 REGISTER MAP Table 2

ADDRESS

7FFFF 10 YEAR YEAR YEAR 00-99 7FFFE X X X 10 MO MONTH MONTH 01-12 7FFFD X X 10 DATE DATE DATE 01-31 7FFFC BF FT X X X DAY DAY 01-07 7FFFB X X 10 HOUR HOUR HOUR 00-23 7FFFA X 10 MINUTES MINUTES MINUTES 00-59

7FFF9 7FFF8 W R 10 CENTURY CENTURY CENTURY 00-39

OSC = STOP BIT R = READ BIT FT = FREQUENCY TEST W = WRITE BIT X = SEE NOTE BELOW BF = BATTERY FLAG

DATA B

7 B6

OSC

B5 B4 B

3 B2

B1 B

FUNCTION/RANGE

10 SECONDS SECONDS SECONDS 00-59

NOTE:

All indicated “X” bits are not dedicated to any particular function and can be used as normal RAM bits.

RETRIEVING DATA FROM RAM OR CLOCK

The DS1747 is in the read mode whenever OE (output enable) is low, WE (write enable) is high, and

CE (chip enable) is low. The device architecture allows ripple-through access to any of the address locations in the NV SRAM. Valid data will be available at the DQ pins within t

input is stable, providing that the

CE and OE access times and states are satisfied. If CE or OE access

times and states are not met, valid data will be available at the latter of chip enable access (t

output enable access time (t

OEA). The state of the data input/output pins (DQ) is controlled by CE and

AA after the last address

CEA) or at

OE . If the outputs are activated before tAA, the data lines are driven to an intermediate state until tAA. If

the address inputs are changed while data hold time (t

OH) but will then go indeterminate until the next address access.

CE and OE remain valid, output data will remain valid for output

WRITING DATA TO RAM OR CLOCK

The DS1747 is in the write mode whenever WE , and CE are in their active state. The start of a write is

referenced to the latter occurring transition of

the cycle. write cycle. Data in must be valid t

typical application, the

CE or WE must return inactive for a minimum of tWR prior to the initiation of another read or

DS prior to the end of write and remain valid for tDH afterward. In a

OE signal will be high during a write cycle. However, OE can be active

provided that care is taken with the data bus to avoid bus contention. If transitioning low the data bus can become active with read data defined by the address inputs. A low

transition on

WE will then disable the output tWEZ after WE goes active.

WE or CE . The addresses must be held valid throughout

OE is low prior to WE

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DS1747/DS1747P

DATA RETENTION MODE

The 5-volt device is fully accessible and data can be written or read only when V However, when V

is below the power failing point, VPF, (point at which write protection occurs) the

internal clock registers and SRAM are blocked from any access. At this time the power fail reset output

is greater than V

signal ( below the battery switch point V

RST ) is driven active and will remain active until V

(battery supply level), device power is switched from the VCC pin to

the backup battery. RTC operation and SRAM data are maintained from the battery until V to nominal levels. The 3.3 volt device is fully accessible and data can be written or read only when V is greater than V

this time the power fail reset output signal ( returns to nominal levels. If V supply (V V

BAT) when VCC drops below VPF. If V

to the backup supply (V

maintained from the battery until V

output and requires a pull up. Except for the powered down when V

. When VCC falls below the power fail point, VPF, access to the device is inhibited. At

RST ) is driven active and will remain active until V

is less than V

) when VCC drops below Vso. RTC operation and SRAM data are

BAT

is returned to nominal levels. The RST signal is an open drain

, the device power is switched from VCC to the backup

is greater than Vso, the device power is switched from

RST , all control, data, and address signals must be

is powered down.

returns to nominal levels. When VCC falls

is returned

BATTERY LONGEVITY

The DS1747 has a lithium power source that is designed to provide energy for clock activity, and clock and RAM data retention when the V is sufficient to power the DS1747 continuously for the life of the equipment in which it is installed. For specification purposes, the life expectancy is 10 years at 25 in the absence of V

power. Each DS1747 is shipped from Dallas Semiconductor with its lithium

energy source disconnected, guaranteeing full energy capacity. When V greater than V

, the lithium energy source is enabled for battery backup operation. Actual life

expectancy of the DS1747 will be much longer than 10 years since no lithium battery energy is consumed when V

CC is present.

supply is not present. The capability of this internal power supply

°C with the internal clock oscillator running

CC is first applied at a level

BATTERY MONITOR

The DS1747 constantly monitors the battery voltage of the internal battery. The Battery Flag bit (bit 7) of the day register is used to indicate the voltage level range of the battery. This bit is not writable and should always be a one when read. If a zero is ever present, an exhausted lithium energy source is indicated and both the contents of the RTC and RAM are questionable.

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