Rainbow Electronics DS17287 User Manual

www.maxim-ic.com

DS17285/DS17287

3V/5V Real-Time Clock

FEATURES

Incorporates industry standard DS1287 PC clock plus enhanced features:

§ Y2K compliant

§ +3V or +5V operation

§ SMI recovery stack

§ 64-bit silicon serial number

§ Power-control circuitry supports system

power-on from date/time alarm or key closure

§ 32kHz output on power-up

§ Crystal select bit allows RTC to operate with

6pF or 12.5pF crystal

§ 114 bytes user NV RAM

§ Auxiliary battery input

§ 2kB additional NV RAM

§ RAM clear input

§ Century register

§ Date alarm register

§ Compatible with existing BIOS for original

DS1287 functions

§ Available as chip (DS17285) or standalone

module with embedded battery and crystal (DS17287)

§ Timekeeping algorithm includes leap-year

compensation valid up to 2100

§ Underwriters Laboratory (UL) recognized

PIN ASSIGNMENT

AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7

GND

3 4

5 6

7 8

9 10

11 12

DS17285 24-Pin DIP

DS17285S 24-Pin SO

NC AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7

GND

2 3 4

5 6

7 8

9 10

11 12

DS17287 24-Pin

Encapsulated Package

24 23

22 21

20 19

18 17

16 15

14 13

24 23

22 21

20 19

18 17

16 15

14 13

VCC SQW

VBAU

RCLR VBAT IRQ KS RD GND WR

VCC SQW VBAU

RCLR NC IRQ KS RD NC WR

TYPICAL OPERATING CIRCUIT

IRQ 1 28 KS VBAT 2 27 RD RCLR 3 26 GND VBAUX 4 25 WR SQW 5 24 ALE VCC 6 23 CS VCC 7 22 GND PWR 8 21 GND X1 9 20 AD7 X2 10 19 AD6 NC 11 18 NC ADO 12 17 AD5 AD1 13 16 AD4 AD2 14 15 AD3

DS17285E 28-Pin TSOP

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ORDERING INFORMATION

PART # DESCRIPTION

DS17285XX-X RTC Chip

3 +3V operating range 5 +5V operating range

blank commercial temp range

industrial temp range blank 24-pin DIP E 28- pin TSOP

S 24- pin SO

DS17287X-X RTC Module; 24-pin DIP

3 +3V operating rang

5 +5V operating range

blank commercial temp range

industrial

PIN DESCRIPTION

X1 - Crystal Input X2 - Crystal Output

RCLR - RAM Clear Input

AD0–AD7 - Multiplexed Address/Data Bus

PWR - Power-On Interrupt Output (Open Drain)

DS17285/DS17287

KS - Kickstart Input

CS - RTC Chip-Select Input

ALE - RTC Address Strobe

WR - RTC Write Data Strobe

RD - RTC Read Data Strobe

IRQ - Interrupt Request Output (Open Drain)

SQW - Square-Wave Output VCC - +3V or +5V Main Supply GND - Ground VBAT - Battery + Supply VBAUX - Auxiliary Battery Supply NC - No Connect

DESCRIPTION

The DS17285/DS17287 are real-time clocks (RTCs) designed as successors to the industry standard DS1285, DS1385, DS1485, DS1585, and DS1685 PC real-time clocks. These devices provide the industry standard DS1285 clock function with either +3V or +5V operation. The DS17285 also incorporates a number of enhanced features including a silicon serial number, power-on/off control circuitry, 114 bytes of user NV SRAM plus 2kB of additional NV RAM, and 32.768kHz output for sustaining power management activities.

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DS17285/DS17287

The DS17285/DS17287 power-control circuitry allows the system to be powered on by an external

stimulus such as a keyboard or by a time-and-date (wake-up) alarm. The PWR output pin is triggered by

one or either of these events, and is used to turn on an external power supply. The PWR pin is under software control, so that when a task is complete, the system power can then be shut down.

The DS17285 is a clock/calendar chip with the features described above. An external crystal and battery are the only components required to maintain time-of-day and memory status in the absence of power. The DS17287 incorporates the DS17285 chip, a 32.768kHz crystal, and a lithium battery in a complete, self-contained timekeeping module. The entire unit is fully tested at Dallas Semiconductor such that a minimum of 10 years of timekeeping and data retention in the absence of VCC is guaranteed.

OPERATION

The block diagram in Figure 1 shows the pin connections with the major internal functions of the DS17285/DS17287. The following paragraphs describe the function of each pin.

SIGNAL DESCRIPTIONS

GND, VCC – DC power is provided to the device on these pins. V

is the +3V or +5V input.

SQW – Square-Wave Output. The SQW pin provides a 32kHz square-wave output, t

, after a power-

REC

up condition has been detected. This condition sets the following bits, enabling the 32kHz output; DV1 = 1, and E32k = 1. A square wave is output on this pin if either SQWE = 1 or E32k = 1. If E32k = 1, then 32kHz is output regardless of the other control bits. If E32k = 0, then the output frequency is dependent on the control bits in register A. The SQW pin can output a signal from one of 13 taps provided by the 15 internal divider stages of the RTC. The frequency of the SQW pin can be changed by programming Register A, as shown in Table 2. The SQW signal can be turned on and off using the SQWE bit in register B or the E32k bit in extended register 4Bh. A 32kHz SQW signal is output when the enable 32kHz (E32k) bit in extended register 4Bh is a logic 1 and V

is above VPF. A 32kHz square

wave is also available when VCC is less than VPF if E32k = 1, ABE = 1, and voltage is applied to the V

BAUX

pin.

AD0 to AD7 – Multiplexed Bidirectional Address/Data Bus. Multiplexed buses save pins because address information time and data information time share the same signal paths. The addresses are present during the first portion of the bus cycle and the same pins and signal paths are used for data in the second portion of the cycle. Address/data multiplexing does not slow the access time of the DS17285 since the bus change from address to data occurs during the internal RAM access time. Addresses must be valid prior to the latter portion of ALE, at which time the DS17285/DS17287 latches the address.

Valid write data must be present and held stable during the latter portion of the WR pulse. In a read cycle

the DS17285/DS17287 outputs 8 bits of data during the latter portion of the

terminated and the bus returns to a high impedance state as

RD transitions high. The address/data bus

RD pulse. The read cycle is

also serves as a bidirectional data path for the external extended RAM.

ALE – RTC Address Strobe Input; Active High. A pulse on the address strobe pin serves to demultiplex the bus. The falling edge of ALE causes the RTC address to be latched within the DS17285/DS17287.

RD –RTC Read Input; Active Low. RD identifies the time period when the DS17285/DS17287 drives

the bus with RTC read data. The RD signal is an enable signal for the output buffers of the clock.

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DS17285/DS17287

WR – RTC Write Input; Active Low. The WR signal is an active low signal. The WR signal defines

the time period during which data is written to the addressed register.

CS – RTC Chip-Select Input; Active Low. The chip select signal must be asserted low during a bus

cycle for DS17285/DS17287 to be accessed. CS must be kept in the active state during RD and WR

timing. Bus cycles that take place with ALE asserted but without asserting CS latches addresses. However, no data transfer occurs.

IRQ – Interrupt Request Output; Open Drain, Active Low. The IRQ pin is an active low output of

the DS17285/DS17287 that can be tied to the interrupt input of a processor. The IRQ output remains low as long as the status bit causing the interrupt is present and the corresponding interrupt-enable bit is set.

To clear the IRQ pin, the application software must clear all enabled flag bits contributing to IRQ ’s active state.

When no interrupt conditions are present, the IRQ level is in the high-impedance state. Multiple

interrupting devices can be connected to an IRQ bus. The IRQ pin is an open-drain output and requires an external pullup resistor. The voltage on the pullup supply should be no greater than VCC + 0.2V.

PWR – Power-On Output; Open-Drain, Active Low. The PWR pin is intended for use as an on/off

control for the system power. With VCC voltage removed from the DS17285/DS17287, PWR can be

automatically activated from a kickstart input by the KS pin or from a wake-up interrupt. Once the

system is powered on, the state of PWR can be controlled by bits in the Dallas registers. The PWR pin can be connected through a pullup resistor to a positive supply. For 5V operation, the voltage of the pullup supply should be no greater than 5.7V. For 3V operation, the voltage on the pullup supply should be no greater than 3.9V.

KS – Kickstart Input; Active Low. When V

is removed from the DS17285/DS17287, the system can

be powered on in response to an active low transition on the KS pin, as might be generated from a key closure. V

function is used, and the

must be present and auxiliary-battery-enable bit (ABE) must be set to 1 if the kickstart

BAUX

KS pin must be pulled up to the V

supply. While VCC is applied, the KS pin

BAUX

can be used as an interrupt input.

RCLR – RAM Clear Input; Active Low. If enabled by software, taking RCLR low results in the

clearing of the 114 bytes of user RAM. When enabled,

RCLR can be activated whether or not V

present. RCLR has an internal pullup and should not be connected to an external pullup resistor.

clock/calendar and user RAM if V other energy source can be used. For 3V operation, V 5V operation, V

– Auxiliary battery input required for kickstart and wake-up features. This input also supports

BAUX

is at lower voltage or is not present. A standard +3V lithium cell or

BAT

must be held between +2.5V and +3.7V. For

BAUX

must be held between +2.5V and +5.2V. If V

BAUX

is not going to be used it should

BAUX

be grounded and the auxiliary-battery-enable bit bank 1, register 4BH, should = 0.

UL recognized to ensure against reverse charging current when used with a lithium battery. See “Conditions of Acceptability” at www.maxim-ic.com/TechSupport/QA/ntrl.htm.

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Figure 1. BLOCK DIAGRAM

DS17285/DS17287

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DS17285/DS17287

DS17285 ONLY

X1, X2 – Connections for a standard 32.768kHz quartz crystal. For greatest accuracy, the DS17285 must be used with a crystal that has a specified load capacitance of either 6pF or 12.5pF. The crystal select (CS) bit in extended-control register 4B is used to select operation with a 6pF or 12.5pF crystal. The crystal is attached directly to the X1 and X2 pins. There is no need for external capacitors or resistors. Note: X1 and X2 are very high-impedance nodes. It is recommended that they and the crystal be guardringed with ground and that high frequency signals be kept away from the crystal area.

For more information about crystal selection and crystal layout considerations, refer to Application Note 58, “Crystal Considerations with Dallas Real-Time Clocks.” The DS17285 can also be driven by an external 32.768kHz oscillator. In this configuration, the X1 pin is connected to the external oscillator signal and the X2 pin is floated.

– Battery input for any standard 3V lithium cell or other energy source. Battery voltage must be

BAT

held between 2.5V and 3.7V for proper operation. UL recognized to ensure against reverse charging current when used in conjunction with a lithium battery. See “Conditions of Acceptability” at

www.maxim-ic.com/TechSupport/AQ/ntrl.htm.

POWER-DOWN/POWER-UP CONSIDERATIONS

The RTC function continues to operate and all of the RAM, time, calendar, and alarm memory locations remain nonvolatile regardless of the level of the VCC input. When VCC is applied to the DS17285/DS17287 and reaches a level of greater than VPF (power-fail trip point), the device becomes accessible after t reset (Register A). This time period allows the system to stabilize after power is applied.

, provided that the oscillator is running and the oscillator countdown chain is not in

REC

The DS17285/DS17287 is available in either a 3V or a 5V device.

The 5V device is fully accessible and data can be written and read only when VCC is greater than 4.5V. When VCC is below 4.5V, read and writes are inhibited. However, the timekeeping function continues unaffected by the lower input voltage. As VCC falls below the greater of V timekeeper are switched over to a lithium battery connected either to the V

The 3V device is fully accessible and data can be written or read only when V When V power supply is switched from V below V supply when VCC drops below the larger of V

When V

RCLR , and SQW pins, all inputs are ignored and all outputs are in a high-impedance state.

falls below VPF, access to the device is inhibited. If VPF is less than V

to the backup supply (the greater of

. If VPF is greater than V

falls below VPF, the chip is write-protected. With the possible exception of the KS , PWR ,

BAT

and V

, the power supply is switched from VCC to the backup

BAUX

BAT

and V

BAUX

VBAT

BAT

pin or V

BAT

and V

is greater than 2.7V.

BAUX

, the RAM and

BAUX

pin.

BAUX

and V

BAT

) when VCC drops

BAUX

, the

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DS17285/DS17287

RTC ADDRESS MAP

The address map for the RTC registers of the DS17285/DS17287 is shown in Figure 2. The address map consists of the 14 clock/calendar registers. Ten registers contain the time, calendar, and alarm data, and 4 bytes are used for control and status. All registers can be directly written or read except for the following:

1) Registers C and D are read-only.

2) Bit 7 of Register A is read-only.

3) The high order bit of the second byte is read-only.

Figure 2. DS17285 REAL-TIME CLOCK ADDRESS MAP

TIME, CALENDAR, AND ALARM LOCATIONS

The time and calendar information is obtained by reading the appropriate register bytes shown in Table 1. The time, calendar, and alarm are set or initialized by writing the appropriate register bytes. The contents of the time, calendar, and alarm registers can be either binary or binary-coded decimal (BCD) format. Table 1 shows the binary and BCD formats of the 10 time, calendar, and alarm locations that reside in both bank 0 and in bank 1, plus the two extended registers that reside in bank 1 only (bank 0 and bank 1 switching is explained later in this text).

Before writing the internal time, calendar, and alarm registers, the SET bit in Register B should be written to a logic 1 to prevent updates from occurring while access is being attempted. Also at this time, the data format (binary or BCD) should be set by the data mode bit (DM) of Register B. All time, calendar, and alarm registers must use the same data mode. The set bit in Register B should be cleared after the data mode bit has been written to allow the real-time clock to update the time and calendar bytes.

Once initialized, the real time clock makes all updates in the selected mode. The data mode cannot be changed without reinitializing the 10 data bytes. The 24/12 bit cannot be changed without reinitializing the hour locations. When the 12-hour format is selected, the high order bit of the hours byte represents PM when it is a logic 1. The time, calendar, and alarm bytes are always accessible because they are double-buffered. Once per second the 10 bytes are advanced by 1 second and checked for an alarm condition. If a read of the time and calendar data occurs during an update, a problem exists where seconds, minutes, hours, etc., may not correlate. The probability of reading incorrect time and calendar data is low. Several methods of avoiding any possible incorrect time and calendar reads are covered later in this text.

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DS17285/DS17287

The three time alarm bytes can be used in two ways. First, when the alarm time is written in the appropriate hours, minutes, and seconds alarm locations, the alarm interrupt is initiated at the specified time each day if the alarm enable bit is high. The second use condition is to insert a “don’t care” state in one or more of the three time alarm bytes. The “don’t care” code is any hexadecimal value from C0 to FF. The two most significant bits of each byte set the “don’t care” condition when at logic 1. An alarm is generated each hour when the “don’t care” bits are set in the hours byte. Similarly, an alarm is generated every minute with “don’t care” codes in the hours and minute alarm bytes. The “don’t care” codes in all three time alarm bytes create an interrupt every second. The three time-alarm bytes can be used with the date alarm as described in Wake-Up/Kickstart. The century counter is discussed later in this text.

Table 1. TIME, CALENDAR, AND ALARM DATA MODES

ADDRESS

LOCATION

OOH Seconds 0 to 59 00 to B 00 to 59

01H Seconds Alarm 0 to 59 00 to 3B 00 to 59 02H Minutes 0 to 59 00 to 3B 00 to 59

03H Minutes Alarm 0 to 59 00 to 3B 00 to 59

Hours 12-hour Mode 1 to 12 01 to 0C AM, 81 to 8C PM 01 to 12 AM, 81 to 92 PM

04H

Hours 24-hour Mode 0 to 23 00 to 17 00 to 23

Hours Alarm 12-hour Mode 1 to 12 01 to 0C AM, 81 to 8C PM 01 to 12 AM, 81 to 92 PM

05H

Hours Alarm 24-hour Mode 0 to 23 00 to 17 00 to 23

06H Days of the Week Sunday = 1 1 to 7 01 to 07 01 to 07 07H Date of Month 1 to 31 01 to 1F 01 to 31

08H Month 1 to 12 01 to 0C 01 to 12

09H Year 0 to 99 00 to 63 00 to 99

BANK 1, 48H Century 0 to 99 00 to 63 00 t o 99

BANK 1, 49H Date Alarm 1 to 31 01 to 1F 01 to 31

FUNCTION

DECIMAL

RANGE

BINARY DATA MODE BCD DATA MODE

RANGE

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DS17285/DS17287

CONTROL REGISTERS

The four control registers; A, B, C, and D reside in both bank 0 and bank 1. These registers are accessible at all times, even during the update cycle.

MSB LSB

BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

UIP DV2 DV1 DV0 RS3 RS2 RS1 RS0

UIP – Update-in-Progress. The UIP bit is a status flag that can be monitored. When the UIP bit is a 1, the update transfer occurs soon. When UIP is a 0, the update transfer does not occur for at least 244µs. The time, calendar, and alarm information in RAM is fully available for access when the UIP bit is 0. The UIP bit is read-only. Writing the SET bit in Register B to a 1 inhibits any update transfer and clears the UIP status bit.

DV2, DV1, DV0 – These bits are defined as follows: DV2 = Countdown Chain

1 – Resets countdown chain only if DV1 = 1 0 – Countdown chain enabled

DV1 = Oscillator Enable

0 – Oscillator off 1 – Oscillator on, VCC power-up state

DV0 = Bank Select

0 – Original bank 1 – Extended registers

A pattern of 01x is the only combination of bits that turns the oscillator on and allows the RTC to keep time. A pattern of 11x enables the oscillator but holds the countdown chain in reset. The next update occurs at 500ms after a pattern of 01x is written to DV2, DV1, and DV0.

RS3, RS2, RS1, RS0 – These four rate-selection bits select one of the 13 taps on the 15-stage divider or disable the divider output. The tap selected can be used to generate an output square wave (SQW pin) and/or a periodic interrupt. The user can do one of the following:

§ Enable the interrupt with the PIE bit;

§ Enable the SQW output pin with the SQWE or E32k bits;

§ Enable both at the same time and the same rate; or

§ Enable neither.

Table 2 lists the periodic interrupt rates and the square-wave frequencies that can be chosen with the RS bits.

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DS17285/DS17287

MSB LSB

BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

SET PIE AIE UIE SQWE DM 24/12 DSE

SET – When the SET bit is a 0, the update transfer functions normally by advancing the counts once per second. When the SET bit is written to a 1, any update transfer is inhibited and the program can initialize the time and calendar bytes without an update occurring in the midst of initializing. Read cycles can be executed in a similar manner. SET is a read/write bit that is not modified by internal functions of the DS17285/DS17287.

PIE – Periodic Interrupt Enable. The PIE bit is a read/write bit, which allows the periodic interrupt flag (PF) bit in Register C to drive the

IRQ pin low. When the PIE bit is set to 1, periodic interrupts are

generated by driving the

IRQ pin low at a rate specified by the RS3–RS0 bits of Register A. A 0 in the

PIE bit blocks the IRQ output from being driven by a periodic interrupt, but the PF bit is still set at the periodic rate. PIE is not modified by any internal DS17285/DS17287 functions.

AIE – Alarm Interrupt Enable. The AIE bit is a read/write bit which, when set to a 1, permits the alarm flag (AF) bit in Register C to assert IRQ . An alarm interrupt occurs for each second that the three time

bytes equal the three alarm bytes, including a “don’t care” alarm code of binary 11XXXXXX. When the AIE bit is set to 0, the AF bit does not initiate the IRQ signal. The internal functions of the

DS17285/DS17287 do not affect the AIE bit.

UIE – Update-Ended Interrupt Enable. The UIE bit is a read/write bit that enables the update-end flag (UF) bit in Register C to assert IRQ . The SET bit going high clears the UIE bit.

SQWE – Square-Wave Enable. When the SQWE bit is set to a 1 and E32k = 0, a square-wave signal at the frequency set by the rate-selection bits RS3 through RS0 is driven out on the SQW pin. When the SQWE bit is set to 0and E32k = 0, the SQW pin is held low. SQWE is a read/write bit. SQWE is set to a 1 when V

is powered up.

DM – Data Mode. The DM bit indicates whether time and calendar information is in binary or BCD format. The DM bit is set by the program to the appropriate format and can be read as required. This bit is not modified by internal functions. A 1 in DM signifies binary data while a 0 in DM specifies BCD data.

24/12 – 24/12-Control Bit. This bit establishes the format of the hours byte. A 1 indicates the 24-hour mode and a 0 indicates the 12-hour mode. This bit is read/write.

DSE – Daylight Savings Enable. The DSE bit is a read/write bit that enables two special updates when DSE is set to 1. On the first Sunday in April, the time increments from 1:59:59 AM to 3:00:00 AM. On the last Sunday in October, when the time first reaches 1:59:59 AM, it changes to 1:00:00 AM. These special updates do not occur when the DSE bit is a 0. This bit is not affected by internal functions.

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DS17285/DS17287

MSB LSB

BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

IRQF PF AF UF 0 0 0 0

IRQF – Interrupt Request Flag. This bit is set to a 1 when one or more of the following are true:

PF = PIE = 1 WF = WIE= 1 AF = AIE = 1 KF = KSE= 1 UF = UIE = 1 RF = RIE = 1

i.e., IRQF = (PF x PIE) + (AF x AIE) + (UF x UIE) + (WF x WIE) + (KF x KSE) + (RF x RIE)

Any time the IRQF bit is a 1, the IRQ pin is driven low. Flag bits PF, AF, and UF are cleared after Register C is read by the program.

PF – Periodic Interrupt Flag. This is a read-only bit that is set to a 1 when an edge is detected on the selected tap of the divider chain. The RS3 through RS0 bits establish the periodic rate. PF is set to a 1

independent of the state of the PIE bit. When both PF and PIE are 1s, the IRQ signal is active and sets the IRQF bit. The PF bit is cleared by a software read of Register C.

AF – Alarm Interrupt Flag. A 1 in the AF bit indicates that the current time has matched the alarm time. If the AIE bit is also a 1, the IRQ pin goes low and a 1 appears in the IRQF bit. A read of Register

C clears AF.

UF – Update Ended Interrupt Flag. This bit is set after each update cycle. When the UIE bit is set to 1, the 1 in UF causes the IRQF bit to be a 1, which asserts the IRQ pin. UF is cleared by reading Register C.

BIT 3 to BIT 0 – These are unused bits of the status Register C. These bits always read 0 and cannot be written.

MSB LSB

BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

VRT0000000

VRT – Valid RAM and Time. This bit is a read-only status bit. When VRT = 0, the RTC and RAM data are questionable and indicates that the lithium energy source has been exhausted and should be replaced. This bit indicates that status of the V

BAT

and V

BAUX

inputs.

BIT 6 to BIT 0 – The remaining bits of Register D are not usable. They cannot be written and, when read, they always read 0.

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DS17285/DS17287

NV RAM–RTC

The general-purpose NV RAM bytes are not dedicated to any special function within the DS17285/DS17287. They can be used by the application program as nonvolatile memory and are fully available during the update cycle.

The user RAM is divided into two separate memory banks. When the bank 0 is selected, the 14 real-time clock registers and 114 bytes of user RAM are accessible. When bank 1 is selected, an additional 4kB of user RAM are accessible through the extended RAM address and data registers.

INTERRUPT CONTROL

The DS17285/DS17287 includes six separate, fully automatic sources of interrupt for a processor:

1) Alarm Interrupt

2) Periodic Interrupt

3) Update-Ended Interrupt

4) Wake-Up Interrupt

5) Kickstart Interrupt

6) RAM Clear Interrupt

The conditions that generate each of these independent interrupt conditions are described in greater detail elsewhere in this data sheet. This section describes the overall control of the interrupts.

The application software can select which interrupts, if any, should be used. There are 6 bits including 3 bits in Register B and 3 bits in Extended Register 4B that enable the interrupts. The extended register locations are described later. Writing a logic 1 to an interrupt-enable bit permits that interrupt to be

initiated when the event occurs. A logic 0 in the interrupt-enable bit prohibits the IRQ pin from being

asserted from that interrupt condition. If an interrupt flag is already set when an interrupt is enabled, IRQ is immediately be set at an active level, even though the event initiating the interrupt condition may have occurred much earlier. As a result, there are cases where the software should clear these earlier generated interrupts before first enabling new interrupts.

When an interrupt event occurs, the relating flag bit is set to a logic 1 in Register C or in Extended Register 4A. These flag bits are set regardless of the setting of the corresponding enable bit located either in Register B or in Extended Register 4B. The flag bits can be used in a polling mode without enabling the corresponding enable bits.

However, care should be taken when using the flag bits of Register C because they are automatically cleared to 0 immediately after they are read. Double latching is implemented on these bits so that bits that are set remain stable throughout the read cycle. All bits that were set are cleared when read and new interrupts that are pending during the read cycle are held until after the cycle is completed. 1 bit, 2 bits, or 3 bits can be set when reading Register C. Each used flag bit should be examined when read to ensure that no interrupts are lost.

The flag bits in Extended Register 4A are not automatically cleared following a read. Instead, each flag bit can be cleared to 0 only by writing 0 to that bit.

When using the flag bits with fully enabled interrupts, the IRQ line is driven low when an interrupt flag

bit is set and its corresponding enable bit is also set. IRQ is held low as long as at least one of the six

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