Rainbow Electronics DS1687 User Manual

www.maxim-ic.com

DS1685/DS1687

3V/5V Real-Time Clock

FEATURES

Incorporates industry-standard DS1287 PC clock plus enhanced features:

§ Y2K-compliant

§ +3 or +5V operation

§ 64-bit silicon serial number

§ Power-control circuitry supports system

power-on from date/time alarm or key closure

§ 32kHz output for power management

§ Crystal-select bit allows RTC to operate with

6pF or 12.5pF crystal

§ SMI Recovery Stack

§ 242 bytes user NV RAM

§ Auxiliary battery input

§ RAM clear input

§ Century register

§ Date alarm register

§ Compatible with existing BIOS for original

DS1287 functions

§ Available as chip (DS1685) or standalone

module with embedded battery and crystal (DS1687)

§ Timekeeping algorithm includes leap-year

compensation valid up to 2100

§ Underwriters Laboratory (UL) recognized

Package Dimension Information

http://www.maxim-ic.com/TechSupport/DallasPackInfo.htm

BAUX

N.C.

VCCSQW

RCL

GND

AD0

AD1

AD2 AD3 AD4 AD5 N.C.

X2X1PWR

4 3 2 1 28 27 26

12 13 14 15 16 17 18

PIN ASSIGNMENT (Top View)

SQW

BAUX

RCL

BAT

GND

ALE

SQW

BAUX

RCLR

N.C.

IRQ

AD0

AD1

AD2

AD3

AD4

AD5

AD6

AD7

GND

DS1685 24-Pin DIP

DS1685S 24-Pin SO (300mil)

DS1685E 24-Pin TSSOP

PWR

N.C.

AD0

AD1

AD2

AD3

AD4

AD5

AD6

AD7

GND

DS1687 24-Pin Module PDIP (740mil)

AD7

GND

ALE

AD6

N.C.

DS1685Q 28-Pin PLCC

Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device may be simultaneously available through various sales channels. For information about device errata, click here: http://www.maxim-ic.com/errata.

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ORDERING INFORMATION

DS1685/DS1687

PART PIN-PACKAGE

VOLTAGE

(V)

TOP MARK TEMP RANGE

DS1685-3 24 DIP 3 DS1685-3 0°C to +70°C DS1685-5 24 DIP 5 DS1685-5 0°C to +70°C DS1685-5IND 24 DIP 5 DS1685-5* -40°C to +85°C DS1685E-3 24 TSSOP 3 DS1685E-3 0°C to +70°C

DS1685E-5 24 TSSOP 5 DS1685E 0°C to +70°C DS1685EN-3 24 TSSOP 3 DS1685E-3* -40°C to +85°C DS1685EN-5 24 TSSOP 5 DS1685E* -40°C to +85°C

DS1685E-3/T&R

DS1685E-5/T&R

DS1685EN-3/T&R

DS1685EN-5/T&R

24 TSSOP/

Tape and Reel

24 TSSOP/

Tape and Reel

24 TSSOP/

Tape and Reel

24 TSSOP/

Tape and Reel

3 DS1685E-3 0°C to +70°C

5 DS1685E 0°C to +70°C

3 DS1685E-3* -40°C to +85°C

5 DS1685E* -40°C to +85°C

DS1685Q-3 24 PLCC 3 DS1685Q-3 0°C to +70°C DS1685Q-5 24 PLCC 5 DS1685Q-5 0°C to +70°C

DS1685QN-3 24 PLCC 3 DS1685Q-3* -40°C to +85°C

DS1685QN-5 24 PLCC 5 DS1685Q-5* -40°C to +85°C

DS1685QN-5/T&R 24 PLCC/Tape and Reel 5 DS1685Q-5* -40°C to +85°C

DS1685Q-3/T&R 24 PLCC/Tape and Reel 3 DS1685Q-3 0°C to +70°C

DS1685Q-5/T&R 24 PLCC/Tape and Reel 5 DS1685Q-5 0°C to +70°C

DS1685S-3 24 SO 3 DS1685S-3 0°C to +70°C

DS1685S-5 24 SO 5 DS1685S-5 0°C to +70°C

DS1685SN-3 24 SO 3 DS1685S-3* -40°C to +85°C

DS1685SN-5 24 SO 5 DS1685S-5* -40°C to +85°C

DS1685SN-5/T&R 24 SO/Tape and Reel 5 DS1685S-5* -40°C to +85°C

DS1685S-3/T&R 24 SO/Tape and Reel 3 DS1685S-3 0°C to +70°C

DS1685S-5/T&R 24 SO/Tape and Reel 5 DS1685S-5 0°C to +70°C

DS1687-3

DS1687-5

DS1687-3IND

DS1687-5IND

24 PDIP Module

(740mil)

24 PDIP Module

(740mil)

24 PDIP Module

(740mil)

24 PDIP Module

(740mil)

3 DS1687-3 0°C to +70°C

5 DS1687-5 0°C to +70°C

3 DS1687-3* -40°C to +85°C

5 DS1687-5* -40°C to +85°C

*An “N” located in the right-hand corner of the top of the package denotes an industrial device.

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DS1685/DS1687

TYPICAL OPERATING CIRCUIT

DESCRIPTION

The DS1685/DS1687 is a real-time clock (RTC) designed as a successor to the industry-standard DS1285, DS1385, DS1485, and DS1585 PC RTCs. This device provides the industry-standard DS1285 clock function with either +3.0V or +5.0V operation. The DS1685 also incorporates a number of enhanced features including a silicon serial number, power-on/off control circuitry, 242 bytes of user NV SRAM, and 32.768kHz output for sustaining power management activities.

The DS1685/DS1687 power-control circuitry allows the system to be powered on by an external stimulus

such as a keyboard or by a time and date (wake-up) alarm. The PWR output pin can be triggered by one

or either of these events, and can be used to turn on an external power supply. The PWR pin is under software control, so that when a task is complete, the system power can then be shut down.

The DS1685 is a clock/calendar chip with the features described above. An external crystal and battery are the only components required to maintain time-of-day and memory status in the absence of power. The DS1687 incorporates the DS1685 chip, a 32.768kHz crystal, and a lithium battery in a complete, self-contained timekeeping module. The entire unit is fully tested at Dallas Semiconductor such that a minimum of 10 years of timekeeping and data retention in the absence of V

is guaranteed.

OPERATION

The block diagram in Figure 1 shows the pin connections with the major internal functions of the DS1685/DS1687. The following paragraphs describe the function of each pin.

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SIGNAL DESCRIPTIONS

GND, VCC – DC power is provided to the device on these pins. VCC is the +3V or +5V input.

DS1685/DS1687

SQW (Square-Wave Output) - The SQW pin provides a 32kHz square-wave output, t

, after a power-

REC

up condition has been detected. This condition sets the following bits, enabling the 32kHz output; DV1 = 1, and E32K = 1. A square wave is output on this pin if either SQWE = 1 or E32K = 1. If E32K = 1, then 32kHz is output regardless of the other control bits. If E32K = 0, then the output frequency is dependent on the control bits in register A. The SQW pin can output a signal from one of 13 taps provided by the 15 internal divider stages of the RTC. The frequency of the SQW pin can be changed by programming Register A as shown in Table 2. The SQW signal can be turned on and off using the SQWE bit in register B or the E32K bit in extended register 4Bh. A 32kHz SQW signal is output when the enable-32kHz (E32K) bit in extended register 4Bh is a logic 1 and VCC is above VPF. A 32kHz square wave is also available when VCC is less than VPF if E32K = 1, ABE = 1, and voltage is applied to the V

BAUX

pin.

AD0–AD7 (Multiplexed Bidirectional Address/Data Bus) – Multiplexed buses save pins because address information and data information time-share the same signal paths. The addresses are present during the first portion of the bus cycle and the same pins and signal paths are used for data in the second portion of the cycle. Address/data multiplexing does not slow the access time of the DS1685 since the bus change from address to data occurs during the internal RAM access time. Addresses must be valid prior to the latter portion of ALE, at which time the DS1685/DS1687 latches the address. Valid write data must

be present and held stable during the latter portion of the WR pulse. In a read cycle, the DS1685/DS1687

outputs 8 bits of data during the latter portion of the RD pulse. The read cycle is terminated and the bus

returns to a high-impedance state as RD transitions high. The address/data bus also serves as a bidirectional data path for the external extended RAM.

ALE (RTC Address-Strobe Input; Active High) – A pulse on the address strobe pin serves to demultiplex the bus. The falling edge of ALE causes the RTC address to be latched within the DS1685/DS1687.

RD (RTC Read Input; Active Low) - RD identifies the time period when the DS1685/DS1687 drives

the bus with RTC read data. The RD signal is an enable signal for the output buffers of the clock.

WR (RTC Write Input; Active Low) -The WR signal is an active-low signal. The WR signal defines

the time period during which data is written to the addressed register.

CS (RTC Chip-Select Input; Active Low) – The chip-select signal must be asserted low during a bus

cycle for the RTC portion of the DS1685/DS1687 to be accessed.

during

RD and WR timing. Bus cycles that take place with ALE asserted but without asserting CS latch

CS must be kept in the active state

addresses. However, no data transfer occurs.

IRQ (Interrupt-Request Output; Open Drain, Active Low) – The IRQ pin is an active-low output of

the DS1685/DS1687 that can be connected to the interrupt input of a processor. The

IRQ output remains

low as long as the status bit causing the interrupt is present and the corresponding interrupt-enable bit is

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DS1685/DS1687

set. To clear the IRQ pin, the application software must clear all enabled flag bits contributing to IRQ ’s active state.

When no interrupt conditions are present, the IRQ level is in the high-impedance state. Multiple

interrupting devices can be connected to an IRQ bus. The IRQ pin is an open-drain output and requires an external pullup resistor. The voltage on the pullup supply should be no greater than VCC + 0.2V.

PWR (Power-On Output; Open Drain, Active Low) – The PWR pin is intended for use as an on/off

control for the system power. With VCC voltage removed from the DS1685/DS1687, PWR can be

automatically activated from a kickstart input by the KS pin or from a wake-up interrupt. Once the

system is powered on, the state of PWR can be controlled by bits in the Dallas registers. The PWR pin can be connected through a pullup resistor to a positive supply. For 5V operation, the voltage of the pullup supply should be no greater than 5.7V. For 3V operation, the voltage of the pullup supply should be no greater than 3.9V.

KS (Kickstart Input; Active Low) – When V

is removed from the DS1685/DS1687, the system can

be powered on in response to an active-low transition on the KS pin, as might be generated from a key closure. V

function is used, and the KS pin must be pulled up to the V

must be present and the auxiliary-battery enable bit (ABE) must be set to 1 if the kickstart

BAUX

supply. While VCC is applied, the KS pin

BAUX

can be used as an interrupt input.

RCLR (RAM Clear Input; Active Low) – If enabled by software, taking RCLR low clears the 242

bytes of user RAM. When enabled, RCLR can be activated whether or not VCC is present. The RCLR function is designed to be used by a human interface (shorting to ground manually or by a switch) and not to be driven with external buffers. This pin is internally pulled up. Do not use an external pullup resistor on this pin.

clock/ calendar and user RAM if V

– Auxiliary battery input required for kickstart and wake-up features. This input also supports

BAUX

is at lower voltage or is not present. A standard +3V lithium cell or

BAT

other energy source can be used. Battery voltage must be held between +2.5V and +3.7V for proper operation. If V

is not going to be used it should be grounded, and auxiliary-battery enable bit bank 1,

BAUX

See “Conditions of Acceptability” at http://www.maxim-ic.com/TechSupport/QA/ntrl.htm.

DS1685 ONLY

X1, X2 – Connections for a standard 32.768kHz quartz crystal. For greatest accuracy, the DS1685 must be used with a crystal that has a specified load capacitance of either 6pF or 12.5pF. The crystal-select (CS) bit in Extended Control Register 4B is used to select operation with a 6pF or 12.5pF crystal. The crystal is attached directly to the X1 and X2 pins. There is no need for external capacitors or resistors. Note: X1 and X2 are very high-impedance nodes. It is recommended that they and the crystal be guardringed with ground and that high-frequency signals be kept away from the crystal area.

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DS1685/DS1687

– Battery input for any standard 3V lithium cell or other energy source. Battery voltage must be

BAT

held between 2.5V and 3.7V for proper operation. V be placed between V

and the battery.

BAT

must be grounded if not used. Diodes should not

BAT

N.C. – No Connection.

See “Conditions of Acceptability” at http://www.maxim-ic.com/TechSupport/QA/ntrl.htm

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Figure 1. BLOCK DIAGRAM

DS1685/DS1687

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DS1685/DS1687

OSCILLATOR STARTUP TIME

Oscillator startup times are highly dependent upon crystal characteristics and layout. High ESR and excessive capacitive loads are the major contributors to long startup times. A circuit using a crystal with the recommended characteristics and following the recommended layout usually starts within one second.

CLOCK ACCURACY

The accuracy of the clock is dependent on the accuracy of the crystal and the accuracy of the match between the capacitive load of the oscillator circuit and the capacitive load for which the crystal was trimmed. Additional error is added by crystal frequency drift caused by temperature shifts. External circuit noise coupled into the oscillator circuit can result in the clock running fast.

The DS1685 can also be driven by an external 32.768 kHz oscillator. In this configuration, the X1 pin is connected to the external oscillator signal and the X2 pin is floated. Refer to Application Note 58 “Crystal Considerations with Dallas Real-Time Clocks” for detailed information about crystal selection and crystal layout.

RECOMMENDED LAYOUT FOR CRYSTAL

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DS1685/DS1687

POWER-DOWN/POWER-UP CONSIDERATIONS

The RTC function continues to operate, and all of the RAM, time, calendar, and alarm memory locations remain nonvolatile regardless of the level of the VCC input. When VCC is applied to the DS1685/DS1687 and reaches a level of greater than VPF (power-fail trip point), the device becomes accessible after t provided that the oscillator is running and the oscillator countdown chain is not in reset (Register A). This time period allows the system to stabilize after power is applied.

The DS1685/DS1687 is available in either a 3V or a 5V device.

The 5V device is fully accessible and data can be written and read only when VCC is greater than 4.5V. When VCC is below 4.5V, read and writes are inhibited. However, the timekeeping function continues unaffected by the lower input voltage. As VCC falls below the greater of V timekeeper are switched over to a lithium battery connected either to the V

BAT

pin or V

BAT

and V

, the RAM and

BAUX

pin.

BAUX

The 3V device is fully accessible and data can be written or read only when VCC is greater than 2.7V. When VCC falls below VPF, access to the device is inhibited. If VPF is less than V power supply is switched from VCC to the backup supply (the greater of V drops below VPF. If VPF is greater than V backup supply when VCC drops below the larger of V

BAT

and V

, the power supply is switched from VCC to the

BAUX

BAT

and V

BAUX

BAT

and V

BAT

and V

) when V

BAUX

REC

, the

When VCC falls below VPF, the chip is write-protected. With the possible exception of the KS , PWR , and SQW pins, all inputs are ignored and all outputs are in a high-impedance state.

RTC ADDRESS MAP

The address map for the RTC registers of the DS1685/DS1687 is shown in Figure 2. The address map consists of the 14 clock/calendar registers. Ten registers contain the time, calendar, and alarm data, and four bytes are used for control and status. All registers can be directly written or read except for the following:

1) Registers C and D are read-only.

2) Bit 7 of Register A is read-only.

3) The high order bit of the seconds byte is read-only.

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Figure 2. DS1685 RTC ADDRESS MAP

DS1685/DS1687

0 00H 0 SECONDS

14 0EH 3 MINUTES ALARM

64 040H 5 HOURS ALARM

127 07FH 13 REGISTER D

CLOCK/

CALENDAR

14 BYTES

50 BYTES

USER RAM

BANK0, BANK 1

REGISTERS,

RAM

1 SECONDS ALARM

0DH 2 MINUTES

03FH 4 HOURS

6 DAY OF THE WEEK

7 DAY OF THE MONTH

8MONTH

9 YEAR

10 REGISTER A

11 REGISTER B

12 REGISTER C

BINARY OR BCD INPUTS

TIME, CALENDAR, AND ALARM LOCATIONS

The time and calendar information is obtained by reading the appropriate register bytes shown in Table 1. The time, calendar, and alarm are set or initialized by writing the appropriate register bytes. The contents of the time, calendar, and alarm registers can be either binary or binary coded decimal (BCD) format. Table 1 shows the binary and BCD formats of the 10 time, calendar, and alarm locations that reside in both bank 0 and in bank 1, plus the two extended registers that reside in bank 1 only (bank 0 and bank 1 switching are explained later in this text).

Before writing the internal time, calendar, and alarm registers, the SET bit in Register B should be written to a logic 1 to prevent updates from occurring while access is being attempted. Also at this time, the data format (binary or BCD) should be set by the data mode bit (DM) of Register B. All time, calendar, and alarm registers must use the same data mode. The set bit in Register B should be cleared after the data mode bit has been written to allow the RTC to update the time and calendar bytes.

Once initialized, the RTC makes all updates in the selected mode. The data mode cannot be changed without reinitializing the 10 data bytes. The 24/12 bit cannot be changed without reinitializing the hour locations. When the 12-hour format is selected, the high order bit of the hours byte represents PM when it is a logic 1. The time, calendar, and alarm bytes are always accessible because they are double buffered. Once per second the 10 bytes are advanced by one second and checked for an alarm condition. If a read of the time and calendar data occurs during an update, a problem exists where seconds, minutes, hours, etc., might not correlate. The probability of reading incorrect time and calendar data is low. Several methods of avoiding any possible incorrect time and calendar reads are covered later.

The three time alarm bytes can be used in two ways. First, when the alarm time is written in the appropriate hours, minutes, and seconds alarm locations, the alarm interrupt is initiated at the specified time each day if the alarm enable bit is high. The second use condition is to insert a “don’t care” state in one or more of the three time-alarm bytes. The “don’t care” code is any hexadecimal value from C0 to FF. The two most significant bits of each byte set the “don’t care” condition when at logic 1. An alarm is

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DS1685/DS1687

generated each hour when the “don’t care” bits are set in the hours byte. Similarly, an alarm is generated every minute with “don’t care” codes in the hours and minute alarm bytes. The “don’t care” codes in all three time alarm bytes create an interrupt every second. The three time-alarm bytes can be used with the date alarm as described in the Wake-Up/Kickstart section. The century counter is discussed later in this text.

Table 1. TIME, CALENDAR, AND ALARM DATA MODES

ADDRESS

LOCATION

FUNCTION

DECIMAL

RANGE

DATA MODE RANGE

BINARY BCD

00H Seconds 0–59 00–3B 00–59 01H Seconds Alarm 0–59 00–3B 00–59 02H Minutes 0–59 00–3B 00–59 03H Minutes Alarm 0–59 00–3B 00–59

04H

Hours 12-hour Mode 1–12

01–0C AM,

81–8C PM

Hours 24-hour Mode 0–23 00–17 00–23

05H

Hours Alarm 12-hour

Mode

Hours Alarm 24-hour

Mode

1–12

0–23 00–17 00–23

01–0C AM,

81–8C PM

06H Day of Week Sunday = 1 1–7 01–07 01–07 07H Date of Month 1–31 01–1F 01–31 08H Month 1–12 01–0C 01–12 09H Year 0–99 00–63 00–99

BANK 1,

48H

BANK 1,

49H

Century 0–99 00–63 00–99

Date Alarm 1–31 01–1F 01–31

01–12 AM,

81–92 PM

01–12 AM,

81–92 PM

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DS1685/DS1687

CONTROL REGISTERS

The four control registers A, B, C, and D reside in both bank 0 and bank 1. These registers are accessible at all times, even during the update cycle.

MSB LSB

BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

UIP DV2 DV1 DV0 RS3 RS2 RS1 RS0

UIP – The update-in-progress (UIP) bit is a status flag that can be monitored. When the UIP bit is a 1, the update transfer occurs soon. When UIP is a 0, the update transfer does not occur for at least 244ms. The time, calendar, and alarm information in RAM is fully available for access when the UIP bit is 0. The UIP bit is read-only. Writing the SET bit in Register B to a 1 inhibits any update transfer and clears the UIP status bit.

DV2, DV1, DV0 – These bits are defined as follows:

DV2 = Countdown Chain

1 – resets countdown chain only if DV1 = 1 0 – countdown chain enabled

DV1 = Oscillator Enable

0 – oscillator off 1 – oscillator on

DV0 = Bank Select

0 – original bank

A pattern of 01X is the only combination of bits that turns the oscillator on and allows the RTC to keep time. A pattern of 11X enables the oscillator but holds the countdown chain in reset. The next update occurs at 500ms after a pattern of 01X is written to DV2, DV1, and DV0.

RS3, RS2, RS1, RS0 – These four rate-selection bits select one of the 13 taps on the 15-stage divider or disable the divider output. The tap selected can be used to generate an output square wave (SQW pin) and/or a periodic interrupt. The user can do one of the following:

1) Enable the interrupt with the PIE bit;

2) Enable the SQW output pin with the SQWE or E32K bits;

3) Enable both at the same time and the same rate; or

4) Enable neither.

Table 2 lists the periodic interrupt rates and the square-wave frequencies that can be chosen with the RS bits.

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Rainbow Electronics DS1687 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual