Rainbow Electronics DS1680 User Manual

DS1680

www.maxi

m-ic.com

44-

Pin MQFP (10 x 10 x 2mm)

Package dimension information can be found at:

Portable System Controller

with Touch-Screen Control

FEATURES

PIN ASSIGNMENT

§ Real-time clock (RTC)

− Counts seconds, minutes, hours, date,

month, day of the week, and year with leap-year compensation valid up to 2100

− Power control circuitry supports system

power-on from day/time alarm

§ Microprocessor monitor

− Halts microprocessor during power-fail

− Automatically restarts microprocessor

after power failure

− Monitors pushbutton for external

override

− Halts and resets an out of control

microprocessor

§ NV RAM control

− Automatic battery backup and write

protection to external SRAM

§ 1.25V threshold detector for power-fail

BAT

X2 AVG BHE

COEN

OUT_SELECT

CONVERT

PD_RESET

PEN_SELECT

ANSELIN

INT

AVS

I/O

REF

SCLK

AIN1

AIN0

CCO

CSSTVCCRST

Y-

X+

Y+

AVD

PFO

CEO

X-

PEN_OFF

CEI

2311

OSCIN

PFI GND D7 D6 D5 D4 D3 D2 D1 D0 NEW_DATA

warning

§ 10-bit analog-to-digital converter (ADC)

− Monotonic with no missing codes

http://www.maxim-ic.com/TechSupport/DallasPackInfo.htm

§ Four-wire analog resistive touch-screen interface

ORDERING INFORMATION

DS1680FP-3 3.3V Operation DS1680FP-5 5.0V Operation

DESCRIPTION

The DS1680 incorporates many functions necessary for low-power portable products, providing an RTC, NV RAM controller, microprocessor monitor, power-f ail warning, 10-bit ADC, and a touch-screen controller in one chip.

The RTC provides seconds, minutes, hours, day, date, month, and year information with leap-year compensation as well as an alarm interrupt. This interrupt works when the DS1680 is powered by the system power supply or when in battery-backup operation, so the alarm can be used to wake up a system that is powered down.

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DS1680

CLOCK

OSC

CLOCK

GEN

PANEL

DRIVE

CONVERT

CONTROL

10-BIT

ADC

INPUT

MUX

TOUCH

DETECT

POWER

CONTROL

RTC

SERIAL

INTERFACE

WATCHDOG

OUTPUT

MUX

BHE

OUT_SELECT

PEN_SELECT

AIN0

AIN1

COEN

CONVERT

PEN_OFF

PD_RST

D0-D7

OSCIN

X1X2INT

SCLK

I/O

RST

POWER SWITCH,

WRITE PROTECT,

NV CONTROL,

AND

POWER FAIL

WARNING

VCCV

CEI

CEO

PFI

PFO

ANSELIN

X+X-Y+Y-NEW_DATA

Automatic backup and write protection of an external SRAM is provided through the V

CCO

and

CEO pins. The backup energy source used to power the RTC is also used to retain RAM data in the

absence of VCC through the V

pin. The chip -enable output to SRAM, CE0 , is controlled during power

CCO

transients to prevent data corruption.

The DS1680’s microprocessor-monitor circuitry provides three basic functions. First, a precision temperature-compensated reference and comparator circuit monitors the status of VCC. When an out -of-

tolerance condition occurs, an internal power-fail signal is generated that forces RST to the active state. When VCC returns to an in-tolerance condition, the RST signal is kept in the active state for t

to allow

RPU

the power supply and processor to stabilize. The DS1680 debounces a pushbutton input and guarantees an active RST pulse width of t

. The third function is a watchdog timer. The DS1680’s internal timer

RST

forces the RST signal to the active state if the strobe input is not driven low prior to watchdog time-out.

The DS1680 also provides a touch-screen controller along with a 10-bit successive approximation ADC. The ADC is monotonic (no missing codes) and has an internal analog filter to reduce high frequency noise.

DS1680 BLOCK DIAGRAM Figure 1

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BAT

CCO

DS1680

SIGNAL DESCRIPTIONS

VCC, GND (Digital Supply and Digital Ground) – DC power to the RTC, watchdog, X and Y drivers, and power-switching circuitry is provided to the device on these pins.

(Backup Power Supply) – Battery input for standard 3V lithium cell or other energy source.

BAT

SCLK (Serial Clock Input) – SCLK is used to synchronize data movement on the serial interface.

I/O (Data Input/Output) – The I/O pin is the bidirectional data pin for the 3-wire interface.

CS (Chip Select) – The chip-select signal must be asserted high during a read or a write for

communication over the 3-wire serial interface.

(External SRAM Power Supply Output) – This pin is internally connected to V

CCO

within nominal limits. However, during power-fail V Switchover occurs when V

drops below V

CCSW

is internally connected to the V

CCO

INT (Interrupt Output) – The INT pin is an active-high output of the DS1680 that can be used as an interrupt input to a microprocessor. The INT output remains high as long as the status bit causing the interrupt is present and the corresponding interrupt-enable bit is set. The INT pin operates when the DS1680 is powered by VCC or V

BAT

when VCC is

BAT

pin.

CEI (SRAM Chip-Enable Input) – CEI must be driven low to enable the external SRAM.

CEO (SRAM Chip-Enable Output) – Chip-enable output for SRAM.

PFI (Power-Fail Input) – Power-fail comparator input. When PFI is less than 1.25V, PFO goes low; otherwise PFO remains high. Connect PFI to GND or VCC when not used.

PFO (Power-Fail Output) – Power-fail output goes low and sinks current when PFI is less than 1.25V;

otherwise PFO remains high.

SI (Strobe Input) – The strobe input pin is used in conjunction with the watchdog timer. If the ST pin is

not driven low within the watchdog time period, the RST pin is driven low.

RST (Reset) – The RST pin functions as a microprocessor reset signal. This pin has an internal 47kΩ

pullup resistor. X1, X2 – Connections for a standard 32.768kHz quartz crystal. For greatest accuracy, the DS1680 must

be used with a crystal that has a specified load capacitance of 6pF. There is no need for external capacitors or resistors. Note: X1 and X2 are very high-impedance nodes. It is recommended that they and the crystal be guard-ringed with ground and that high-frequency signals be kept away from the crystal area. For more information about crystal selection and crystal layout considerations, please consult Application Note 58, “Crystal Considerations with Dallas Real-Time Clocks.” The DS1680 will not function without a crystal.

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DS1680

AVD, AVS (ADC Supply and Ground) – Power supply and ground for the ADC.

AIN0, AIN1 (Analog Inputs) – These pins are the analog inputs for the ADC.

(Voltage Reference) – Reference voltage for the ADC.

REF

X+, X- (Resistive Tablet X Plane Dri ver) – Connect to X-terminal of resistive tablet.

Y+, Y- (Resistive Tablet Y Plane Driver) – Connect to Y-terminal of resistive tablet. CONVERT – Assert to logic 1 to request sample from AIN0 or AIN1. Use with ANSELIN input. ANSELIN (Analog Select Input ) – Assert to logic 0 to select AIN0. Assert to logic 1 to select AIN1.

Use with CONVERT input. BHE (Bus High Enable Input) – Drive to logic 1 to select high byte (data bits 2–9). Drive to logic 0 to

select low byte (data bits 0–1). The lower 6 bits will all be zeros when asserted low.

PEN_SELECT (Pen Select Input) – Assert to logic 1 to select X- or Y- data output. Assert to logic 0 to select AIN0 or AIN1 data output. Use with OUT_SELECT input.

OUT_SELECT (Output Select Input) – Assert to logic 0 to select AIN0 or X- data. Assert to logic 1 to select AIN1 or Y- data. Use with PEN_SELECT input.

COEN (Chip Output Enable) – The COEN pin must be asserted low to enable the ADC data to be

read on D0–D7.

D0-D7 (Data Bus) – Data output from ADC.

AVG (Data Average Select Pin) – Logic 1 selects data average mode; logic 0 selects raw data mode.

NEW_DATA (New Data Indicator) – A logic 0 pulse indicates that new data packet is available on

D0–D7.

OSCIN (Oscillator Input) – Input for the ADC clock.

PEN_OFF (Pen Detection Output) – Indicates pen not detected. Logic 1 if pen is not detected. PD_RESET (Power Down/Reset Input) – Assert logic 1 for ≥10ns to reset. Hold at logic 1 for power-

down mode of the analog circuitry.

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DS1680

3-WIRE SERIAL INTERFACE

Communication with the RTC and watchdog is accomplished through a simple 3-wire interface consisting of the chip select (CS), serial clock (SCLK), and input/output (I/O) pins.

All data transfers are initiated by driving the CS input high. The CS input serves two functions. First, CS turns on the control logic, which allows access to the shift register for the address/command sequence. Second, the CS signal provides a method of terminating either single byte or multip le byte (burst) data transfer. A clock cycle is a sequence of a rising edge followed by a falling edge. For data input, data must be valid during the clock’s rising edge and data bits are output on the clock’s falling edge. If the CS input goes low, all da ta transfer terminates and the I/O pin goes to a high-impedance state.

Address and data bytes are always shifted LSB first into the I/O pin. Any transaction requires the address/command byte to specify a read or write to a specific register followed by one or more bytes of data. The address byte is always the first byte entered after CS is driven high. The most significant bit (RD /WR) of this byte determines if a read or write will take place. If this bit is 0, one or more read cycles will occur. If this bit is 1, one or more write cycles will occur.

Data transfers can occur one byte at a time or in multiple-byte burst mode. After CS is driven high an address is written to the DS1680. After the address, one or more data bytes can be read or written. For a single byte transfer one byte is read or written and then CS is driven low. Multiple bytes can be read or written to the DS1680 after the address has been written. Each read or write cycle causes the register address to automatically increment. Incrementing continues until the device is disabled. After accessing register 0Dh, the address wraps to 00h.

Data transfer for single-byte transfer and multiple -byte burst transfer is illustrated in Figures 2 and 3.

SINGLE- BYTE DATA TRANSFER Figure 2

MULTIPLE-BYTE BURST TRANSFER Figure 3

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DS1680

ADDRESS/COMMAND BYTE

Figure 4 shows the command byte for the DS1680. Each data transfer is initiated by a command byte. Bits 0–6 specify the address of the registers to be accessed. The MSB (bit 7) is the read/write bit. This bit specifies whether the accessed byte will be read or written. A read operation is selected if bit 7 is a zero and a write operation is selected if bit 7 is a one. The address map for the DS1680 is shown in Figure 5.

ADDRESS/COMMAND BYTE Figure 4

7 6 5 4 3 2 1 0

A6 A5 A4 A3 A2 A1 A0

RTC/WATCHDOG ADDRESS MAP Figure 5

BIT7

00 0 10 SECONDS SECONDS 01 0 10 MINUTES MINUTES

12 24

10 HR

A/P

10 HR HOURS

03 0 0 0 0 0 DAY 04 0 0 10 DATE DATE 05 0 0 0 10 MO. 06 10 YEAR YEAR 07 M 10 SEC ALARM SECONDS ALARM 08 M 10 MIN ALARM MINUTES ALARM

12 24

10 HR

A/P

10 HR HOUR ALARM

0A M 0 0 0 0 DAY ALARM 0B CONTROL REGISTER 0C STATUS REGISTER 0D WATCHDOG REGISTER 0E

RESERVED

BIT0

MONTH

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DS1680

CLOCK, CALENDAR, AND ALARM

The time and calendar information is accessed by reading/writing the appropriate register bytes. Note that some bits are set to zero. These bits will always read zero regardless of how they are written. Also note that registers 0Eh to 7Fh are reserved. These registers will always read zero regardless of how they are written. The contents of the time, calendar, and alarm registers are in the binary-coded decimal (BCD) format.

The DS1680 can run in either 12-hour or 24-hour mode. Bit 6 of the hours register is defined as the 12- or 24-hour mode select bit. When high, the 12-hour mode is selected. In the 12-hour mode, bit 5 is the AM/PM bit with logic one being PM. In the 24-hour mode, bit 5 is the second 10-hour bit (20–23 hours).

The DS1680 also contains a time-of-day alarm. The alarm registers are located in registers 07h to 0Ah. Bit 7 of each of the alarm registers are mask bits (Table 1). When all of the mask bits are logic 0, an alarm will occur once per week when the values stored in time-keeping registers 00h to 03h match the values stored in the time-of -day alarm registers. An alarm will be generated every day when mask bit of the day alarm register is set to one. An alarm wil l be generated every hour when the day and hour alarm mask bits are set to one. Similarly, an alarm will be generated every minute when the day, hour, and minute alarm mask bits are set to one. When day, hour, minute, and second alarm mask bits are set to one, an alarm will occur every second.

TIME- OF-DAY ALARM BITS Table 1

ALARM REGISTER MASK BITS (BIT 7)

Seconds Minutes Hours Day

1 1 1 1 Alarm once per second. 0 1 1 1 Alarm when seconds match. 0 0 1 1 Alarm when minutes and seconds match. 0 0 0 1 Alarm when hours, minutes and seconds match. 0 0 0 0 Alarm when day, hours, minutes and seconds match.

SPECIAL PURPOSE REGISTERS

The DS1680 has two additional registers (control register and status register) that control the RTC and interrupts.

CONTROL REGISTER – 0Bh

BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

EOSC

WP SP1 SP0 0 0 0 AIE

EOSC (Enable Oscillator) – This bit, when set to logic 0, will start the oscillator. When this bit is set to

a logic 1, the oscillator is stopped and the DS1680 is placed into a low-power standby mode (I

BAT

) when

in battery-backup mode. When the DS1680 is powered by VCC, the oscillator is always on regardless of the status of the EOSC bit; however, the RTC is incremented only when EOSC is a logic 0.

SP0 and SP1 (Speed Select) – These bits select the on time of the X- and Y-measurement duty cycle. The programmable duty cycle section has more detail.

WP (Write Protect) – Before any write operation to the RTC or any other registers, this bit must be logic

0. When high, the write-protect bit prevents a write operation to any register.

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