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DS1672
Low-Voltage Serial Timekeeping Chip
GENERAL DESCRIPTION
The DS1672 low-voltage serial timekeeping chip
incorporates a 32-bit counter and powermonitoring functions. The 32-bit counter is
designed to count seconds and can be used to
derive time-of-day, week, month, month, and
year by using a software algorithm. A precision,
temperature-compensated reference and
comparator circuit monitors the status of VCC.
When an out-of-tolerance condition occurs, an
internal power-fail signal is generated that forces
the reset to the active state. When VCC returns to
an in-tolerance condition, the reset signal is kept
in the active state for 250ms to allow the power
supply and processor to stabilize.
TYPICAL OPERATING CIRCUIT
FEATURES
§ 32-bit counter
§ 2-wire serial interface
§ Automatic power-fail detect and switch
circuitry
§ Power-fail reset output
§ Low-voltage oscillator operation (1.3V min)
§ Trickle charge capability
§ Underwriters Laboratory (UL) recognized
ORDERING INFORMATION
PART
DS1672-2
DS1672-3
DS1672-33
DS1672S-2
DS1672S-3
DS1672S-33
DS1672U-2
DS1672U-3
DS1672U-
33
TEMP
RANGE
-40°C to +85°C 8 0.300" DIP DS1672-2
-40°C to +85°C 8 0.300" DIP DS1672-3
-40°C to +85°C 8 0.300" DIP DS1672-33
-40°C to +85°C 8 0.150" SO DS1672-2
-40°C to +85°C 8 0.150" SO DS1672-3
-40°C to +85°C 8 0.150" SO DS1672-33
-40°C to +85°C 8 µSOP 1672rr-2
-40°C to +85°C 8 µSOP 1672rr-22
-40°C to +85°C 8 µSOP 1672rr-33
PINPACKAGE
TOP
MARK
PIN CONFIGURATION
TOP VIEW
V
BACKUP
X1
X2
GND
Package Dimension Information
www.maxim-ic.com/TechSupport/DallasPackInfo.htm
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device
may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata.
1 of 12 100302
1
2
3
4
DIP
SO
SOP
8
V
CC
RST
7
6
SCL
SDA
5
DS1672
ABSOLUTE MAXIMUM RATINGS
Voltage Range on Any Pin Relative to Ground -0.5V to +6.0V
Operating Temperature Range -40°C to +85°C
Storage Temperature Range -55°C to +125°C
Soldering Temperature See IPC/JEDEC J-STD-020A
This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operation
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time can affect reliability.
RECOMMENDED DC OPERATING CONDITIONS
(TA = -40°C to +85°C)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Supply Voltage (DS1672-33)
(DS1672-3)
(DS1672-2)
Logic 1 V
Logic 0 V
Backup Supply Voltage V
Note 1: All voltages referenced to ground.
V
CC
V
CC
V
CC
IH
IL
BACKUP
2.97 3.3 3.63 V 1
2.7 3.0 3.3 V 1
1.8 2.0 2.2 V 1
0.7V
CC
-0.5 0.3V
V
+ 0.5 V 1
CC
CC
V1
1.3 3.0 3.63 V 1
DC ELECTRICAL CHARACTERISTICS
(V
Active Supply Current I
Standby Current I
Power-Fail Voltage V
Power-Fail Voltage V
Power-Fail Voltage V
V
Logic 0 Output (VOL = 0.4V) I
Logic 0 Output (DS1672-2)
(V
(V
Note 1: All voltages referenced to ground.
Note 2: I
Note 3: I
Note 4: SDA and RST .
< VCC < V
CCMIN
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Leakage Current I
BACKUP
> 2 V; VOL = 0.4V)
CC
< 2 V; VOL = .2VCC)
CC
specified with SCL clocking at max frequency (400kHz), trickle charger disabled.
CCA
specified with VCC = V
CCS
CCMAX, TA
CCTYP
= -40°C to +85°C)
CCA
CCS
PF
PF
PF
BACKUPLKG
OL
I
OL
and SDA, SCL = V
, trickle charger disabled.
CCTYP
600
500
mA
mA
2.80 2.88 2.97 V
2.5 2.6 2.7 V
1.6 1.7 1.8 V
25 50 nA
3 mA 1, 4
3
3
mA 1, 4
2
3
2 of 12
DC ELECTRICAL CHARACTERISTICS
(VCC = 0V, TA = -40°C to +85°C)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
V
V
Note 5: Using the recommended crystal on X1 and X2.
Current (Osc on) I
BACKUP
Current (Osc off) I
BACKUP
BACKUPOSC
BACKUP
0.425 1
200 nA
mA
DS1672
5
CRYSTAL SPECIFICATIONS
*
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Nominal Frequency F
O
32.768 kHz
Series Resistance ESR 45 kΩ
Load Capacitance C
*The crystal, traces, and crystal input pins should be isolated from RF generating signals. Refer to Application Note 58: Crystal Considerations
for Dallas Real-Time Clocks for additional specifications
L
6pF
3 of 12
AC ELECTRICAL CHARACTERISTICS
(VCC > V
PARAMETER SYMBOL CONDITION MIN TYP MAX UNITS NOTES
, TA = -40°C to +85°C)
CCMIN
DS1672
SCL Clock
Frequency
Bus Free Time
Between a STOP and
START Condition
Hold Time
(Repeated) START
Condition
LOW Period of SCL
Clock
HIGH Period of SCL
Clock
Setup Time for a
Repeated START
Condition
Data Hold Time t
Data Setup Time t
Rise Time of Both
SDA and SCL
Signals
Fall Time of Both
SDA and SCL
Signals
Setup Time for STOP
Condition
f
SCL
t
BUF
t
HD:STA
t
LOW
t
HIGH
t
SU:STA
HD:DAT
SU:DAT
t
R
t
F
t
SU:STO
Fast Mode 100 400
Standard Mode 100
Fast Mode 1.3
Standard Mode 4.7
Fast Mode 0.6
Standard Mode 4.0
Fast Mode 1.3
Standard Mode 4.7
Fast Mode 0.6
Standard Mode 4.0
Fast Mode 0.6
Standard Mode 4.7
Fast Mode 0 0.9
Standard Mode 0
Fast Mode 100
Standard Mode 250
Fast Mode 20 + 0.1C
B
300
Standard Mode 1000
Fast Mode 20 + 0.1C
B
300
Standard Mode 300
Fast Mode 0.6
Standard Mode 4.0
kHz
ms
ms
ms
ms
ms
ms
ns 9
ns 10
ns 10
ms
6
7, 8
Capacitive Load for
Each Bus Line
I/O Capacitance C
Note 6: After this period, the first clock pulse is generated.
Note 7: A device must internally provide a hold time of at least 300ns for the SDA signal (referenced to the V
bridge the undefined region of the falling edge of SCL.
Note 8:The maximum t
Note 9: A fast mode device can be used in a standard mode system, but the requirement t
automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW
period of the SCL signal, it must output the next data bit to the SDA line t
released.
Note 10: C
– Total capacitance of one bus line in pF.
B
has only to be met if the device does not stretch the LOW period (t
HD:DAT
C
B
I/O
max + t
R
10 pF
LOW
SU:DAT
= 1000 + 250 = 1250ns before the SCL line is
SU:DAT
400 pF 10
) of the SCL signal.
>= to 250ns must then be met. This will
4 of 12
of the SCL signal) in order to
IHMIN
POWER-UP/POWER-DOWN CHARACTERISTICS
(TA = -40°C to +85°C)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
t
t
RPD
RPU
t
F
t
R
300
0
VCC Detect to RST (VCC Falling)
VCC Detect to RST (VCC Rising)
VCC Fall Time; V
VCC Rise Time; V
PF(MAX)
PF(MIN)
to V
to V
PF(MIN)
PF(MAX)
DS1672
10 µs
250 ms 11
ms
ms
Note 11: If the EOSC bit in the control register is set to logic 1, t
is equal to 250ms plus the startup time of the crystal oscillator.
RPU
Warning: Under no circumstances are negative undershoots, of any amplitude, allowed when device is in write
protection.
Figure 1. Timing Diagram
SDA
t
BUF
t
SCL
STOP
START
LOW
t
HD:STA
t
HD:DAT
t
HIGH
t
F
t
t
SU:DAT
SU:STA
REPEATED
START
t
HD:STA
t
SU:STO
Figure 2. Power-Up/Power-Down Timing
V
CC
V
PF(max)
V
PF(min)
t
F
t
PD
t
RPD
RST
INPUTS
OUTPUTS
RECOGNIZED
VALID
5 of 12
DON'T CARE
HIGH-Z
t
R
t
RPU
RECOGNIZED
VALID
PIN DESCRIPTIONS
PIN NAME FUNCTION
32.768kHz Crystal Pins. These signals are connections for a standard
1, 2 X1, X2
32.768kHz quartz crystal. The internal oscillator circuitry is designed for
operation with a crystal having a specified load capacitance (CL) of 6pF. (See
note)
Power Supply Input. Battery input for any standard 3V lithium cell or other
energy source. Battery voltage must be held between 1.3V and 3.63V for
3 V
BACKUP
proper operation. UL recognized to ensure against reverse charging current
when used in conjunction with a lithium battery (charger disabled). See
“Conditions of Acceptability” at www.maxim-ic.com/TechSupport/QA/ntrl.htm.
4 GND Ground. DC power is provided to the device on these pins.
DS1672
5 SDA
6 SCL
Serial-Data Input/Output. SDA is the input/output pin for the 2-wire serial
interface. The SDA pin is open drain and requires an external pullup resistor.
2-Wire Serial-Clock Input. SCL is used to synchronize data movement on the
serial interface and requires an external pullup resistor.
Reset Output. It functions as a microprocessor reset signal. This pin is an open
7
RST
drain output and requires an external pullup resistor.
8 VCC Power Supply. DC power is provided to the device on these pins.
Note: For more information about crystal selection and crystal layout considerations, refer to Application Note 58: Crystal Considerations with
Dallas Real-Time Clocks. The DS1672 can also be driven by an external 32.768kHz oscillator. In this configuration, the X1 pin is connected to
the external oscillator signal and the X2 pin is floated.
Figure 3. Recommended Layout for Crystal
6 of 12
DS1672
OPERATION
The block diagram in Figure 4 shows the main elements of the DS1672. As shown, communications to
and from the DS1672 occur serially over a 2-wire, bidirectional bus. The DS1672 operates as a slave
device on the serial bus. Access is obtained by implementing a START condition and providing a device
identification code followed by a register address. Subsequent registers can be accessed sequentially until
a STOP condition is executed.
Figure 4. Block Diagram
V
BACKUP
V
CC
GND
RST
SCL
SDA
X1
OSCILLATOR
AND DIVIDER
POWER
CONTROL
SERIAL BUS
INTERFACE
X2
32-BIT
COUNTER
(4 BYTES)
CONTROL
TRICKLE CHARGER
CONTROL
LOGIC
ADDRESS
REGISTER
Clock Accuracy
The accuracy of the clock is dependent upon the accuracy of the crystal and the accuracy of the match
between the capacitive load of the oscillator circuit and the capacitive load for which the crystal was
trimmed. Additional error will be added by crystal frequency drift caused by temperature shifts. External
circuit noise coupled into the oscillator circuit may result in the clock running fast. Refer to Application
Note 5: “Crystal Considerations with Dallas Real-Time Clocks” for detailed information.
Address Map
The counter is accessed by reading or writing the first 4 bytes of the DS1672 (00h–03h). The control
register and trickle charger are accessed by reading or writing the appropriate register bytes as illustrated
in Table 1. If the master continues to send or request more data after the address pointer has reached 05h,
the address pointer will wrap around to location 00h.
Table 1. Registers
ADDRESS B7 B6 B5 B4 B3 B2 B1 B0 FUNCTION
00h LSB Counter Byte 1
01h Counter Byte 2
02h Counter Byte 3
03h MSB Counter Byte 4
04h
EOSC
05h TCS TCS TCS TCS DS DS RS RS Trickle Charger
7 of 12
Control
DS1672
Data Retention Mode
The device is fully accessible and data can be written and ready only when VCC is greater than VPF.
However, when VCC falls below VPF, (point at which write protection occurs) the internal clock registers
are blocked from any access. If VPF is less than V
V
BACKUP
V
CC
when VCC drops below VPF. If VPF is greater than V
to V
BACKUP
when VCC drops below V
BACKUP
. The registers are maintained from the V
BACKUP
, the device power is switched from VCC to
BACKUP
, the device power is switched from
BACKUP
source
until VCC is returned to nominal levels.
Oscillator Control
The EOSC bit (bit 7 of the control register) controls the oscillator when in back-up mode. This bit when
set to logic 0 will start the oscillator. When this bit is set to a logic 1, the oscillator is stopped and the
DS1672 is placed into a low-power standby mode (I
powered by V
the oscillator is always on regardless of the status of the EOSC bit; however, the counter
CC,
BACKUP
) when in back-up mode. When the DS1672 is
is incremented only when EOSC is a logic 0.
Microprocessor Monitor
A temperature-compensated comparator circuit monitors the level of VCC. When VCC falls to the powerfail trip point, the RST signal (open drain) is pulled active. When VCC returns to nominal levels, the RST
signal is kept in the active state for 250ms (typically) to allow the power supply and microprocessor to
stabilize. Note, however, that if the EOSC bit is set to a logic 1 (to disable the oscillator during write
protection), the reset signal will be kept in an active state for 250ms plus the startup time of the oscillator.
Trickle Charger
The trickle charger is controlled by the trickle charge register. The simplified schematic of Figure 5
shows the basic components of the trickle charger. The trickle charge select (TCS) bit (bits 4–7) controls
the selection of the trickle charger. In order to prevent accidental enabling, only a pattern on 1010 will
enable the trickle charger. All other patterns will disable the trickle charger. The DS1672 powers up with
the trickle charger disabled. The diode select (DS) bits (bits 2, 3) select whether or not a diode is
connected between VCC and V
BACKUP
The RS bits (bits 0, 1) select whether a resistor is connected between VCC and V
of the resistor is. The resistor selected by the resistor select (RS) bits and the diode selected by the diode
select (DS) bits are as follows:
TCS TCS TCS TCS DS DS RS RS FUNCTION
XXXX 0 0XXDisabled
XXXX 1 1XXDisabled
XXXXXX 0 0Disabled
10100101
10101001
10100110
10101010
10100111
10101011
. If DS is 01, no diode is selected or if DS is 10, a diode is selected.
BACKUP
No diode, 250W resistor
One diode, 250W resistor
No diode, 2kW resistor
One diode, 2kW resistor
No diode, 4kW resistor
One diode, 4kW resistor
and what the value
8 of 12
DS1672
Diode and resistor selection is determined by the user according to the maximum current desired for
battery or super cap charging. The maximum charging current can be calculated as illustrated in the
following example. Assume that a system power supply of 3V is applied to VCC and a super cap is
connected to V
BACKUP
between VCC and V
. Also assume that the trickle charger has been enabled with a diode and resistor R2
BACKUP
. The maximum current I
I
= (5.0V - diode drop) / R1 » (5.0V - 0.7V) / 2kW » 2.2mA
MAX
would, therefore, be calculated as follows:
MAX
As the super cap changes, the voltage drop between VCC and V
charge current will decrease.
Figure 5. Programmable Trickle Charger
V
CC
1 OF 16 SELECT
NOTE: ONLY 1010 ENABLES
1 OF 2
SELECT
1 OF 3
SELECT
BACKUP
will decrease and, therefore, the
R1
250W
R2
2kW
R3
4kW
V
BACKUP
TCS TCS TCS TCS DS DS RS RS
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
TRICKLE CHARGE REGISTER
9 of 12
TCS = TRICKLE CHARGER SELECT
DS = DIODE SELECT
RS = RESISTOR SELECT
DS1672
2-Wire Serial Data Bus
The DS1672 supports a bidirectional 2-wire bus and data transmission protocol. A device that sends data
onto the bus is defined as a transmitter and a device receiving data as a receiver. The device that controls
the message is called a “master.” The devices that are controlled by the master are “slaves.” The bus must
be controlled by a master device that generates the serial clock (SCL), controls the bus access, and
generates the START and STOP conditions. The DS1672 operates as a slave on the 2-wire bus.
Connections to the b us are made via the open-drain I/O lines SDA and SCL.
The following bus protocol has been defined (Figure 6):
§ Data transfer may be initiated only when the bus is not busy.
§ During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in
the data line while the clock line is high will be interpreted as control signals.
Accordingly, the following bus conditions have been defined:
Bus not busy: Both data and clock lines remain HIGH.
Start data transfer: A change in the state of the data line from high to low, while the clock line is high,
defines a START condition.
Stop data transfer: A change in the state of the data line from low to high, while the clock line is high,
defines a STOP condition.
Data valid: The state of the data line represents valid data when, after a START condition, the data line
is stable for the duration of the high period of the clock signal. The data on the line must be changed
during the low period of the clock signal. There is one clock pulse per bit of data.
Each data transfer is initiated with a START condition and terminated with a STOP condition. The
number of data bytes transferred between the START and the STOP conditions is not limited, and is
determined by the master device. The information is transferred byte-wise and each receiver
acknowledges with a ninth bit. Within the 2-wire bus specifications a standard mode (100kHz clock rate)
and a fast mode (400kHz clock rate) are defined.
Acknowledge: Each receiving device, when addressed, is obliged to generate an acknowledge after the
reception of each byte. The master device must generate an extra clock pulse that is associated with this
acknowledge bit.
A device that acknowledges must pull down the SDA line during the acknowledge clock pulse in such a
way that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse. Of
course, setup and hold times must be taken into account. A master must signal an end of data to the slave
by not generating an acknowledge bit on the last byte that has been clocked out of the slave. In this case,
the slave must leave the data line HIGH to enable the master to generate the STOP condition.
10 of 12
DS1672
Figures 7 and 8 detail how data transfer is accomplished on the 2-wire bus. Depending upon the state of
the R/ W bit, two types of data transfer are possible:
1) Data transfer from a master transmitter to a slave receiver. The first byte transmitted by the
master is the slave address. Next follows a number of data bytes. The slave returns an acknowledge
bit after each received byte.
2) Data transfer from a slave transmitter to a master receiver. The first byte (the slave address) is
transmitted by the master. The slave then returns an acknowledge bit. Next follows a number of data
bytes transmitted by the slave to the master. The master returns an acknowledge bit after all received
bytes other than the last byte. At the end of the last received byte, a “not acknowledge” is returned.
The master device generates all of the serial clock pulses and the START and STOP conditions. A
transfer is ended with a STOP condition or with a repeated START condition. Since a repeated START
condition is also the beginning of the next serial transfer, the bus will not be released.
The DS1672 can operate in the following two modes:
1) Slave receiver mode (DS1672 write mode): Serial data and clock are received through SDA and
SCL. After each byte is received, an acknowledge bit is transmitted. START and STOP conditions are
recognized as the beginning and end of a serial transfer. Address recognition is performed by
hardware after reception of the slave address and direction bit (Figure 7). The slave address byte is the
first byte received after the START condition is generated by the master. The slave address byte
contains the 7-bit DS1672 address, which is 1101000, followed by the direction bit (R/ W ), which for
a write is a 0. After receiving and decoding the slave address byte the DS1672 outputs an
acknowledge on the SDA line. After the DS1672 acknowledges the slave address + write bit, the
master transmits a word address to the DS1672. This will set the register pointer on the DS1672, with
the DS1672 acknowledging the transfer. The master may then transmit zero or more bytes of data,
with the DS1672 acknowledging each byte received. The register pointer will increment after each
byte is transferred. The master will generate a stop condition to terminate the data write.
2) Slave transmitter mode (DS1672 read mode): The first byte is received and handled as in the slave
receiver mode. However, in this mode, the direction bit will indicate that the transfer direction is
reversed. Serial data is transmitted on SDA by the DS1672 while the serial clock is input on SCL.
START and STOP conditions are recognized as the beginning and end of a serial transfer (Figure 8).
The slave address byte is the first byte received after the START condition is generated by the master.
The slave address byte contains the 7-bit DS1672 address, which is 1101000, followed by the
direction bit (R/
W ), which for a read is a 1. After receiving and decoding the slave address byte the
DS1672 outputs an acknowledge on the SDA line. The DS1672 then begins to transmit data starting
with the register address pointed to by the register pointer. If the register pointer is not written to
before the initiation of a read mode the first address that is read is the last one stored in the register
pointer. The DS1672 must receive a “not acknowledge” to end a read.
11 of 12
Figure 6. Data Transfer on 2-Wire Serial Bus
SDA
MSB
slave address
R/W
direction
bit
acknowledgement
signal from receiver
acknowledgement
signal from receiver
DS1672
SCL
START
CONDITION
12 6789
ACK ACK
12 89
Figure 7. Data Write: Slave Receiver Mode
<Slave Addr ess> <W ord Addre ss (n)> <Da ta(n) <D ata(n+ 1)> <D ata(n +X)>
S - START
A - ACKNOWLEDGE
P - STOP
R/W - READ/WRITE OR DIRECTION BIT ADDRESS = D0H
<RW>
AXXXXXXXXA1101000S 0 XXXXXXXX A XXXXXXXX A XXXXXXXX A P
DATA TRANSFERRED
(X+1 BYTES + ACKNOWLEDGE)
Figure 8. Data Read: Slave Transmitter Mode
3 - 8
repeated if more bytes
are transferred
STOP CONDITION
OR
REPEATED
START CONDITION
<Slave Addr ess> <D ata(n )> <D ata(n+1 ) <Da ta(n+2 )> <D ata(n+X)>
<RW>
AXXXXXXXXA1101000S 1 XXXXXXXX A XXXXXXXX A XXXXXXXX A P
S - START
A - ACKNOWLEDGE
P - STOP
A - NOT ACKNOWLEDGE
(X+1 BYTES + ACKNOWLEDGE); NOTE: LAST DATA BYTE IS
FOLLOWED BY A NOT ACKNOWLEDGE (A) SIGNAL)
DATA TRANSFERRED
R/W - READ/WRITE OR DIRECTION BIT ADDRESS = D1H
12 of 12
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