Rainbow Electronics DS1646P User Manual

www.dalsemi.com

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DS1646/DS1646P

Nonvolatile Timekeeping RAM

FEATURES

 Integrates NV SRAM, real time clock,

crystal, power-fail control circuit and lithium
energy source

 Clock registers are accessed identically to the

static RAM. These registers are resident in
the eight top RAM locations

 Totally nonvolatile with over 10 years of

operation in the absence of power

 BCD coded year, month, date, day, hours,

minutes, and seconds with leap year
compensation valid up to 2100

 Power-fail write protection allows for ±10%

VCC power supply tolerance

 DS1646 only (DIP Module)

− Standard JEDEC bytewide 128k x 8 RAM

pinout

 DS1646P only (PowerCap® Module Board)

− Surface mountable package for direct

connection to PowerCap containing battery
and crystal

− Replaceable battery (PowerCap)

− Power-fail output

− Pin-for-pin compatible with other densities

of DS164XP Timekeeping RAM

ORDERING INFORMATION

DS1646 32-pin DIP module

*DS1646P 34-pin PowerCap Module

Board

PIN ASSIGNMENT

NC
A15
A16

PFO

V

CC

WE

OE

CE

DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0

GND

NC

A16
A14
A12

DQ0
DQ1
DQ2

GND

34-Pin PowerCap Module Board

(Uses DS9034PCX PowerCap)

1
2

3
4

A7

5

A6

6

A5

7

A4

8

A3

9

A2

10

A1

11
12

A0

13
14
15
16

32-Pin Encapsulated Package

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15

X1 GND V
16
17

BAT

32
31

30
29

28
27

26
25

24
23

22
21

20
19
18
17

X2

V

CC

15
NC
WE

11
OE

10
CE

DQ7
DQ6
DQ5
DQ4
DQ3

34
33
32
31
30
29
28

27
26
25
24
23
22
21
20
19
18

NC
NC

14
12
10
8

5
3

2
1
0

*DS9034PCX Power Cap

(Required; must be ordered

separately)

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DS1646/DS1646P

PIN DESCRIPTION

A0-A16 - Address Input

CE - Chip Enable
OE - Output Enable

WE - Write Enable

- +5V

V

CC

GND - Ground

DQ0-DQ7 - Data Input/Output
NC - No Connection

PFO - Power-fail Output

(DS1646P only)
X1, X2 - Crystal Connection
V

- Battery Connection

BAT

DESCRIPTION

The DS1646 is a 128k x 8 nonvolatile static RAM with a full-function real time clock, which are both
accessible in a byte-wide format. The nonvolatile timekeeping RAM is functionally equivalent to any
JEDEC standard 128k x 8 SRAM. The device can also be easily substituted for ROM, EPROM and
EEPROM, providing read/write nonvolatility and the addition of the real time clock function. The real
time clock information resides in the eight uppermost RAM locations. The RTC registers contain year,
month, date, day, hours, minutes, and seconds data in 24-hour BCD format. Corrections for the day o f the
month and leap year are made automatically. The RTC clock registers are double-buffered to avoid access
of incorrect data that can occur during clock update cycles. The double-buffered system also prevents
time loss as the timekeeping countdown continues unabated by access to time register data. The DS1646
also contains its own power-fail circuitry, which deselects the device when the VCC supply is in an out-of­tolerance condition. This feature prevents loss of data from unpredictable system operation brought on b y
low VCC as errant access and update cycles are avoided.

PACKAGES

The DS1646 is available in two packages: 32-pin DIP and 34-pin PowerCap module. The 32-pin DIP
style module integrates the crystal, lithium energy source, and silicon all in one package. The 34-pin
PowerCap Module Board is designed with contacts for connection to a separate PowerC ap (DS9034PCX)
that contains the crystal and battery. This design allows the PowerCap to be mounted on top of the
DS1646P after the completion of the surface mount process. Mounting the PowerCap aft er the surface
mount process prevents damage to the crystal and battery due to the hi gh tempe ratur es required for solde r
reflow. The PowerCap is keyed to prevent reverse insertion. The PowerCap Module Board and PowerCap
are ordered separately and shipped in separate containers. The part number for the PowerCap is
DS9034PCX.

CLOCK OPERATIONS - READING THE CLOCK

While the double-buffered register structure reduces the chanc e of r eadin g incor rect d ata, internal updates
to the DS1646 clock registers should be halted before clock data is read to prevent reading of data in
transition. However, halting the internal clock register updating process does not affect clock accuracy.
Updating is halted when a 1 is written into the read bit, the 7th most significant bit in the control register.
As long as 1 remains in that position, updating is halted. After a halt is issued, the registers reflect the
count, that is day, date, and time that was present at the moment the halt command was issued. However,
the internal clock registers of the double-buffered system continue to update so that clock accuracy is not
affected by the access of data. All of the DS1646 registers are updated simultaneously after the clock
status is reset. Updating is within a second after the read bit is written to 0.

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BLOCK DIAGRAM DS1646 Figure 1

TRUTH TABLE DS1646 Table 1

V

CC

5V ± 10%

<4.5V >V

<V

BAT

BAT

CE OE WE

V

IH

X X DESELECT HIGH-Z STANDBY

X X X DESELECT HIGH-Z STANDBY
V
V
V

IL
IL
IL

XVILWRITE DATA IN ACTIVE
V
V

IL
IH

V
V

IH
IH

X X X DESELECT HIGH-Z CMOS STANDBY
X X X DESELECT HIGH-Z DATA RETENTION

DS1646/DS1646P

MODE DQ POWER

READ DATA OUT ACTIVE
READ HIGH-Z ACTIVE

MODE

SETTING THE CLOCK

The MSB Bit, B7, of the control register is the write bit. Setting the write bit to a 1, like the read bit halts
updates to the DS1646 registers. The user can then load them with the correct day, date and time data in
24-hour BCD format. Resetting the write bit to a 0 then transfers those values to the actual clock counters
and allows normal operation to resume.

STOPPING AND STARTING THE CLOCK OSCILLATOR

The clock oscillator may be stopped at any time. To increase the shelf life, the oscillator can be turned off
to minimize current drain from the battery. The

OSC bit is the MSB for the second’s registers. Setting it

to a 1 stops the oscillator.

FREQUENCY TEST BIT

Bit 6 of the day byte is the frequency test bit. When the frequency test bit is set to logic 1 and
the oscillator is running, the LSB of the second’s register will toggle at 512 Hz. When the seconds
register is being read, the DQ0 line will toggle at the 512 Hz frequency as long as conditions for access

remain valid (i.e.,

CE low, OE low, and address for seconds register remain valid and stable).

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DS1646/DS1646P

CLOCK ACCURACY (DIP MODULE)

The DS1646 is guaranteed to keep time accuracy to within ±1 minute per month at 25°C. The RTC is
calibrated at the factory by Dallas Semiconductor using nonvolatile tuning elements, and does not require
additional calibration. For this reason, methods of field clock calibration are not available and not
necessary. Clock accuracy is also effected by the electrical environment and caution should be taken to
place the RTC in the lowest level EMI section of the PCB layout. For additional information please see
application note 58.

CLOCK ACCURACY (POWERCAP MODULE)

The DS1646 and DS9034PCX are each individually tested for accuracy. Once mounted together, the
module will typically keep time accuracy to within ±1.53 minutes per month (35 ppm) at 25°C. Clock
accuracy is also effected by the electrical environment and caution should be taken to place the RTC in
the lowest level EMI section of the PCB layout. For additional information please see application note

58.

1646 REGISTER MAP - BANK1 Table 2

ADDRESS

B

7

B

6

B

5

1FFFF - - - - - - - - YEAR 00-99

1FFFE X X X - - - - - MONTH 01-12
1FFFD X X - - - - - - DATE 01-31
1FFFC X FT X X X - - - DAY 01-07
1FFFB X X - - - - - - HOUR 00-23
1FFFA X - - - - - - - MINUTES 00-59

1FFF9

OSC

-------

1FFF8WRXXXXXXCONTROLA

OSC = STOP BIT

W = WRITE BIT X = UNUSED

DATA

B

4

B

3

B

2

B

1

B

0

FUNCTION

SECONDS 00-59

R = READ BIT FT = FREQUENCY TEST

NOTE:

All indicated “X” bits are not dedicated to any particular function and can be used as normal RAM bits.

RETRIEVING DATA FROM RAM OR CLOCK

The DS1646 is in the read mode whenever WE (write enable) is high; CE (chip enable) is low. The
device architecture allows ripple-through access to an y of the address locations in the NVSRAM. Valid

data will be available at the DQ pins within tAA after the last address input is stable, providing that the CE
and OE access times and states are satisfied. If CE or OE access times are not met, valid data will be

available at the latter of chip -enable access (t
data input/output pins (DQ) is controlled by

) or at output enable access time (t

CEA

CE and OE . If the outputs are activated befor e t

lines are driven to an intermediate state until tAA. If the address inputs are changed while CE and OE
remain valid, output data will remain valid for output data hold time (tOH) but will then go indeterminate
until the next address access.

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). The state of the

OEA

, the data

AA