Rainbow Electronics DS1558Y User Manual

Note:

Some revisions of this device may inco

rporate deviations from published specifications known as errata. Multiple revisions of any device

DS1558

Watchdog Clock with

NV RAM Control

www.

maxim

-ic.com

www.maxim

ic.com

A18

A16

A12A6A4A3A2A1A5A7A14

N.C.

VCCO

1 2 3 4 5 6 7 8 10 12 35 36

VCC N.C.

A16 GND RST NC N.C. DQ0

DQ1DQ2

DQ6

VBAT1

IRQ/FT

A8 OE

A10 CE

X1 GND VBAT

A15 A13 OER A9 A11 34 33 32 31 30 29 28 27 26 25

24 23 22 21 20 19 18 17 16 15 14 13

11 9

484746454443424140393837CER

DQ7

DQ5

DQ4

DQ3

GND

X2 N.C.

FEATURES

§ Integrated real-time clock (RTC), power-fail control circuit, and NV RAM controller

§ Clock registers are accessed identically to the static RAM; these registers are resident in the 16 top RAM locations

§ Century register

§ Greater than 10 ye ars of timekeeping and data

retention in the absence of power with small lithium coin cell(s) and low-leakage SRAM

§ Precision power-on reset

§ Programmable watchdog timer and RTC

alarm

§ BCD-coded year, month, date, day, hours, minutes, and seconds with automatic leapyear compensation valid up to the year 2100

§ Battery voltage -level indicator flag

§ Power-fail write protection allows for ±10%

VCC power-supply tolerance

§ Underwriters Laboratory (UL) recognized

ORDERING INFORMATION

PART

PIN-

PACKAGE

(V)

DS1558Y 48 TQFP 5 DS1558B DS1558W 48 TQFP 3.3 DS1558D

TOP

MARK

PIN ASSIGNMENT (Top View)

DS1558

48-Pin TQFP

Package Dimension Information

http://www.maxim-ic.com/TechSupport/DallasPackInfo.htm

PIN DESCRIPTION

A0–A18 - Address Input DQ0–DQ7 - Data Input/Outputs

IRQ\FT - Interrupt, Frequency-Test

Output (Open Drain)

RST - Power-On Reset Output

(Open Drain)

CE - Chip-Enable Input

CER - Chip-Enable RAM

OE - Output-Enable Input

OER - Output-Enable RAM

WE - Write Enable

- Power-Supply Input

- VCC Out to RAM

CCO

GND - Ground N.C. - No Connection X1, X2 - Crystal Connection V

BAT1

BAT2

may be simultaneously available through various sales channels. For information about device errata, click here: http://www.maxim -ic.com/errata.

1 of 18 072402

- +3V Battery Input

TYPICAL OPERATING CIRCUIT

DS1558

DESCRIPTION

The DS1558 is a full function, year 2000-compliant (Y2KC), real-time clock/calendar with an RTC alarm, watchdog timer, power-on reset, battery monitor, and NV SRAM controller. User access to all registers within the DS1558 is accomplished with a byte-wide interface as shown in Figure 1. The RTC registers contain century, year, month, date, day, hours, minutes, and seconds data in 24-hour BCD format. Corrections for day of month and leap year are made automatically.

The DS1558 maps the RTC registers into the SRAM address space and constantly monitors A0–A18.

When any of the upper 16 address locations are accessed, the DS1558 inhibits CER and OER to the SRAM, and redirects reads and writes to the RTC registers within the DS1558. The DS1558 can be used with SRAMs up to 524,272 addresses. Smaller SRAMs can be used, provided that the unused upper address lines on the DS1558 are connected to VCC.

The RTC registers are double-buffered into an internal and external set. The user has direct access to the external set. Clock/calendar updates to the external set of registers can be disabled and enabled to allow the user to access static data. Assuming the internal oscillator is turned on, the internal set of registers is continuously updated; this occurs regardless of external register settings to guarantee that accurate RTC information is always maintained.

The DS1558 has interrupt (

The

IRQ /FT interrupt output can be used to generate an external interrupt when the RTC register values

IRQ /FT) and reset ( RST ) outputs that can be used to control CPU activity.

match user-programmed alarm values. The interrupt is always available while the device is powered from the system supply, and it can be programmed to occur when in the battery-backed state to serve as a system wake-up. The

IRQ /FT output can also be used as a CPU watchdog timer. CPU activity is

monitored and an interrupt or reset output are activated if the correct activity is not detected within

2 of 18

DS1558

programmed limits. The DS1558 power-on reset can be used to detect a system power-down or failure and hold the CPU in a safe reset state until normal power returns and stabilizes; the RST output is used for this function.

The DS1558 also contains its own power-fail circuitry, which automatically protects the data in the clock and SRAM against out-of-tolerance V enters an out-of-tolerance condition. When V

conditions by inhibiting the CE input when the VCC supply

CCI

goes below the level of V

CCI

, the external battery is

BAT

switched on to supply energy to the clock and the external SRAM. This feature provides a high degree of data security during unpredictable system operation brought on by low VCC levels.

Figure 1. BLOCK DIAGRAM

Note: Any unused upper address pins must be connected to VCC to properly address the RTC.

SIGNAL DESCRIPTIONS

A0–A18 – Address inputs for address decode. The DS1558 uses the address inputs to determine whether or not a read or write cycle should be directed to the attached SRAM or to the RTC registers.

DQ0–DQ7 – Data input/output pins for the RTC registers.

IRQ /FT – This pin is used to output the alarm interrupt or the frequency test signal. It is open drain and

requires an external pullup resistor.

3 of 18

DS1558

RST – This pin is an output used to signal that V

is out of tolerance. On power-up, RST is held low for

a period of time to allow the system to stabilize. The RTC and SRAM are not accessible while RST is active. This pin is open drain and requires an external pullup resistor.

CE – Chip-enable input that is used to access the RTC and the external SRAM.

CER – Chip-enable RAM output. CE is passed through to CER , with an added propagation delay. When

the signals on A0–A18 match an RTC address,

CER is held high, disabling the SRAM. If OE is also low,

the RTC outputs data on DQ0–DQ7.

OE – Output-enable input that is used to access the RTC and the external SRAM.

OER – Output-enable RAM output. OE is passed through to OER , with an added propagation delay.

When the signals on A0–A18 match an RTC address, CER is held high, disabling the SRAM. If CE is also low, the RTC outputs data on DQ0–DQ7.

WE – Write-enable input that is used to write data to the RTC registers.

VCC, GND – DC power is provided to the device on these pins. VCC is the +5V input. When 5V (or 3.3V for the 3.3V version) is applied within normal limits, the device is fully accessible and data can be written and read. Reads and writes are inhibited when a 3V battery is connected to the device and VCC is VTP. However, the timekeeping function continues unaffected by the lower input voltage. As VCC falls below V

, the RAM and RTC are switched over to the external power supply (nominal 3.0V DC) at V

BAT

– VCC output to RAM. While VCC is above V

CCO

VCC is below the battery level, the SRAM is powered by one of the V

, the external SRAM is powered by VCC. When

BAT

inputs.

BAT

N.C. – No internal connection.

X1, X2 – Connections for a standard 32.768kHz quartz crystal. The internal oscillator circuitry is

designed for operation with a crystal having a specified load capacitance (C

) of 6pF. For more

information about crystal selection and crystal layout considerations, refer to Application Note 58 “Crystal Considerations with Dallas Real-Time Clocks.” The DS1558 can also be driven by an external

32.768kHz oscillator. In this configuration, the X1 pin is connected to the external oscillator signal and the X2 pin is floated.

BAT1

, V

– Battery inputs for any standard 3V lithium cell or other energy source. Battery voltage

BAT2

must be held between 2.5V and 3.7V for proper operation. UL recognized to ensure against reverse charging current when used with a lithium battery. If only one battery is used, it should be attached to V

BAT1

, and V

should be grounded.

BAT2

See “Conditions of Acceptability” at http://www.maxim-ic.com/TechSupport/QA/ntrl.htm.

4 of 18

Table 1. OPERATING MODES

DS1558

VCC > V

VSO < VCC < V

VCC < VSO < V

CE OE WE

X X X High-Z Deselect CMOS Standby

X X X High-Z Data Retention Battery Current

X X High-Z Deselect Standby

XVILD V V

V V

DQ0–DQ7 MODE POWER

Write Active

Read Active

OUT

High-Z Read Active

DATA READ MODE

The DS1558 is in the read mode whenever CE is low and WE is high. The device architecture allows ripple-through access to any valid address location. Valid data is available at the DQ pins within t

the last address input is stable, provided that times are not met, valid data is available at the latter of chip-enable access (t

access time (t

). The state of the data input/output pins (DQ) is controlled by CE and OE . If the

OEA

CE and OE access times are satisfied. If CE or OE access

) or at output-enable

CEA

after

outputs are activated before tAA, the data lines are driven to an intermediate state until tAA. If the address inputs are changed while CE and OE remain valid, output data remains valid for output-data hold time

(tOH), but then goes indeterminate until the next address access.

DATA WRITE MODE

The DS1558 is in the write mode whenever WE and CE are in their active state. The start of a write is referenced to the latter occurring transition of WE or CE . The addresses must be held valid throughout the cycle. CE and WE must return inactive for a minimum of tWR prior to the initiation of a subsequent

read or write cycle. Data in must be valid tDS prior to the end of the write and remain valid for t afterward. In a typical application, the OE signal is high during a write cycle. However, OE can be active provided that care is taken with the data bus to avoid bus contention. If OE is low prior to WE

transitioning low, the data bus can become active with read data defined by the address inputs. A low transition on WE then disables the outputs t

after WE goes active.

WEZ

DATA RETENTION MODE

The 5V device is fully accessible and data can be written and read only when VCC is greater than VPF. However, when VCC is below the power-fail point VPF (point at which write protection occurs), the internal clock registers and SRAM are blocked from any access. When VCC falls below the battery switch point V operation and SRAM data are maintained from the battery until VCC is returned to nominal levels.

The 3.3V device is fully accessible and data can be written and read only when V When VCC falls below VPF, access to the device is inhibited. If VPF is less than VSO, the device power is switched from V than VSO, the device power is switched from VCC to the internal backup lithium battery when VCC drops below V nominal levels.

All control, data, and address signals must be powered down when V

(battery supply level), device power is switched from the VCC pin to the backup battery. RTC

is greater than VPF.

to the internal backup lithium battery when VCC drops below VPF. If VPF is greater

. RTC operation and SRAM data are maintained from the battery until VCC is returned to

is powered down.

5 of 18

DS1558

BATTERY LONGIVITY

The battery lifetime is dependent on the RAM battery standby current and the DS1558 internal clock oscillator current. The total battery current is I

OSC

+ I

. When VCC is above VPF, I

CCO

current is less than

BAT

50nA. The DS1558 has an internal circuit to prevent battery charging. No external protection components are required, and none should be used. The DS1558 has two battery pins that operate independently; the DS1558 selects the higher of the two inputs. If only one battery is used, the battery should be attached to V

BAT1

, and V

should be grounded.

BAT2

INTERNAL BATTERY MONITOR

The DS1558 constantly monitors the battery voltage of the internal battery. The battery-low flag (BLF) bit of the flags register (B4 of 7FFF0h) is not writable and should always be a 0 when read. If a 1 is ever present, both battery inputs are below 1.8V and both the contents of the RTC and RAM are questionable.

POWER-ON RESET

A temperature-compensated comparator circuit monitors the level of VCC. When VCC falls to the powerfail trip point, the

signal continues to be pulled low for a period of 40ms to 200ms. The power-on reset function is independent of the RTC oscillator and thus is operational whether or not the oscillator is enabled.

RST signal (open drain) is pulled low. When V

returns to nominal levels, the RST

6 of 18

+ 12 hidden pages