Rainbow Electronics DS14287 User Manual

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DS14285/DS14287

Real Time Clock with NV RAM Control

FEATURES

 Direct replacement for IBM AT computer

clock/calendar

 Functionally compatible with the

DS1285/DS1287

 Available as chip (DS14285, DS14285S, or

DS14285Q) or stand-alone module with embedded lithium battery and crystal (DS14287)

 Automatic backup supply and write

protection to make external SRAM nonvolatile

 Counts seconds, minutes, hours, days, day of

the week, date, month, and year with leap year compensation valid up to 2100

 Binary or BCD representation of time,

calendar, and alarm

 12- or 24-hour clock with AM and PM in

12-hour mode

 Daylight Savings Time option  Multiplex bus for pin efficiency  Interfaced with software as 128 RAM

locations – 14 bytes of clock and control registers – 114 bytes of general purpose RAM

 Programmable square wave output signal  Bus-compatible interrupt signals (

IRQ )

 Three interrupts are separately software-

maskable and testable – Time-of-day alarm once/second to

once/day

– Periodic rates from 122 µs to 500 ms – End of clock update cycle

 Optional industrial temperature version

available DS14285 DIP, SOIC, and PLCC

PIN ASSIGNMENT

GND

AD0 AD1 AD2 AD3 AD4 AD5

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NC AD0 AD1 AD2 AD3

AD4 AD5 AD6 AD7

GND

AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7

3 4

5 6

7 8

9 10

11 12

DS14285 24-Pin DIP

DS14285S 24-Pin SOIC

X2X1MOT

VCCO

4 3 2 1 28 27 26

5 6 7 8 9 10 11

12 13 14 15 16 17 18

AD6NCAD7

GND

DS14285Q 28-Pin PLCC

1 2

3 4

5 6

7 8

9 10

11 12

24 23

22 21

20 19

18 17

16 15

14 13

VCC

SQW

24 23

22 21

20 19

18 17

16 15

14 13

CE0

25 24 23 22 21 20 19

V SQW

CEO

CEI V

BAT

IRQ RESET DS GND R/W

CEI V IRQ RESET DS GND R/W

BAT

W CEO CEI NC IRQ RESET DS NC R/W

DS14287 24-Pin

Encapsulated Package

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ORDERING INFORMATION

DS14285 RTC Chip; 24-pin DIP DS14285N RTC Chip; 24-pin DIP; Industrial Temp Range DS14285S RTC Chip; 24-pin SOIC DS14285SN RTC Chip; 24-pin SOIC; Industrial Temp Range DS14285Q RTC Chip; 28-pin PLCC DS14285QN RTC Chip; 28-pin PLCC; Industrial Temp Range DS14287 RTC Module; 24-pin DIP

PIN DESCRIPTION

AD0-AD7 - Multiplexed Address/Data Bus NC - No Connection MOT - Bus Type Select (DS14285Q only)

CS - Chip Select

AS - Address Strobe R/W - Read/Write Input

DS - Data Strobe

RESET - Reset Input

DS14285/DS14287

IRQ - Interrupt Request Output

SQW - Square Wave Output VCC - +5V Supply GND - Ground V

- RAM Power Supply Output

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CEI - RAM Chip Enable In CEO - RAM Chip Enable Out

X1, X2 - 32.768 kHz Crystal Connections V

- +3V Battery Input

BAT

DESCRIPTION

The DS14285/DS14287 Real Time Clock with NVRAM Control provides the industry standard DS1287 clock function with the additional feature of providing nonvolatile control for an external SRAM. Functions include a nonvolatile time-of-day clock, alarm, 100-year calendar, programmable interrupt, square wave generator, and 114 bytes of nonvolatile static RAM. For the DS14287 a lithium energy source, quartz crystal, and write protection circuitry are contained within a 24-pin dual in-line package. The DS14285 requires an external quartz crystal connected to the X1 and X2 pins as well as an external energy source connected to the V to the DS14285 via pins 1 and 2 (X1, X2). The crystal selected for use should have a specified load capacitance (C

) of 6 pF. For more information on crystal selection and crystal layout considerations,

please consult Application Note 58, “Crystal Considerations with Dallas Real-time Clocks.”

pin. A standard 32.768 kHz quartz crystal can be directly connected

BAT

The DS14285/DS14287 uses its backup energy source and battery-backup controller to make a standard CMOS static RAM nonvolatile during power-fail conditions. During power fail, the DS14285/DS14287 automatically write-protects the external SRAM and provides a V

output sourced from its internal

battery.

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DS14285/DS14287

For the DS14287 the internal lithium cell is electrically isolated from the clock and memory when shipped from the factory. This isolation is removed after the first application of V

cell to provide data retention to the clock, internal RAM, V

and CEO on subsequent powe r-downs.

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allowing the lithium

CC,

Care must be taken after this isolation has been broken to avoid inadvertently discharging the lithium cell through the V

and CEO pins.

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OPERATION

The block diagram in Figure 1 shows the pin connections with the major internal functions of the DS14285/DS14287. The following paragraphs describe the function of each pin.

SIGNAL DESCRIPTIONS

GND, V

SQW (Square Wave Output) - The SQW pin can output a signal from one of 13 taps provided by the 15

internal divider stages of the real time clock. The frequency of the SQW pin can be changed by programming Register A as shown in Table 1. The SQW signal can be turned on and off using the SQWE bit in Register B. The SQW signal is not available when V

AD0-AD7 (Multiplexed Bi-directional Address/Data Bus) - Multiplexed buses save pins because address information and data information time-share the same signal paths. The addresses are present during the first portion of the bus cycle and the same pins and signal paths are used for data in the second portion of the cycle. Address/data multiplexing does not slow the access time of the DS14285/DS14287 since the bus change from address to data occurs during the internal RAM access time. Addresses must be valid prior to the falling edge of AS/ALE, at which time the DS14285/DS14287 latches the address from

AD0 to AD6. Valid write data must be present and held stable during the latter portion of the DS or WR pulses. In a read cycle the DS14285/DS14287 outputs 8 bits of data during the latter portion of the DS or

RD pulses. The read c ycle is terminated and the bus returns to a high impedance stat e as DS transiti ons

low in the case of Motorola timing or as RD transitions high in the case of Intel timing.

- DC power is provided to the device on these pins. VCC is the +5 volt input.

is less than 4.25 volts typical.

MOT (Mode Select) - The MOT pin offers the flexibility to choose between to bus types. When connected to V

, Motorola bus timing is selected. When connected to GND or left disconnected, Intel

bus timing is selected. The pin has an internal pull-down resistance of approximately 20 KΩ. This pin is on the DS14285Q only.

AS (Address Strobe Input) - A positive going address strobe pulse serves to demultiplex the bus. The falling edge of AS/ALE causes the address to be latched within the DS14285/DS14287.

DS (Data Strobe or Read Input) - For the DS14285Q the DS/ depending on the level of the MOT pin. When the MOT pin is connected to V

RD pin has two modes of operation

, Motorola bus timing is

selected. In this mode DS is a positive pulse during the latter portion of the bus cycle and is called Data Strobe. During read cycles, DS signifies the time that the DS14285Q is to drive the bidirectional bus. In write cycles the trailing edge of DS causes the DS14285Q to latch the written data. When the MOT pin is

connected to GND, Intel bus timing is selected. In this mode the DS pin is called Read(RD ).RD identifies the time period when the DS14285Q drives the bus with read data. The RD signal is the same definition as the Output Enable (

OE ) signal on a typical memory.

The DS14285, DS14285S and DS14287 do not have a MOT pin and therefore operate only in Intel bus timing mode.

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DS14285/DS14287

R/W (Read/Write Input) - The R/ W pin also has two modes of operation. When the MOT pin is connected to VCC for Motorola timing, R/W is at a level which indicates wh ether the current cycle is a read or write. A read cycle is indicated with a high level on R/ W while DS is high. A write cycle is indicated when R/ W is low during DS.

When the MOT pin is connected to GND for Intel timing, the R/W signal i s an active low signal call ed

WR . In this mode the R/ W pin has the same meaning as the Write Enable signal ( WE ) on generic

RAMs.

CS (Chip Select Input) - The Chip Select signal must be asserted low for a bus cycle in the

DS14285/DS14287 to be accessed. CS must be kept in the active state during DS for Motorola timing and during RD and WR for Intel timing. Bus cycles which take place without asserting CS will latch

addresses but no access will occur. When VCC is below 4.25 volts, the DS14285/DS14287 internally inhibits access cycles by internally disabling the CS input. This action protects both the real time clock

data and RAM data during power outages.

IRQ (Interrupt Request Output) - The IRQ pin is an active low output of the DS14285/DS14287 that

can be used as an interrupt input to a processor. The IRQ output remains low as long as the status bit causing the interrupt is present and the corresponding interrupt-enable bit is set. To clear the IRQ pin the processor program normally reads the C register. The RESET pin also clears pending interrupts.

When no interrupt conditions are present, the IRQ level is in the high impedance state. Multiple interrupting devices can be connected to an IRQ bus. The IRQ bus is an open drain output and requires an

external pull-up resistor.

RESET (Reset Input) - The RESET pin has no effect on the clock, calendar, or RAM. On power-up the

RESET pin can be held low for a time in order to allow the power supply to stabilize. The amount of time

RESET is held low is dependent on the application. However, if RESET is used on power-up, the

that time RESET is low should exceed 200 ms to make sure that the internal timer that controls the DS14285/DS14287 on power-up has timed out. When

RESET is low and V

is above 4.25 volts, the

following occurs:

A. Periodic Interrupt Enable (PEI) bit is cleared to 0. B. Alarm Interrupt Enable (AIE) bit is cleared to 0. C. Update Ended Interrupt Flag (UF) bit is cleared to 0. D. Interrupt Request Status Flag (IRQF) bit is cleared to 0. E. Periodic Interrupt Flag (PF) bit is cleared to 0.

F. The device is not accessible until RESET is returned high. G. Alarm Interrupt Flag (AF) bit is cleared to 0.

H. IRQ pin is in the high impedance state. I. Square Wave Output Enable (SQWE) bit is cleared to 0.

J. Update Ended Interrupt Enable (UIE) is cleared to 0. K. CEO is driven high.

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DS14285/DS14287

In a typical application RESET can be connected to VCC. This connection will allow the DS14287 to go in and out of power fail without affecting any of the control registers.

CEI (External RAM Chip Enable Input, active low) - CEI should be driven low to enable the external

RAM. CEI is internally pulled up with a 50kΩ resistor.

CEO (External RAM Chip Enable Output, active low) - When V

CEO will reflect CEI provided the RESET is at a logic high. When V CEO will be forced to an inactive level regardless of CEI .

(External RAM Power Supply Output) - V

CCO

provides the higher of VCC or V

CCO

is greater than 4.25 volts (typical),

is less than 4.25 volts (typical),

through an

BAT

internal switch to power an external RAM.

DS14285 Only

X1, X2 - Connections for a standard 32.768 kHz quartz crystal. The internal oscillator circuitry is designed for operation with a crystal having a specified load capacitance (CL) of 6 pF. The crystal is connected directly to the X1 and X2 pins. Ther e is no need for external cap acitors or resistors. Note: X1 and X2 are very high impedance nodes. It is recommended that the y and the crystal be guard–ringed with ground and that high frequency signals be kept away from the crystal area. For more information on crystal selection and crystal layout considerations, please consult Application Note 58, “Crystal Considerations with Dallas Real Time Clocks.”

– Battery input for any standard 3-volt lithium cell or other energy source. Se e the Power -Up/Down

BAT

section for considerations in selecting the size of the external energy source

The battery should be connected directly to the V battery to the VBAT pin. Furthermore, a diode is not necessary because reverse charging current protection circuitry is provided internal to the device and has passed the requirements of Underwriters Laboratories for UL listing.

pin. A diode must not be placed in series with t he

BAT

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DS14285/DS14287 BLOCK DIAGRAM Figure 1

DS14285/DS14287

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DS14285/DS14287

POWER-DOWN/POWER-UP CONSIDERATIONS

The real time clock function will continue to operate and all of the RAM, time, calendar, and alarm memory locations remain nonvolatile regardless of the level of the V DS14285/DS14287 and reaches a level of greater than 4.25 volts (typical), the devi ce becomes a ccessible after 200 ms, provided that the oscillator is running and the oscillator countdown chain is not in res et (see Register A). This time period allows the system to stabilize after power is applied. When V

4.25 volts (typical), the chip select input is internally forced to an inactive level regardless of the v alue of

CS at the input pin. The DS14285/DS14287 is, therefore, write-protected. When the DS14285/DS14287

is in a write-protected state, all inputs are ignored and all outputs are in a high impedance state. When V

falls below a level of approximately 3 volts, the external VCC supply is switched off and an internal

lithium energy source supplies power to the Real-time Clock and the RAM memory.

input. When VCC is applied to the

falls below

An external SRAM can be made nonvolatile by using the V

and SRAM chip enable pins (see Figu re

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1). Nonvolatile control of the external SRAM is analogous to that of the real time clock registers. When V

slews down during a power fail, CEO is driven to an inactive level regardless CEI. This write

protection occurs when V

is less than 4.25 volts (typical).

During power up, when VCC reaches a level of greater than 4.25 volts (typical), CEO will reflect CEI after 200 ms. During power-valid operation, the CEI input is passed to the CEO output with a

propagation delay of less than 10 ns.

When V V

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internal lithium cell through the V powered by V

When the device is in battery backup mode, the ener gy source connected to the V

is above a level of approximatel y 3V, the external SRAM will be powered by VCC through the

pin. When VCC is below a level of approximately 3V, the external SRAM will be powered by the

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or the internal lithium cell.

pin. An internal compar ator and switch determine whether V

pin in the case of

BAT

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the DS14285, or the internal lithium cell in the case of the DS14287 can power an external SRAM for an extended period of time. The amount of time that the lithium cell can supply power to the external SRAM is a function of the data retention current of the SRAM. The capacity of the lithium cell that is encapsulated within the DS14287 module is 130 mAh. If an SRAM with a data retention current of less than 1 µA is used and the oscillator current is 300 nA (typical), the cumulative data retention time is calculated at more than 11 years.

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DS14285/DS14287

RTC ADDRESS MAP

The address map of the DS14285/DS14287 is shown in Figure 2. The address map consists of 114 bytes of user RAM, 10 bytes of RAM that contain the RTC time, calendar, and alarm data, and 4 bytes which are used for control and status. All 128 bytes can be directly written or read except for the following:

1. Registers C and D are read-only.

2. Bit 7 of Register A is read-only.

3. The high order bit of the seconds byte is read-only.

The contents of four registers (A,B,C, and D) are described in the “Registers” section.

DS14285/DS14287 ADDRESS MAP Figure 2

TIM E , C ALE N DAR AN D ALARM LOC AT I O N S

The time and calendar information is obtained by reading the appropriate memory bytes. The time, calendar, and alarm are set or initialized by writing the appropriate RAM bytes. The contents of the 10 time, calendar, and alarm bytes can be either Binary or Binary-Coded Decimal (BCD) format. Before writing the internal time, calendar, and alarm registers, the SET bit in Register B should be w ritten to a logic 1 to prevent updates from occurring while access is being attempted. In addition to writing the 10 time, calendar, and alarm registers in a selected format (binary or BCD), the data mode bit (DM) of Register B must be set to the appropriate logic level. All 10 time, calendar, and alarm bytes must use the same data mode. The set bit in Register B should be cleared after the d ata mode bit has been written to allow the real-time clock to update the time and calendar bytes. Once initialized, the real-time clock makes all updates in the selected mode. The data mode cannot be changed without reinitializing the 10 data bytes. Table 1 shows the binary and BCD formats of the ten time, calendar, and alarm locations. The 24-12 bit cannot be changed without reinitializing the hour locations. When the 12-hour format is selected, the high order bit of the hours byte represents PM when it is a logic one. The time, calendar,

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