General Description
The low-voltage serial-peripheral interface (SPI™)
DS1390/DS1391 and the low-voltage 3-wire DS1392/
DS1393 real-time clocks (RTCs) are clocks/calendars
that provide hundredths of a second, seconds, minutes, hours, day, date, month, and year information.
The date at the end of the month is automatically
adjusted for months with fewer than 31 days, including
corrections for leap year. The clock operates in either
the 24-hour or 12-hour format with an AM/PM indicator.
One programmable time-of-day alarm is provided. A
temperature-compensated voltage reference monitors
the status of VCCand automatically switches to the
backup supply if a power failure is detected. On the
DS1390, a single open-drain output provides a CPU
interrupt or a square wave at one of four selectable frequencies. The DS1391 replaces the SQW/INT pin with a
RST output/debounced input.
The DS1390 and DS1391 are programmed serially
through an SPI-compatible, bidirectional bus. The
DS1392 and DS1393 communicate over a 3-wire serial
bus, and the extra pin is used for either a separate
interrupt pin or a RST output/debounced input.
All four devices are available in a 10-pin µSOP package,
and are rated over the industrial temperature range.
Applications
Hand-Held Devices
GPS/Telematics Devices
Embedded Time Stamping
Medical Devices
Features
♦ Real-Time Clock Counts Hundredths of Seconds,
Seconds, Minutes, Hours, Day, Date, Month, and
Year with Leap-Year Compensation Valid Up to
2100
♦ Output Pin Configurable as Interrupt or Square
Wave with Programmable Frequency of
32.768kHz, 8.192kHz, 4.096kHz, or 1Hz
(DS1390/DS1393 Only)
♦ One Time-of-Day Alarm
♦ Power-Fail Detect and Switch Circuitry
♦ Reset Output/Debounced Input (DS1391/DS1393)
♦ Separate SQW and INT Output (DS1392)
♦ Trickle-Charge Capability
♦ SPI Supports Modes 1 and 3 (DS1390/DS1391)
♦ 3-Wire Interface (DS1392/DS1393)
♦ 4MHz at 3.0V and 3.3V
♦ 1MHz at 1.8V
♦ Three Operating Voltages: 1.8V ±5%, 3.0V ±10%,
and 2.97 to 5.5V
♦ Industrial Temperature Range: -40°C to +85°C
♦ Underwriters Laboratory (UL) Recognized
DS1390/DS1391/DS1392/DS1393
Low-Voltage SPI/3-Wire RTCs with
Trickle Charger
______________________________________________ Maxim Integrated Products 1
Ordering Information
Rev 0; 7/04
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Typical Operating Circuits and Pin Configurations appear at
end of the data sheet.
Where “rr” is a revision code on the second line of the top mark.
PART
PIN-
TOP MARK
DS1390U-18
10 µSOP
DS1390 rr-18
DS1390U-3
10 µSOP DS1390 rr-3
DS1390U-33
10 µSOP
DS1390 rr-33
DS1391U-18
10 µSOP
DS1391 rr-18
DS1391U-3
10 µSOP DS1391 rr-3
DS1391U-33
10 µSOP
DS1391 rr-33
DS1392U-18
10 µSOP
DS1393 rr-18
DS1392U-3
10 µSOP DS1392 rr-3
DS1392U-33
10 µSOP
DS1392 rr-33
DS1393U-18
10 µSOP
DS1393 rr-18
DS1393U-3
10 µSOP DS1393 rr-3
DS1393U-33
-40°C to +85°C
10 µSOP
DS1393 rr-33
SPI is a trademark of Motorola, Inc.
TEMP RANGE
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
PACKAGE
DS1390/DS1391/DS1392/DS1393
Low-Voltage SPI/3-Wire RTCs with
Trickle Charger
2 _____________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
RECOMMENDED DC OPERATING CONDITIONS
(VCC= V
CC(MIN)
to V
CC(MAX)
, TA= -40°C to +85°C, unless otherwise noted. Typical values are at nominal supply voltage and TA= +25°C,
unless otherwise noted.) (Note 1)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Voltage Range on VCCPin Relative to Ground .....-0.3V to +6.0V
Voltage Range on Inputs Relative
to Ground ...............................................-0.3V to (V
CC
+ 0.3V)
Operating Temperature Range ...........................-40
°C to +85°C
Storage Temperature Range .............................-55°C to +125°C
Soldering Temperature .......................................See IPC/JEDEC
J-STD-020A Specification
PARAMETER
CONDITIONS
UNITS
DS139x-33
3.3
DS139x-3 2.7 3.0 3.3
Supply Voltage (Note 2) V
CC
DS139x-18
1.8
V
Logic 1 V
IH
(Note 2)
0.7 x
VCC +
0.5
V
Logic 0 V
IL
(Note 2)
+0.3 x
V
Supply Voltage, Pullup
SQW/INT, SQW, INT, VCC = 0V
V
PU
(Note 2) 5.5 V
-33 1.3
)
-3 1.3 3.0 3.7
V
BACKUP
Voltage (Note 2)
-18 1.3 3.0 3.7
V
-33
-3
2.6
Power-Fail Voltage (Note 2) V
PF
-18
1.6
V
R1 (Notes 3, 4)
R2 (Notes 3, 5)
Trickle-Charge Current-Limiting
Resistors
R3 (Notes 3, 6)
Ω
Input Leakage I
LI
(Note 7) -1 +1 µA
I/O Leakage I
LO
(Note 8) -1 +1 µA
RST Pin I/O Leakage I
LORST
(Note 9)
µA
-33, -3 (V
OH
= 0.85 x VCC)-1
DOUT Logic 1 Output
-18 (V
OH
= 0.80 x VCC)
mA
-33, -3 (V
OL
= 0.15 x VCC)3
DOUT Logic 0 Output
-18 (V
OL
= 0.20 x VCC)2
mA
VCC > 1.71V; VOL = 0.4V 3.0 mA
Logic 0 Output
(DS1390/DS1393 SQW/INT;
DS1392 SQW, INT;
DS1391/DS1393 RST)
I
OLSIR
1.3V < VCC < 1.71V; VOL = 0.4V 250 µA
-33 2
-3 2
mA
VCC Active Supply Current
(Note 10)
I
CCA
-18 500 µA
SYMBOL
MIN TYP MAX
2.97
5.50
V
BACKUP
I
OHDOUT
I
OHDOUT
1.71
V
CC
-0.3
3.0 V
2.70 2.88 2.97
2.45
1.51
250
2000
4000
-200 +10
1.89
V
CC(MAX
2.70
1.71
0.750
CC
DS1390/DS1391/DS1392/DS1393
Low-Voltage SPI/3-Wire RTCs with
Trickle Charger
_____________________________________________________________________ 3
RECOMMENDED DC OPERATING CONDITIONS (continued)
(VCC= V
CC(MIN)
to V
CC(MAX)
, TA= -40°C to +85°C, unless otherwise noted. Typical values are at nominal supply voltage and TA= +25°C,
unless otherwise noted.) (Note 1)
PARAMETER
CONDITIONS
UNITS
-33
175
-3 80 125
VCC Standby Current
(Note 11)
I
CCS
-18 60 100
µA
V
BACKUP
Leakage Current
(V
BACKUP
= 3.7V,
V
CC
= V
CC(MAX)
)
15 100 nA
DC ELECTRICAL CHARACTERISTICS
(VCC= 0V, V
BACKUP
= 3.7V, TA= -40°C to +85°C, unless otherwise noted.) (Note 1)
PARAMETER
CONDITIONS
UNITS
V
BACKUP
Current OSC On,
SQW Off
(Note 12)
nA
V
BACKUP
Current OSC On,
SQW On (32kHz)
(Note 12)
nA
V
BACKUP
Current OSC On,
SQW On, V
BACKUP
= 3.0V,
T
A
= +25°C
(Note 12)
nA
V
BACKUP
Current, OSC Off
(Data Retention)
(Note 12) 25 100 nA
AC ELECTRICAL CHARACTERISTICS—SPI INTERFACE
(VCC= V
CC(MIN)
to V
CC(MAX)
, TA= -40°C to +85°C, unless otherwise noted.) (Note 1)
PARAMETER
CONDITION
UNITS
2.7V ≤ VCC ≤ 5.5V 4
SCLK Frequency (Note 13) f
SCLK
1.71V ≤ VCC ≤ 1.89V 1
MHz
Data to SCLK Setup t
DC
(Notes 13, 14) 30 ns
SCLK to Data Hold t
CDH
(Notes 13, 14) 30 ns
2.7V ≤ VCC ≤ 5.5V 80
SCLK to Data Valid
(Notes 13, 14, 15)
t
CDD
1.71V ≤ VCC ≤ 1.89V 160
ns
2.7V ≤ VCC ≤. 5.5V
SCLK Low Time (Note 13) t
CL
1.71V ≤ VCC ≤ 1.89V
ns
2.7V ≤ VCC ≤ 5.5V
SCLK High Time (Note 13) t
CH
1.71V ≤ VCC ≤ 1.89V
ns
SCLK Rise and Fall tR, t
F
200 ns
CS to SCLK Setup (Note 13) t
CC
ns
SCLK to CS Hold (Note 13) t
CCH
ns
2.7V ≤ VCC ≤. 5.5V
CS Inactive Time (Note 13) t
CWH
1.71V ≤ VCC ≤ 1.89V
ns
CS to Output High Impedance t
CDZ
(Notes 13, 14) 40 ns
SYMBOL
I
BACKUPLKG
SYMBOL
I
BACKUP1
I
BACKUP2
I
BACKUP3
I
BACKUPDR
MIN TYP MAX
115
MIN TYP MAX
500 1000
600 1150
600 1000
SYMBOL
MIN TYP MAX
110
400
110
400
400
100
400
500
DS1390/DS1391/DS1392/DS1393
Low-Voltage SPI/3-Wire RTCs with
Trickle Charger
4 _____________________________________________________________________
CS
SCLK
DIN
W/R
t
DC
t
CL
t
CH
t
CDD
t
CDZ
t
CDH
t
CC
t
R
t
F
A6
A0
D0
WRITE ADDRESS BYTE
NOTE: SCLK CAN BE EITHER POLARITY, SHOWN FOR CPOL = 1.
READ DATA BYTE
DOUT
D7
Figure 1. Timing Diagram—SPI Read Transfer
CS
SCLK
DIN
W/R
t
DC
t
CDH
t
CL
t
CH
t
CCH
t
CWH
t
F
t
R
t
CC
A6
A0
WRITE ADDRESS BYTE
WRITE DATA BYTE
D7 D0
Figure 2. Timing Diagram—SPI Write Transfer
DS1390/DS1391/DS1392/DS1393
Low-Voltage SPI/3-Wire RTCs with
Trickle Charger
_____________________________________________________________________ 5
AC ELECTRICAL CHARACTERISTICS—3-WIRE INTERFACE
(VCC= V
CC(MIN)
to V
CC(MAX)
, TA= -40°C to +85°C.) (Note 1) (Figures 3, 4)
PARAMETER
CONDITION
UNITS
2.7V ≤ VCC ≤ 5.5V 4
SCLK Frequency (Note 13) f
SCLK
1.71V ≤ VCC ≤ 1.89V 1
MHz
Data to SCLK Setup t
DC
(Notes 13, 14) 30 ns
SCLK to Data Hold t
CDH
(Notes 13, 14) 30 ns
2.7V ≤ VCC ≤ 5.5V 80
SCLK to Data Valid (Notes 13,
14, 15)
t
CDD
1.71V ≤ VCC ≤ 1.89V 160
ns
2.7V ≤ VCC ≤ 5.5V
SCLK Low Time (Note 13) t
CL
1.71V ≤ VCC ≤ 1.89V
ns
2.7V ≤ VCC ≤ 5.5V
SCLK High Time (Note 13) t
CH
1.71V ≤ VCC ≤ 1.89V
ns
SCLK Rise and Fall tR, t
F
200 ns
CS to SCLK Setup t
CC
(Note 13)
ns
SCLK to CS Hold t
CCH
(Note 13)
ns
2.7V ≤ VCC ≤ 5.5V
CS Inactive Time (Note 13) t
CWH
1.71V ≤ VCC ≤ 1.89V
ns
CS to Output High Impedance t
CDZ
(Note 13, 14) 40 ns
AC ELECTRICAL CHARACTERISTICS
(VCC= V
CC(MIN)
to V
CC(MAX)
, TA= -40°C to +85°C, unless otherwise noted.) (Note 1)
PARAMETER
CONDITIONS
UNITS
Pushbutton Debounce PB
DB
200 ms
Reset Active Time t
RST
200 ms
Oscillator Stop Flag (OSF) Delay
t
OSF
(Note 16)
ms
SYMBOL
MIN TYP MAX
110
400
110
400
400
100
400
500
SYMBOL
MIN TYP MAX
160
160
100
DS1390/DS1391/DS1392/DS1393
Low-Voltage SPI/3-Wire RTCs with
Trickle Charger
6 _____________________________________________________________________
t
DC
t
CL
t
CH
t
CDH
t
CC
t
CDD
t
CDZ
t
R
t
F
A0 A1 R/W
D0 D7
WRITE ADDRESS BYTE
READ DATA BYTE
CE
SCLK
I/O
Figure 3. Timing Diagram—3-Wire Read Transfer
I/O
CE
SCLK
t
DC
t
CL
t
CH
t
CDH
t
CC
t
CCH
t
CWH
t
R
t
F
A0 A1 R/W
D0
D7
WRITE ADDRESS BYTE
WRITE DATA BYTE
Figure 4. Timing Diagram—3-Wire Write Transfer
DS1390/DS1391/DS1392/DS1393
Low-Voltage SPI/3-Wire RTCs with
Trickle Charger
_____________________________________________________________________ 7
OUTPUTS
V
CC
V
PF(MAX)
INPUTS
HIGH-IMPEDANCE
RST
DON'T CARE
VALID
RECOGNIZED
RECOGNIZED
VALID
V
PF(MIN)
t
RST
t
RPU
t
R
t
F
V
PF
V
PF
Figure 5. Power-Up/Down Timing
t
RST
PB
DB
RST
Figure 6. Pushbutton Reset Timing
POWER-UP/POWER-DOWN CHARACTERISTICS
(TA= -40°C to +85°C) (Figures 5, 6)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
VCC Detect to Recognize Inputs
(V
CC
Rising)
t
RST
(Note 17)
200 ms
VCC Fall Time; V
PF(MAX)
to
V
PF(MIN)
t
F
µs
VCC Rise Time; V
PF(MIN)
to
V
PF(MAX)
t
R
0µs
160
300
DS1390/DS1391/DS1392/DS1393
Low-Voltage SPI/3-Wire RTCs with
Trickle Charger
8 _____________________________________________________________________
CAPACITANCE
(TA= +25°C)
PARAMETER
CONDITIONS
UNITS
Capacitance on All Input Pins C
IN
10 pF
Capacitance on All Output Pins
(High Impedance)
C
IO
10 pF
WARNING: Under no circumstances are negative undershoots, of any amplitude, allowed when the device
is in write protection.
Note 1: Limits at -40°C are guaranteed by design and not production tested.
Note 2: All voltages are referenced to ground.
Note 3: The use of the 250Ω trickle-charge resistor is not allowed at V
CC
> 3.63V and should not be enabled. Use of the diode is
not recommended for V
CC
< 3.0V.
Note 4: Measured at V
CC
= typ, V
BACKUP
= 0V, register 0Fh = A5h.
Note 5: Measured at V
CC
= typ, V
BACKUP
= 0V, register 0Fh = A6h.
Note 6: Measured at V
CC
= typ, V
BACKUP
= 0V, register 0Fh = A7h.
Note 7: SCLK, DIN, CS on DS1390/DS1391; SCLK, and CE on DS1392/DS1393.
Note 8: DOUT, SQW/INT (DS1390/DS1393), SQW, and INT (DS1392).
Note 9: The RST pin has an internal 50kΩ (typ) pullup resistor to V
CC
.
Note 10: I
CCA
—SCLK clocking at max frequency = 4MHz for 3V and 3.3V versions; 1MHz for 1.8V version; RST (DS1391/DS1393)
inactive. Outputs are open.
Note 11: Specified with bus inactive.
Note 12: Measured with a 32.768kHz crystal attached to X1 and X2. Typical values measured at +25°C and 3.0V
BACKUP
.
Note 13: With 50pF load.
Note 14: Measured at V
IH
= 0.7 x VDDor VIL= 0.2 x VDD, 10ns rise/fall times.
Note 15: Measured at V
OH
= 0.7 x VDDor VOL= 0.2 x VDD. Measured from the 50% point of SCLK to the VOHminimum of SDO.
Note 16: The parameter t
OSF
is the time that the oscillator must be stopped for the OSF flag to be set over the voltage range of
0 ≤ V
CC
≤ V
CC(MAX)
and 1.3V ≤ V
BAT
≤ 5.5V.
Note 17: This delay applies only if the oscillator is enabled and running. If the EOSC bit is 1, the startup time of the oscillator is
added to this delay.
SYMBOL
MIN TYP MAX
DS1390/DS1391/DS1392/DS1393
Low-Voltage SPI/3-Wire RTCs with
Trickle Charger
_____________________________________________________________________ 9
Typical Operating Characteristics
(VCC= +3.3V, TA= +25°C, unless otherwise noted.)
I
BACKUP
vs. V
BACKUP
, BBSQ1 = 0
DS1390 TOC01
V
BACKUP
(V)
SUPPLY CURRENT (nA)
4.5 4.94.13.3 3.72.92.52.11.7
350
400
450
500
550
600
300
1.3 5.3
VCC= 0
I
BACKUP
vs. V
BACKUP
, BBSQ1 = 1
DS1390 toc02
V
BACKUP
(V)
SUPPLY CURRENT (nA)
5.34.94.1 4.52.1 2.5 2.9 3.3 3.71.7
350
400
450
500
550
600
650
700
750
800
850
900
950
1000
300
1.3
VCC = 0V
I
BACKUP
vs. TEMPERATURE
V
BACKUP
= 3.0V
DS1390 toc03
TEMPERATURE (°C)
SUPPLY CURRENT (nA)
806040200-20
300
400
350
450
500
550
600
250
-40
VCC = 0V
OSCILLATOR FREQUENCY
vs. SUPPLY VOLTAGE
DS1390 toc04
SUPPLY (V)
FREQUENCY (Hz)
5.34.84.33.83.32.82.31.8
32767.85
32767.90
32767.95
32768.00
32767.80
1.3
DS1390/DS1391/DS1392/DS1393
Low-Voltage SPI/3-Wire RTCs with
Trickle Charger
10 ____________________________________________________________________
Pin Description
PIN
NAME FUNCTION
1111 X1
2222 X2
Connections for Standard 32.768kHz Quartz Crystal. The internal oscillator
circuitry is designed for operation with a crystal having a 6pF specified load
capacitance (C
L
). Pin X1 is the input to the oscillator and can optionally be
connected to an external 32.768kHz oscillator. The output of the internal
oscillator, pin X2, is floated if an external oscillator is connected to pin X1.
3333
DC Backup Power Input for Primary Cell. This pin is a rechargeable
battery/super cap or a secondary supply. UL recognized to ensure against
reverse charging current when used with a lithium battery.
44—— CS SPI Chip-Select Input. This pin is used to select or deselect the part.
—— 44 CE Chip Enable for 3-Wire Interface
5555GND Ground
66—— DIN SPI Data Input. This pin is used to shift address and data into the part.
—— 6 — INT
Interrupt Output. This pin is used to output the interrupt signal, if enabled by
the control register. The maximum voltage on this pin is 5.5V, independent
of V
CC
or V
BACKUP
. If enabled, INT functions when the device is powered
by either V
CC
or V
BAT
.
—9—6 RST
Reset. This active-low, open-drain output indicates the status of V
CC
relative
to the V
PF
specification. As Vcc falls below VPF, the RST pin is driven low.
When Vcc exceeds V
PF
, for t
RST
, the RST pin is driven high impedance.
This pin is combined with a debounced pushbutton input function. This pin
can be activated by a pushbutton reset request. This pin has an internal,
50kΩ (typ) pullup resistor to V
CC
. No external pullup resistors should be
connected. If the crystal oscillator is disabled, the startup time of the
oscillator is added to the t
RST
delay.
77——DOUT
SPI Data Output. Data is output on this pin when the part is in read mode.
CMOS push-pull driver.
—— 77 I/O Input/Output for 3-Wire Interface. CMOS push-pull driver.
8888SCLK
Serial Clock Input. This pin is used to control the timing of data into and out
of the part.
9——9
Square-Wave/Interrupt Output. This pin is used to output the programmable
square wave or interrupt signal. When enabled by setting the ESQW bit to
logic 1, the SQW/INT pin outputs one of four frequencies: 32.768kHz,
8.192kHz, 4.096kHz, or 1Hz. This pin is open drain and requires an external
pullup resistor. The maximum voltage on this pin is 5.5V, independent of
V
CC
or V
BACKUP
. If enabled, SQW/INT functions when the device is
powered by either V
CC
or V
BAT
.
—— 9 — SQW
Square-Wave Output. This pin is open drain and requires an external pullup
resistor. The maximum voltage on this pin is 5.5V, independent of V
CC
or
V
BACKUP
. If enabled, SQW functions when the device is powered by either
V
CC
or V
BAT
.
10 10 10 10 V
CC
DC Power Pin for Primary Power Supply
DS1390 DS1391 DS1392 DS1393
V
BACKUP
SQW/INT
Detailed Description
The DS1390/DS1391/DS1392/DS1393 RTCs are lowpower clocks/calendars with alarms. Address and data
are transferred serially through a 4-wire SPI interface
for the DS1390 and DS1391 and through a 3-wire interface for the DS1392 and DS1393. The clocks/calendars
provide hundredths of seconds, seconds, minutes,
hours, day, date, month, and year information. The
alarm functions are performed off all timekeeping registers, allowing the user to set high resolution alarms. The
date at the end of the month is automatically adjusted
for months with fewer than 31 days, including corrections for leap year. The clocks operate in either the 24hour or 12-hour format with an AM/PM indicator. All four
devices have a built-in temperature-compensated voltage reference that detects power failures and automati-
cally switches to the battery supply. Additionally, the
devices can provide trickle charging of the backup
voltage source, with selectable charging resistance
and diode voltage drops.
Operation
The DS1390/DS1391 operate as a slave device on the
SPI serial bus. The DS1392/DS1393 operate using a
3-wire synchronous serial bus. Access is obtained by
selecting the part by the CS pin (CE on DS1392/
DS1393) and clocking data into/out of the part using
the SCLK and DIN/DOUT pins (I/O on DS1392/
DS1393). Multiple-byte transfers are supported within
one CS low period (see the SPI Serial-Data Bus section). The devices are fully accessible and data can be
written and read when VCCis greater than VPF.
DS1390/DS1391/DS1392/DS1393
Low-Voltage SPI/3-Wire RTCs with
Trickle Charger
____________________________________________________________________ 11
Functional Diagram
BUS
INTERFACE
V
CC
LEVEL DETECT,
POWER SWITCH,
WRITE PROTECT,
TRICKLE CHARGER
32,768Hz
CRYSTAL
OSCILLATOR
(DS1390/91) DIN
(DS1390/91) DOUT
(DS1392/93) I/O
X2
SCLK
V
CC
GND
V
BACKUP
X1
(DS1390/91) CS
(DS1392/93) (CE)
SQUARE-WAVE RATE
SELECTOR, INT, MUX,
RST OUTPUT
HUNDREDTHS-OF-
SECONDS
GENERATOR
REAL-TIME CLOCK
WITH HUNDREDTHS
OF SECONDS
TRICKLE REGISTER
SQW/INT (DS1390/93)
CONTROL/STATUS
REGISTERS
ALARM REGISTERS
RST (DS1391/93)
SQW (DS1392)
DS1390/DS1391/
DS1392/DS1393
DS1390/DS1391/DS1392/DS1393
However, when VCCfalls below VPF, the internal clock
registers are blocked from any access. If VPFis less
than V
BACKUP
, the device power is switched from V
CC
to V
BACKUP
when VCCdrops below VPF. If VPFis
greater than V
BACKUP
, the device power is switched
from VCCto V
BACKUP
when VCCdrops below
V
BACKUP
. The registers are maintained from the
V
BACKUP
source until VCCis returned to nominal levels.
See the Functional Diagram for the main elements of
these serial RTCs.
Oscillator Circuit
All four devices use an external 32.768kHz crystal. The
oscillator circuit does not require any external resistors
or capacitors to operate. Table 1 specifies several crystal parameters for the external crystal, and Figure 7
shows a functional schematic of the oscillator circuit. If
a crystal is used with the specified characteristics, the
startup time is usually less than one second.
Clock Accuracy
The accuracy of the clock is dependent upon the accuracy of the crystal and the accuracy of the match
between the capacitive load of the oscillator circuit and
the capacitive load for which the crystal was trimmed.
Additional error is added by crystal frequency drift
caused by temperature shifts. External circuit noise
coupled into the oscillator circuit can result in the clock
running fast. Figure 8 shows a typical PC board layout
for isolation of the crystal and oscillator from noise.
Refer to Application Note 58: Crystal Considerations
with Dallas Real-Time Clocks for detailed information.
Low-Voltage SPI/3-Wire RTCs with
Trickle Charger
12 ____________________________________________________________________
PARAMETER
UNITS
Nominal Frequency
f
O
32.768
kHz
Series Resistance ESR
kΩ
Load Capacitance
C
L
6pF
Table 1. Crystal Specifications*
*The crystal, traces, and crystal input pins should be isolated
from RF generating signals. Refer to Application Note 58:
Crystal Considerations for Dallas Real-Time Clocks for additional specifications.
Figure 7. Oscillator Circuit Showing Internal Bias Network
LOCAL GROUND PLANE (LAYER 2)
CRYSTAL
GND
X2
X1
NOTE: AVOID ROUTING SIGNAL LINES
IN THE CROSSHATCHED AREA
(UPPER LEFT QUADRANT) OF
THE PACKAGE UNLESS THERE IS
A GROUND PLANE BETWEEN THE
SIGNAL LINE AND THE DEVICE PACKAGE.
Figure 8. Layout Example
SYMBOL MIN TYP MAX
55
COUNTDOWN
CHAIN
1C
C
L
X1
CRYSTAL
2
L
RTC REGISTERS
DS139x
X2
Address Map
Table 2 shows the address map for the DS1390–
DS1393 RTC and RAM registers. The RTC registers are
located in address locations 00h to 0Fh in read mode,
and 80h to 8Fh in write mode. During a multibyte
access, when the address pointer reaches 0Fh, it
wraps around to location 00h. On the falling edge of the
CS pin (DS1390/DS1391) or the rising edge of CE
(DS1392/DS1393), the current time is transferred to a
second set of registers. The time information is read
from these secondary registers, while the clock may
continue to run. This eliminates the need to re-read the
registers if the main registers update during a read. To
avoid rollover issues when writing to the time and date
registers, all registers should be written before the hundredths-of-seconds registers reaches 99 (BCD).
DS1390/DS1391/DS1392/DS1393
Low-Voltage SPI/3-Wire RTCs with
Trickle Charger
____________________________________________________________________ 13
WRITE
ADDRESS
READ
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
FUNCTION
RANGE
80h 00h Tenths of Seconds Hundredths of Seconds
Hundredths
0–99 BCD
81h 01h 0 10 Seconds Seconds Seconds
00–59 BCD
82h 02h 0 10 Minutes Minutes Minutes
00–59 BCD
83h 03h 0
10
Hour Hours
1–12 +AM/PM
00–23 BCD
84h 04h 0 0 0 0 0 Day Day 1–7 BCD
85h 05h 0 0 10 Date Date Date
01–31 BCD
86h 06h
00
10
Month
Month/
Century
01–12 +
Century BCD
87h 07h 10 Year Year Year
00–99 BCD
88h 08h Tenths of Seconds Hundredths of Seconds
Alarm
Hundredths
0–99 BCD
89h 09h
10 Seconds Seconds
Alarm
00–59 BCD
8Ah 0Ah
10 Minutes Minutes
Alarm
00–59 BCD
8Bh 0Bh
10
Hour
1–12 +
AM/PM
00–23 BCD
Day Alarm Day 1–7 BCD
8Ch 0Ch
10 Date
Date
1–31 BCD
0
0 AIE
DS1390/93
0XXX X0X DS1391
8Dh 0Dh
0
0 AIE
Control
DS1392
8Eh 0Eh
0000 00AF Status —
8Fh 0Fh
Trickle
Charger
—
Table 2. Address Map
Note: Unless otherwise specified, the state of the registers is not defined when power (VCCand V
BACKUP
) is first applied.
X = General-purpose read/write bit.
0 = Always reads as zero.
ADDRESS
12/24
Century
AM/PM
10 Hour
Hour
Month
of Seconds
AM1
AM2
AM3 12/24
AM4 DY/DT
EOSC
OSF
TCS3 TCS2 TCS1 TCS0 DS1 DS0 ROUT1 ROUT0
AM/PM
10 Hour
BBSQI RS2 RS1 INTCN
BBSQI RS2 RS1 ESQW
Hour
of Seconds
Alarm Hours
Alarm Date
DS1390/DS1391/DS1392/DS1393
Hundredths-of-Seconds
Generator
The hundredths-of-seconds generator circuit shown in
the functional diagram is a state machine that divides
the incoming frequency (4096Hz) by 41 for 24 cycles
and 40 for one cycle. This produces a 100Hz output
that is slightly off during the short term, and is exactly
correct every 250ms. The divide ratio is given by:
Ratio = [41 x 24 + 40 x 1] / 25 = 40.96
Thus, the long-term average frequency output is
exactly the desired 100Hz.
Clock and Calendar
The time and calendar information is obtained by reading the appropriate register bytes. See Table 2 for the
RTC registers. The time and calendar are set or initialized by writing the appropriate register bytes. The contents of the time and calendar registers are in the
binary-coded decimal (BCD) format. The day-of-week
register increments at midnight. Values that correspond
to the day-of-week are user-defined but must be
sequential (i.e., if 1 equals Sunday, then 2 equals
Monday, and so on). Illogical time and date entries
result in undefined operation. The DS1390–DS1393 can
run in either 12-hour or 24-hour mode. Bit 6 of the hours
register is defined as the 12- or 24-hour mode-select
bit. When high, the 12-hour mode is selected. In the 12hour mode, bit 5 is the AM/PM bit with logic high being
PM. In the 24-hour mode, bit 5 is the second 10-hour
bit (20 to 23 hours). Changing the 12/24-hour modeselect bit requires that the hours data be re-entered,
including the alarm register (if used). The century bit
(bit 7 of the month register) is toggled when the years
register overflows from 99 to 00.
Alarms
All four devices contain one time-of-day/date alarm.
Writing to registers 88h through 8Ch sets the alarm.
The alarm can be programmed (by the alarm enable
and INTCN bits of the control register) to activate the
SQW/INT or INT output on an alarm-match condition.
The alarm can activate the SQW/INT or INT output while
the device is running from V
BACKUP
if BBSQI is
enabled. Bit 7 of each of the time-of-day/date alarm
registers are mask bits (Table 3). When all the mask
bits for each alarm are logic 0, an alarm only occurs
when the values in the timekeeping registers 00h to 06h
match the values stored in the time-of-day/date alarm
registers. The alarms can also be programmed to
repeat every second, minute, hour, day, or date. Table
3 shows the possible settings. Configurations not listed
in the table result in illogical operation.
Low-Voltage SPI/3-Wire RTCs with
Trickle Charger
14 ____________________________________________________________________
ALARM REGISTER MASK BITS (BIT 7)
REGISTER
08H
AM4 AM3 AM2 AM1
ALARM RATE
FFh X 1 1 1 1 Alarm every 1/100th of a second
F[0–9]h X 1 1 1 1 Alarm when hundredths of seconds match
[0–9][0–9]
X1 111Alarm when tenths, hundredths of seconds match
[0–9][0–9]
X1 110
Alarm when seconds, tenths, and hundredths of seconds
match
[0–9][0–9]
X1 100
Alarm when minutes, seconds, tenths, and hundredths of
seconds match
[0–9][0–9]
X1 000
Alarm when hours, minutes, seconds, tenths, and hundredths
of seconds match
[0–9][0–9]
00 000
Alarm when date, hours, minutes, seconds, tenths, and
hundredths of seconds match
[0–9][0–9]
10 000
Alarm when day, hours, minutes, seconds, tenths, and
hundredths of seconds match
Table 3. Alarm Mask Bits
DY/DT
The DY/DT bits (bit 6 of the alarm day/date registers)
control whether the alarm value stored in bits 0 to 5 of
that register reflects the day of the week or the date of
the month. If DY/DT is written to logic 0, the alarm is the
result of a match with date of the month. If DY/DT is
written to a logic 1, the alarm is the result of a match
with day of the week.
When the RTC register values match alarm register settings, the alarm-flag (AF) bit is set to logic 1. If the
alarm-interrupt enable (AIE) is also set to logic 1 and
the INTCN bit is set to logic 1, the alarm condition activates the SQW/INT signal.
Since the contents of register 08h are expected to normally contain a match value of 00–99 decimal, the
codes F[0–9], and FF have been used to tell the part to
mask the tenths or hundredths of seconds accordingly.
Power-Up/Down, Reset, and
Pushbutton Reset Functions
A precision temperature-compensated reference and
comparator circuit monitors the status of VCC. When an
out-of-tolerance condition occurs, an internal power-fail
signal is generated that blocks read/write access to the
device and forces the RST pin (DS1391/DS1393 only)
low. When VCCreturns to an in-tolerance condition, the
internal power-fail signal is held active for t
RST
to allow
the power supply to stabilize, and the RST (DS1391/
DS1393 only) pin is held low. If the EOSC bit is set to
logic 1 (to disable the oscillator in battery-backup
mode), the internal power-fail signal and the RST pin is
kept active for t
RST
plus the startup time of the oscillator.
The DS1391/DS1393 provide for a pushbutton switch to
be connected to the RST output pin. When the
DS1391/DS1393 are not in a reset cycle, it continuously
monitors the RST signal for a low-going edge. If an
edge is detected, the part debounces the switch by
pulling the RST pin low and inhibits read/write access.
After PBDBhas expired, the part continues to monitor
the RST line. If the line is still low, it continues to monitor
the line looking for a rising edge. Upon detecting
release, the part forces the RST pin low and holds it low
for an additional PBDB.
DS1390/DS1391/DS1392/DS1393
Low-Voltage SPI/3-Wire RTCs with
Trickle Charger
____________________________________________________________________ 15
DS1390/DS1391/DS1392/DS1393
Bit 7: Enable Oscillator (EOSC). When set to logic 0,
this bit starts the oscillator. When this bit is set to logic
1, the oscillator is stopped whenever the device is powered by V
BACKUP
. The oscillator is always enabled
when VCCis valid. This bit is enabled (logic 0) when
VCCis first applied.
Bit 5: Battery-Backed Square-Wave and Interrupt
Enable (BBSQI). This bit when set to logic 1 enables
the square wave or interrupt output when VCCis absent
and the DS1390/DS1392/DS1393 are being powered
by the V
BACKUP
pin. When BBSQI is logic 0, the
SQW/INT pin (or SQW and INT pins) goes high impedance when VCCfalls below the power-fail trip point.
This bit is disabled (logic 0) when power is first applied.
Bits 4 and 3: Rate Select (RS2 and RS1). These bits
control the frequency of the square-wave output when
the square wave has been enabled. The table below
shows the square-wave frequencies that can be selected with the RS bits. These bits are both set to logic 1
(32kHz) when power is first applied.
Bit 2: Interrupt Control (INTCN). This bit controls the
SQW/INT signal. When the INTCN bit is set to logic 0, a
square wave is output on the SQW/INT pin. The oscillator must also be enabled for the square wave to be output. When the INTCN bit is set to logic 1, a match
between the timekeeping registers and either of the
alarm registers then activates the SQW/INT (provided
the alarm is also enabled). The corresponding alarm
flag is always set, regardless of the state of the INTCN
bit. The INTCN bit is set to logic 0 when power is first
applied.
Bit 0: Alarm Interrupt Enable (AIE). When set to logic
1, this bit permits the alarm flag (AF) bit in the status
register to assert SQW/INT (when INTCN = 1). When
the AIE bit is set to logic 0 or INTCN is set to logic 0,
the AF bit does not initiate the SQW/INT signal. The AIE
bit is disabled (logic 0) when power is first applied.
Low-Voltage SPI/3-Wire RTCs with
Trickle Charger
16 ____________________________________________________________________
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
EOSC 0 BBSQI RS2 RS1 INTCN 0 AIE
Control Register (0D/8Dh) (DS1390/DS1393 Only)
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
EOSC 0XXXX0X
Control Register (0D/8Dh) (DS1391 Only)
RS2
SQUARE-WAVE OUTPUT FREQUENCY
0
1Hz
0
4.096kHz
1
8.192kHz
1
32.768kHz
Special-Purpose Registers
The DS1390–DS1393 have three additional registers
(control, status, and trickle charger) that control the
RTC, alarms, square-wave output, and trickle charger.
Control bits used in the DS1390 become general-purpose, battery-backed, nonvolatile SRAM bits in the
DS1391.
RS1
0
1
0
1
Bit 7: Oscillator Stop Flag (OSF). A logic 1 in this bit
indicates that the oscillator has stopped or was
stopped for some time and may be used to judge the
validity of the clock and calendar data. This bit is
edge-triggered and is set to logic 1 when the internal
circuitry senses the oscillator has transitioned from a
normal run state to a STOP condition. The following are
examples of conditions that can cause the OSF bit to
be set:
1) The first time power is applied.
2) The voltage present on VCCand V
BACKUP
is
insufficient to support oscillation.
3) The EOSC bit is turned off.
4) External influences on the crystal (i.e., noise,
leakage, etc.).
This bit remains at logic 1 until written to logic 0. This
bit can only be written to logic 0. Attempting to write
OSF to logic 1 leaves the value unchanged.
Bit 6: Alarm Flag (AF). A logic 1 in the AF bit indicates
that the time matched the alarm registers. If the AIE bit
The INTCN bit used in the DS1390/DS1393 becomes
the SQW pin-enable bit in the DS1392. This bit powers
up a zero, making SQW active.
DS1390/DS1391/DS1392/DS1393
Low-Voltage SPI/3-Wire RTCs with
Trickle Charger
____________________________________________________________________ 17
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
EOSC 0 BBSQI RS2 RS1 ESQW 0 AIE
Control Register (0D/8Dh) (DS1392 Only)
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
OSF 000000AF
Status Register (0E/8Eh)
is logic 1 and the INTCN bit is set to logic 1, the
SQW/INT pin is also asserted. AF is cleared when written to logic 0. This bit can only be written to logic 0.
Attempting to write to logic 1 leaves the value
unchanged.
Trickle-Charge Register (0F/8Fh)
The simplified schematic in Figure 9 shows the basic
components of the trickle charger. The trickle-charge
select (TCS) bits (bits 4 to 7) control the selection of
the trickle charger. To prevent accidental enabling,
only a pattern on 1010 enables the trickle charger. All
other patterns disable the trickle charger. The trickle
charger is disabled when power is first applied. The
diode-select (DS) bits (bits 2 and 3) select whether or
not a diode is connected between VCCand V
BACKUP
.
If DS is 01, no diode is selected or if DS is 10, a diode
is selected. The ROUT bits (bits 0 and 1) select the
value of the resistor connected between VCCand
V
BACKUP
. Table 5 shows the resistor selected by the
resistor-select (ROUT) bits and the diode selected by
the diode-select (DS) bits.
TCS3
DS1 DS0
FUNCTION
XXXX00XXDisabled
XXXX11XXDisabled
XXXXXX00Disabled
10100101No diode, 250Ω resistor
10101001One diode, 250Ω resistor
10100110No diode, 2kΩ resistor
10101010One diode, 2kΩ resistor
10100111No diode, 4kΩ resistor
10101011One diode, 4kΩ resistor
00000000Initial default value—disabled
Table 5. Trickle-Charge Register
TCS2 TCS1 TCS0
ROUT1 ROUT0
DS1390/DS1391/DS1392/DS1393
The user determines diode and resistor selection
according to the maximum current desired for battery
or super cap charging. The maximum charging current
can be calculated as illustrated in the following example. Assume that a system power supply of 3.3V is
applied to VCCand a super cap is connected to
V
BACKUP
. Also, assume that the trickle charger has
been enabled with a diode and resistor R2 between
VCCand V
BACKUP
. The maximum current I
MAX
would
therefore be calculated as follows:
I
MAX
= (3.3V - diode drop) / R2 ≈ (3.3V - 0.7V) /
2kΩ≈1.3mA
As the super cap changes, the voltage drop between
VCCand V
BACKUP
decreases and therefore the charge
current decreases.
Low-Voltage SPI/3-Wire RTCs with
Trickle Charger
18 ____________________________________________________________________
R1
250Ω
R2
2kΩ
R3
4kΩ
V
CC
V
BACKUP
BIT 7
BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
TCS3 TCS2 TCS1 TCS0 DS1 DS0 ROUT1 ROUT0
TRICKLE-CHARGE REGISTER (8Fh WRITE, 0Fh READ)
1 0F 16 SELECT
NOTE: ONLY 1010b ENABLES CHARGER
1 OF 2
SELECT
1 OF 3
SELECT
TCS
0-3
= TRICKLE-CHARGE SELECT
DS
0-1
= DIODE SELECT
ROUT
0-1
= RESISTOR SELECT
Figure 9. DS1390/DS1391 Programmable Trickle Charger
CS
SCLK WHEN CPOL = 0
SCLK WHEN CPOL = 1
DATA LATCH (WRITE/INTERNAL STROBE)
SHIFT DATA OUT (READ)
DATA LATCH (WRITE/INTERNAL STROBE)
SHIFT DATA OUT (READ)
NOTE 1:
CPHA BIT POLARITY (IF APPLICABLE) MAY NEED TO BE SET ACCORDINGLY.
NOTE 2:
CPOL IS A BIT SET IN THE MICROCONTROLLER'S CONTROL REGISTER.
NOTE 3:
SDO REMAINS AT HIGH IMPEDANCE UNTIL 8 BITS OF DATA ARE READY TO BE
SHIFTED OUT DURING A READ.
Figure 10. Serial Clock as a Function of Microcontroller ClockPolarity Bit
MODE
SCLK SDI SDO
Disable
Input
Disabled
Input
Disabled
High
Impedance
CPOL* = 1,
Write
CPOL = 0,
Data Bit
Latch
High
Impedance
CPOL = 1,
Read
CPOL = 0,
X
Next Data
Bit Shift**
Table 6. SPI Pin Function
*CPOL is the clock-polarity bit set in the control register of the
host microprocessor.
**SDO remains at high impedance until 8 bits of data are ready to
be shifted out during a read.
CSZ
H
L
L
SCLK Rising
SCLK Falling
SCLK Falling
SCLK Rising
SPI Serial-Data Bus
The DS1390/DS1391 provide a 4-wire SPI serial-data
bus to communicate in systems with an SPI host controller. Both devices support single-byte and multiplebyte data transfers for maximum flexibility. The DIN and
DOUT pins are the serial-data input and output pins,
respectively. The CS input initiates and terminates a
data transfer. The SCLK pin synchronizes data movement between the master (microcontroller) and the
slave (DS1390/DS1391) devices. The shift clock
(SCLK), which is generated by the microcontroller, is
active only during address and data transfer to any
device on the SPI bus. Input data (DIN) is latched on
the internal strobe edge and output data (DOUT) is
shifted out on the shift edge (Figure 10). There is one
clock for each bit transferred. Address and data bits
are transferred in groups of eight.
Address and data bytes are shifted MSB first into the
serial-data input (DIN) and out of the serial-data output
(DOUT). Any transfer requires the address of the byte
to specify a write or read, followed by one or more
bytes of data. Data is transferred out of the DOUT pin
for a read operation and into the DIN for a write operation (Figures 11 and 12).
The address byte is always the first byte entered after
CS is driven low. The most significant bit (W/R) of this
byte determines if a read or write takes place. If W/R is
0, one or more read cycles occur. If W/R is 1, one or
more write cycles occur.
Data transfers can occur one byte at a time or in multiple-byte burst mode. After CS is driven low, an address
is written to the DS1390/DS1391. After the address, one
or more data bytes can be written or read. For a singlebyte transfer, one byte is read or written and then CS is
driven high. For a multiple-byte transfer, however, multiple bytes can be read or written after the address has
been written. Each read or write cycle causes the RTC
register address to automatically increment.
Incrementing continues until the device is disabled.
The address wraps to 00h after incrementing to 0Fh
(during a read) and wraps to 80h after incrementing to
8Fh (during a write). Note, however, that an updated
copy of the time is only loaded into the user-accessible
copy upon the falling edge of CS. Reading the RTC
registers in a continuous loop does not show the time
advancing.
DS1390/DS1391/DS1392/DS1393
Low-Voltage SPI/3-Wire RTCs with
Trickle Charger
____________________________________________________________________ 19
W/R A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
CS
SCLK
DIN
DOUT
HIGH IMPEDANCE
Figure 11. SPI Single-Byte Write
W/R A6 A5 A4 A3 A2 A1 A0
D7 D6 D5 D4 D3 D2 D1 D0
CS
SCLK
DIN
DOUT
HIGH IMPEDANCE
Figure 12. SPI Single-Byte Read
DS1390/DS1391/DS1392/DS1393
Low-Voltage SPI/3-Wire RTCs with
Trickle Charger
20 ____________________________________________________________________
CS
SCLK
DIN
DOUT
HIGH-IMPEDANCE
ADDRESS
BYTE
ADDRESS
BYTE
DATA BYTE 0 DATA BYTE 1
DIN
DATA BYTE N
DATA
BYTE 0
DATA
BYTE 1
DATA
BYTE N
WRITE
READ
Figure 13. SPI Multiple-Byte Burst Transfer
A1 A2 A3 A4 A5 A6
CE
SCLK
I/O
W/R
A0
D1 D2 D3 D4 D5 D6
D7D0
Figure 14. 3-Wire Single-Byte Read
A1 A2 A3 A4 A5 A6
CE
SCLK
I/O
W/R
A0
D1 D2 D3 D4 D5 D6
D7D0
Figure 15. 3-Wire Single-Byte Write
3-Wire Serial-Data Bus
The DS1392/DS1393 provide a 3-wire serial-data bus,
and support both single-byte and multiple-byte data
transfers for maximum flexibility. The I/O pin is the serial-data input/output pin. The CE input is used to initiate
and terminate a data transfer. The SCLK pin is used to
synchronize data movement between the master
(microcontroller) and the slave (DS1392/DS1393)
devices. Input data is latched on the SCLK rising edge
and output data is shifted out on the SCLK falling edge.
There is one clock for each bit transferred. Address
and data bits are transferred in groups of eight.
Address and data bytes are shifted LSB first into the
I/O pin. Data is transferred out LSB first on the I/O pin
for a read operation.
The address byte is always the first byte entered after
CE is driven high. The MSB (W/R) of this byte determines if a read or write takes place. If W/R is 0, one or
more read cycles occur. If W/R is 1, one or more write
cycles occur.
Data transfers can be one byte at a time or in multiplebyte burst mode. After CE is driven high, an address is
written to the DS1392/DS1393. After the address, one
or more data bytes can be written or read. For a singlebyte transfer, one byte is read or written and then CE is
driven low (Figure 14 and 15). For a multiple-byte transfer, however, multiple bytes can be read or written after
the address has been written (Figure 16). Each read or
write cycle causes the RTC register address to automatically increment. Incrementing continues until the
device is disabled. The address wraps to 00h after
incrementing to 0Fh (during a read) and wraps to 80h
after incrementing to 8Fh (during a write). Note, however, that an updated copy of the time is only loaded into
the user-accessible copy upon the rising edge of CE.
Reading the RTC registers in a continuous loop does
not show the time advancing.
Chip Information
TRANSISTOR COUNT: 11,525
PROCESS: CMOS
SUBSTRATE CONNECTED TO GROUND
Thermal Information
Theta-JA: 180°C/W
Theta-JC: 41.9°C/W
DS1390/DS1391/DS1392/DS1393
Low-Voltage SPI/3-Wire RTCs with
Trickle Charger
____________________________________________________________________ 21
CE
SCLK
I/O
ADDRESS
BYTE
DATA
BYTE 0
DATA
BYTE 1
DATA
BYTE N
Figure 16. 3-Wire Multiple-Byte Burst Transfer
DS1390/DS1391/DS1392/DS1393
Low-Voltage SPI/3-Wire RTCs with
Trickle Charger
22 ____________________________________________________________________
X1
TOP VIEW
X2
V
BACKUP
GND
µSOP µSOP
µSOP µSOP
V
CC
DOUT
DIN
1
2
3
4
8
7
6
SQW/INT
5
10
9
SCLK
CS
DS1390
X1
X2
V
BACKUP
GND
V
CC
I/O
INT
1
2
3
4
8
7
6
SQW
5
10
9
SCLK
CE
DS1392
X1
X2
V
BACKUP
GND
V
CC
DOUT
DIN
1
2
3
4
8
7
6
RST
5
10
9
SCLK
CS
DS1391
X1
X2
V
BACKUP
GND
V
CC
I/O
RST
1
2
3
4
8
7
6
SQW/INT
5
10
9
SCLK
CE
DS1393
Pin Configurations
DS1390/DS1391/DS1392/DS1393
Low-Voltage SPI/3-Wire RTCs with
Trickle Charger
____________________________________________________________________ 23
DS1390
DS1393
DS1391
DS1392
CE
SQW
I/O
CPU
V
CC
V
CC
V
CC
DIN
CS
GND
X2X1
CRYSTAL
SQW/INT
V
BACKUP
SCLK
DOUT
INT
CPU
V
CC
V
CC
V
CC
CE
GND
X2X1
CRYSTAL
SQW/INT
V
BACKUP
SCLK
I/O
CPU
V
CC
V
CC
V
CC
DIN
RST
RST
CS
GND
X2X1
CRYSTAL
V
BACKUP
SCLK
DOUT
CPU
V
CC
V
CC
V
CC
GND
X2X1
CRYSTAL
V
BACKUP
SCLK
RST
RST
Typical Operating Circuits
DS1390/DS1391/DS1392/DS1393
Low-Voltage SPI/3-Wire RTCs with
Trickle Charger
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
24 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2004 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.
is a registered trademark of Dallas Semiconductor Corporation.
10LUMAX.EPS
PACKAGE OUTLINE, 10L uMAX/uSOP
1
1
21-0061
I
REV.DOCUMENT CONTROL NO.APPROVAL
PROPRIETARY INFORMATION
TITLE:
TOP VIEW
FRONT VIEW
1
0.498 REF
0.0196 REF
S
6°
SIDE VIEW
α
BOTTOM VIEW
0° 0° 6°
0.037 REF
0.0078
MAX
0.006
0.043
0.118
0.120
0.199
0.0275
0.118
0.0106
0.120
0.0197 BSC
INCHES
1
10
L1
0.0035
0.007
e
c
b
0.187
0.0157
0.114
H
L
E2
DIM
0.116
0.114
0.116
0.002
D2
E1
A1
D1
MIN
-A
0.940 REF
0.500 BSC
0.090
0.177
4.75
2.89
0.40
0.200
0.270
5.05
0.70
3.00
MILLIMETERS
0.05
2.89
2.95
2.95
-
MIN
3.00
3.05
0.15
3.05
MAX
1.10
10
0.6±0.1
0.6±0.1
00.50±0.1
H
4X S
e
D2
D1
b
A2
A
E2
E1
L
L1
c
α
GAGE PLANE
A2 0.030 0.037 0.75 0.95
A1
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/DallasPackInfo
).
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