Rainbow Electronics DS1384 User Manual

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DS1384

Watchdog Timekeeping Controlle

FEATURES

 Keeps track of hundredths of seconds,

seconds, minutes, hours, days, date of the month, months, and years with leap year compensation valid up to 2100

 Watchdog timer restarts an out-of-control

processor

 Alarm function schedules real-time related

INTB/(INTB

activities

 Programmable interrupts and square wave

outputs

 Bytewide RAM-like access  50 bytes of on board user RAM  Greater than 10 years timekeeping and data

retention in the absence of power with small lithium coin cells

 Supports up to 128k x 8 of external static RAM  All timekeeping registers and on board RAM

are individually addressable via the address and data bus

ORDERING INFORMATION

DS 1384FP-12 44-Pin FP

PIN ASSIGNMENT

A14 A12

A7 A6 A5 A4 A3 A2

CCVCCO

INTA

X1X2GND

GND

44 34

A16

GND

SQW

6 D

PF0

7 D

BAT2

CEO

PIN DESCRIPTION

INTA - Interrupt Output A (open drain) INTB(INTB) - Interrupt Output B (open drain)

A0-A16 - Address Inputs DQ0-DQ7 - Data Input/Output

CE - Chip Enable

A15 V

A13

A8 A9 A11 OE

A10 CE OE

BAT1

OE - Output Enable WE - Write Enable

- +5V Input GND - Ground NC - No Connection SQW - Square Wave Output X1, X2 - 32.768 kHz Crystal Connections

PFO - Power Fail Output CEO - Chip Enable RAM OER - Output Enable RAM

CCO

BAT1

BAT2

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- Voltage Out

- +3V Battery Input

DS1384

DESCRIPTION

The DS1384 Watchdog Timekeeping Controller is a self-contained real time clock, alarm, watchdog timer, and interval timer which provides control of up to 128k x 8 of external low power CMOS static RAM in a 44-pin quad flat pack package. An external crystal and battery are the only components required to maintain time of day and RAM memory contents in the absence of power. Access to all RTC functions and the external RAM is the same as conventional bytewide SRAM. Data is maintained in the Watchdog Timekeeper by intelligent control circuitry which detects the status of VCC and write protects both memory and timekeeping functions when VCC is out of tolerance. Timekeeper information includes hundredths of seconds, seconds, minutes, hours, day, date, month, and year. The date at the end of the month is automatically adjusted for months with less than 31 days, including correction for leap year. The timekeeper operates in either 12- or 24-hour format with an AM/PM indicator. The watchdog internal timer provides watchdog alarm windows and interval timing between 0.01 seconds and 99.99 s econds. The real time alarm provides for preset times of up to one week. All of the RTC functions and the internal 50 bytes of RAM reside in the lower 64 bytes of the attached RAM memory map. The externally

attached static RAM is controlled by the DS1384 via the OER and CEO signals.

Automatic backup and write protection for an external SRAM is provided through the V

OER pins. The lithium energy source used to permanently power the real time clock is also used to retain

RAM data in the absence of VCC power through the V

pin. The chip enable output to RAM (CEO ) and

CCO

, CEO and

CCO

the output enable to RAM (OER ) are cont rolled during power transients to prevent data corruption. The DS1384 is a complete one-chip solution in that an external crystal and battery ar e the only components required to maintain time of day memory status in the absence of power.

SIGNAL DESCRIPTIONS

VCC, GND - DC power inputs: DC operating voltage is provided to the device on these pins. VCC is the +5V input.

, V

BAT1

must be held between 2.4 and 4-volts for proper operation. In the absence of power, the DS1384 will have a maximum load of 0.5 µA at 25°C. This should be added to the amount of current drawn from the external RAM in standby mode at 25°C to size the external energy source. The DS1384 samples V and V

BAT2

battery input must be grounded.

A16-A0 - Addr ess Bus (inputs): The address bus inputs qualified by CE , OE , WE , and VCC voltage are used to select the on-chip 64 timekeeping/RAM registers within the memory map of the external SRAM controlled as nonvolatile storage. When the qualified address bus value is within the range of

- Battery inputs for any standard 3-volt lithium cell or other energy source. Battery voltage

BAT2

BAT1

and always selects the battery with the higher voltage. If only one battery is used, the unused

00000H - 0003FH, one of the internal registers will be selected and

OER will remain inactive. When the

value is outside of the range, OE will be passed through to OER . D7-D0 - Data Bus (bi-directional): When a qualified address from 00000H throu gh 0003FH is presented

to the device, data is passed to or from the on-chip 64 timekeeping/RAM registers via the data bus lines. Data will be written on the rising edge of WE when CE is active. If CE is active without WE , data is read from the device and driven onto the data bus pins when OE is low.

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DS1384

- Switched DC power for SRAM (output): This pin will be connected to V

CCO

above VSO (the greater of V

BAT1

or V

). When VCC voltage falls below this level, V

BAT2

when VCC voltage is

will be

CCO

connected to the higher voltage battery pin.

CEO - RAM chip enable (output; active low): When power is good the CE input will be passed through

to CEO . If VCC is below VPF, CEO will remain at an inactive high level.

OER - RAM output enable (output; active low): When power is good and the address value is not within

the range of 00000H and 0003FH, and CE is active, the OE input will be passed through to OER . If these conditions are not met, OER will remain at an inactive high level.

CE - Chip enable (input; active low): The chip enable signal must be asserted low during a bus cycle to

access the on-chip timekeeping RAM registers, or to access the external RAM via CEO .

OE - Output enable (input; active low): The output enable signal identifies the time period when either

the RTC or the external SRAM drives the bus with read data, provided that CE is valid with WE disabled. When one of the 64 on-chip registers is selected during a re ad cycle, the OE is the enable signal

for the DS1384 output buffers and the data bus will be driven with read data. W hen the ex ternal RAM is selected during a read cycle, the OE signal will be passed through to the OER pin so that read data will be

driven by the external SRAM.

WE - Write enable (input; active low): The write enable signal identifies the time period during which

data is written to either the on-chip registers or to an external SRAM location. When one of the on-chip 64 registers is addressed, data will be written to the selected register on the rising edge of WE .

INTA - Interrupt Output A (output; active low): Interrupt output A can be programmed as a Time of Day

Alarm or as a Watchdog Alarm (Interrupt output B becomes the alternate function). In addition, INTA can be programmed to output either a pulse or a level.

INTB - Interrupt Output B (output; active high or low): Interrupt output B outputs the alarm (Time of

Day or Watchdog) that is not selected for

INTA . Interrupt output B is programmable high or low.

Both INTA and INTB(INTB) are open drain outputs. The two interrupts and the internal clock continue to run regardless of the level of VCC. However, it is important to insure that the pull-up resistors used with the interrupt pins are never pulled up to a value which is greater than V

+ 0.3V. As VCC falls below

approximately 3.0 volts, a power switching circuit turns the lithium energy source on the maintain the clock, and timer data functionality. It is also required to insure that during this time (battery backup

mode), the voltage present at INTA and INTB (INTB) does never exceed V

. At all times the current on

BAT

each should not exceed +2.1 mA or -1.0 mA. X1, X2 - Cr ystal inputs: Connections for a standard 32.768 kHz quartz crystal. When ordering, request a

load capacitance or 6 pF. The internal oscillator circuitry is designed for operation with a crystal having a specified load capacitance (CL) of 6 pF.

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DS1384

For more information on crystal selection and crystal layout considerations, please c onsult Application Note 58, “Crystal Considerations with Dallas Real Time Clocks.”

SQW - Square Wave (output): This pin can be programmed to output a 1024 Hz square wave signal. When the signal is turned off, the pin is high Z.

PFO - Power Fail Signal (output; active low when V

>4.5 volts.

occurs): High state occurs t

after power-up and

REC

ADDRESS DECODING

The DS1384 accommodates 17 address lines, which allows direct connection of up to 128k b ytes of static RAM. The lower 14 bytes of RAM, regardless of the density used, will always contain the timekeeping, alarm, and watchdog registers. The 14 clock registers reside in the lower 14 RAM locations without

conflict by inhibiting the OER (output enable RAM) signal during clock access. Since the watchdog timekeeping chip actually contains 64 registers (14 RTC and 50 user RAM), the lower 64 bytes of any attached memory resides within the DS1384. However, the RAM’s physical location is transparent to the user and the memory map looks continuous from the first clock address to the upper most attached RAM address.

OPERATION - READ CYCLE

The DS1384 executes a read cycle wh eneve r WE is inactive (high) and CE and OE are active (l ow). The unique address specified by the address inputs (A0-A16) defines which of the on-chip 64 RTC/RAM or external SRAM locations is to be accessed. When the address value pres ented to the DS1384 is in the range of 00000H through 0003FH, one of the 64 on-chip registers will be selected and valid data will be available to the eight data output drivers within t

providing that the CE and OE access times are also satisfied. If they are not, then data access must be

(access time) after the address input signal is stable,

ACC

measured from the latter occurri ng signal (CE or OE ) and the limiting parameter is either tCO for CE or tOE for OE rather than the address access time. When one of the on-chip registers is selected for read, the

OER signal will remain inactive throughout the read cycle.

When the address value presented to the DS1384 is in the range of 00040H through 1FFFFH, an external SRAM location will be selected. In this case the OE signal will be passed to the OER pin, with the

specified delay times of t

AOEL

or t

OERL

OPERATION - WRITE CYCLE

The DS1384 is in the write mode whenever the WE (Write Enable) and CE (Chip Enable) si gnals are in the active (low) state after the address inputs are stable. The latter occurrin g falling edge of will determine the start of the write cycle. The write cycle is terminated by the earlier rising edge of CE or WE . All address inputs must be kept valid throughout the write cycle. WE must return to the high state

for a minimum recovery state (t bus with sufficient Data Set Up (t

CE or WE . The OE control signal should be kept inactive (high) during write cycles to avoid bus

contention. However, if the output bus has been enabled ( outputs in t

from its falling edge.

WEZ

) before another cycle can be initiated. Data must be valid on the data

) and Data Hold Time (tDH) with respect to the earlier rising edge of

CE and OE active), then WE will disable the

CE or WE

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DS1384

When the address value presented to the DS1384 during the write is in the range of 00000H through 0003FH, one of the 64 on-chip registers will be selected and data will be written into the device.

When the address value presented to the DS1384 during the write is in the range of 00040H through 1FFFFH, an external SRAM location will be selected.

DATA RETENTION MODE

When V with read or write cycles. However, wh en V protection occurs) the internal clock registers and external RAM is blocked from access. This is

is within nominal limits (VCC > 4.5 volts) the DS1384 can be accessed as described above

CCI

is below the power-fail point, VPF, (point at which write

accomplished internally by inhibiting access to the clock registers via the power fail output signal ( External RAM access is inhibited in a similar manner by forcing

0.2 volts of the V

CCI

condition. When V the V

pin to the V

CCI

External RAM is also powered by the V V

pin is capable of supplying 100 µA of current to the attached m emory with less than 0.3 volts drop

CCO

under this condition. On power-up, when V

PFO) is driven active and will remain active until V

CEO to high level. This level is within

input. CEO will remain at this level as long as V

falls below the level of the battery (V

CCI

pin and the clock registers are maintained from the attached battery supply.

BAT

input when V

BAT

returns to in-tolerance conditions, write protection

CCI

or V

BAT1

BAT2

is below V

CE signal. At this time the

returns to nominal levels.

remains at an out-of-tolerance

CCI

), power input is switched from

pin through the V

BAT

pin. The

CCO

continues for 150 ms by inhibiting CEO . The PFO signal also remains active during this time. The DS1384 is capable of supporting two batteries which are used in a redundant fashion for applications which require added reliability or increased battery capacity. When two batteries are used, the higher of the two is selected for use. A selected battery will remain as backup supply until it is significantly below the other. When the selected battery voltage falls below the alternate battery by about 0.6 volts, the alternate battery is selected and then becomes the backup supply. This switching occurs transparently to the user and continues until both batteries are exhausted. When only a single battery is required, both battery inputs can be connected together. However, a more effective method of using a single battery supply is to ground the unused battery input. When using a single battery, V

is the preferred input.

BAT1

WATCHDOG TIMEKEEPER REGISTERS

The DS1384 Watchdog Timekeeper Controller has 14 internal registers, which are 8 bits wide and contain all of the Timekeeping, Alarm, Watchdog, Control, and Data information. The Clock, Calendar, Alarm and Watchdog Registers are memory locations, which contain external (user accessible) and internal copies of the data. The ex ternal copies are independent of interna l functions except that they are updated periodically by the simultaneous transfer of the incremented internal copy (see Figure 1). The Command Register bits are affected by both internal and external functions. This register will be discussed later. The 50 bytes of RAM registers are accessed from t he external address and data bus and reside or overlay external static RAM. Registers 0, 1, 2, 4, 6, 8, 9 and A contain time of da y and date information (see Figure 2). Time of day information is stored in BCD. Registers 3, 5, and 7 contain the time of day alarm information. Time of day alarm information is stored in BCD. Register B is the Command Register and information in this register is binary. Register C and D ar e the Watchdog Alarm Registers and information, which is stored in these two registers, is in BCD. Registers 0000EH through register 0003FH are on-chip user bytes and can be used to contain data at the user’s discretion.

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DS1384 BLOCK DIAGRAM Figure 1

DS1384

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