The DS1338 serial real-time clock (RTC) is a lowpower, full binary-coded decimal (BCD)
clock/calendar plus 56 bytes of NV SRAM. Address
and data are transferred serially through an I
2
C™
interface. The clock/calendar provides seconds,
minutes, hours, day, date, month, and year
information. The end of the month date is
automatically adjusted for months with fewer than 31
days, including corrections for leap year. The clock
operates in either the 24-hour or 12-hour format with
AM/PM indicator. The DS1338 has a built-in powersense circuit that detects power failures and
automatically switches to the battery supply.
APPLICATIONS
Handhelds (GPS, POS Terminal)
Consumer Electronics (Set-Top Box, Digital
Recording, Network Appliance)
Office Equipment (Fax/Printer, Copier)
Medical (Glucometer, Medicine Dispenser)
Telecommunications (Router, Switcher, Server)
Other (Utility Meter, Vending Machine, Thermostat,
Modem)
TYPICAL OPERATING CIRCUIT
V
CPU
CC
RPURPU
RPU = tR / CB
V
CC
CRYSTAL
SCL
X2X1
V
CC
V
CC
SQW/OUT
i
DS1338
SDA
GND
V
BAT
DS1338
2
C RTC with 56-Byte NV RAM
I
FEATURES
§ RTC Counts Seconds, Minutes, Hours, Date of
the Month, Month, Day of the Week, and Year
with Leap-Year Compensation Valid Up to 2100
§ Available in a Surface-Mount Package with an
Integrated Crystal (DS1338C)
§ 56-Byte Battery-Backed NV RAM for Data
Storage
2
C Serial Interface
§ I
§ Programmable Square-Wave Output Signal
§ Automatic Power-Fail Detect and Switch Circuitry
§ Underwriters Laboratory (UL) Recognized
ORDERING INFORMATION
PART TEMP RANGE PIN-PACKAGE TOP MARK
DS1338Z-18 -40°C to +85°C 8 SO (150 mils) DS1338-18
DS1338Z-3 -40°C to +85°C 8 SO (150 mils) DS1338-3
DS1338Z-33 -40°C to +85°C 8 SO (150 mils) DS1338-33
DS1338U-18 -40°C to +85°C
DS1338U-3 -40°C to +85°C
DS1338U-33 -40°C to +85°C
DS1338C-18 -40°C to +85°C 16 SO (300 mils) DS1338C-18
DS1338C-3 -40°C to +85°C 16 SO (300 mils) DS1338C-3
DS1338C-33 -40°C to +85°C 16 SO (300 mils) DS1338C-33
rr = second line, revision level
Pin Configurations appear at end of data sheet.
I2C is a trademark of Philips Corp. Purchase of I2C components from
Maxim Integrated Products, Inc., or one of its sublicensed Associated
Companies, conveys a license under the Philips I
use these components in an I
conforms to the I
2
C Standard Specification as defined by Philips.
8 mSOP
8 mSOP
8 mSOP
2
C system, provided that the system
1338
rr-18
1338
rr-3
1338
rr-33
2
C Patent Rights to
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device
may be simultaneously available through various sales channels. For information about device errata, go to: www.maxim-ic.com/errata
.
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REV: 091404
DS1338 I2C RTC with 56-Byte NV RAM
ABSOLUTE MAXIMUM RATINGS
Voltage Range on Any Pin Relative to Ground………………………………………………………..……..-0.3V to +6.0V
Operating Temperature Range…………………………………………………………………………..……-40°C to +85°C
Storage Temperature Range………………………………………………………………………………...-55°C to +125°C
Soldering Temperature…………….....See precautions in the Handling, PC Board Layout, and Assembly Section
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is
not implied. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability.
Limits at -40°C are guaranteed by design and not production tested.
All voltages are referenced to ground.
SCL only.
SDA and SQW/OUT.
I
—SCL clocking at max frequency = 400kHz.
CCA
Specified with the I
Measured with a 32.768kHz crystal attached to X1 and X2.
After this period, the first clock pulse is generated.
A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the V
the undefined region of the falling edge of SCL.
The maximum t
A fast-mode device can be used in a standard-mode system, but the requirement t
automatically the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW
period of the SCL signal, it must output the next data bit to the SDA line t
is released.
C
—total capacitance of one bus line in pF.
B
Guaranteed by design. Not production tested.
The parameter t
0.0V ≤ V
This delay applies only if the oscillator is enabled and running. If the oscillator is disabled or stopped, no power-up delay occurs.
PF(MAX)
PF(MIN)
≤ V
CC
to V
to V
2
C bus inactive.
HD:DAT
is the time period the oscillator must be stopped for the OSF flag to be set over the voltage range of
OSF
and 1.3V ≤ V
CC MAX
t
PF(MIN)
t
PF(MAX)
need only be met if the device does not stretch the LOW period (t
≤ 3.7V.
BAT
Figure 1. Power-Up/Power-Down Timing
V
V
PF(max)
V
PF(min)
CC
2 ms
REC
300
VCCF
0
VCCR
of the SCL signal) to bridge
IHMIN
) of the SCL signal.
LOW
≥ to 250ns must then be met. This is
SU:DAT
R MAX
+ t
= 1000 + 250 = 1250ns before the SCL line
SU:DAT
ms
ms
INPUTS
OUTPUTS
t
VCCF
RECOGNIZED
VALID
t
VCCR
t
REC
DON'T CARE
RECOGNIZED
HIGH-Z
VALID
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Figure 2. Timing Diagram
A
A
8
DS1338 I2C RTC with 56-Byte NV RAM
Figure 3. Block Diagram
"C" VERSION
ONLY
X1
OSCILLATOR AND
X2
DIVIDER
POWER CONTROL
SCL
SDA
SERIAL BUS
INTERFACE AND
DDRESS
REGISTER
1Hz/4.096kHz/8.192kHz/32.768kHz
1Hz
CONTROL
LOGIC
Dallas
Semiconductor
DS133
MUX/
BUFFER
RAM
(56 x 8)
CLOCK,
CALENDAR,
ND CONTROL
REGISTERS
USER BUFFER
(7 BYTES)
SQW/OUT
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