Rainbow Electronics DS1338 User Manual

www.maxim-ic.com

GENERAL DESCRIPTION

The DS1338 serial real-time clock (RTC) is a low­power, full binary-coded decimal (BCD)
clock/calendar plus 56 bytes of NV SRAM. Address
and data are transferred serially through an I

2

C™
interface. The clock/calendar provides seconds,
minutes, hours, day, date, month, and year
information. The end of the month date is
automatically adjusted for months with fewer than 31
days, including corrections for leap year. The clock
operates in either the 24-hour or 12-hour format with
AM/PM indicator. The DS1338 has a built-in power­sense circuit that detects power failures and
automatically switches to the battery supply.

APPLICATIONS

Handhelds (GPS, POS Terminal)
Consumer Electronics (Set-Top Box, Digital

Recording, Network Appliance)
Office Equipment (Fax/Printer, Copier)
Medical (Glucometer, Medicine Dispenser)
Telecommunications (Router, Switcher, Server)
Other (Utility Meter, Vending Machine, Thermostat,

Modem)

TYPICAL OPERATING CIRCUIT

V

CPU

CC

RPU RPU

RPU = tR / CB

V

CC

CRYSTAL

SCL

X2 X1

V

CC

V

CC

SQW/OUT

i

DS1338

SDA

GND

V

BAT

DS1338

2

C RTC with 56-Byte NV RAM

I

FEATURES

§ RTC Counts Seconds, Minutes, Hours, Date of
the Month, Month, Day of the Week, and Year
with Leap-Year Compensation Valid Up to 2100

§ Available in a Surface-Mount Package with an
Integrated Crystal (DS1338C)

§ 56-Byte Battery-Backed NV RAM for Data
Storage

2

C Serial Interface

§ I

§ Programmable Square-Wave Output Signal

§ Automatic Power-Fail Detect and Switch Circuitry

§ Underwriters Laboratory (UL) Recognized

ORDERING INFORMATION

PART TEMP RANGE PIN-PACKAGE TOP MARK

DS1338Z-18 -40°C to +85°C 8 SO (150 mils) DS1338-18

DS1338Z-3 -40°C to +85°C 8 SO (150 mils) DS1338-3

DS1338Z-33 -40°C to +85°C 8 SO (150 mils) DS1338-33

DS1338U-18 -40°C to +85°C

DS1338U-3 -40°C to +85°C

DS1338U-33 -40°C to +85°C

DS1338C-18 -40°C to +85°C 16 SO (300 mils) DS1338C-18

DS1338C-3 -40°C to +85°C 16 SO (300 mils) DS1338C-3

DS1338C-33 -40°C to +85°C 16 SO (300 mils) DS1338C-33

rr = second line, revision level

Pin Configurations appear at end of data sheet.

I2C is a trademark of Philips Corp. Purchase of I2C components from
Maxim Integrated Products, Inc., or one of its sublicensed Associated
Companies, conveys a license under the Philips I
use these components in an I
conforms to the I

2

C Standard Specification as defined by Philips.

8 mSOP

8 mSOP

8 mSOP

2

C system, provided that the system

1338
rr-18
1338
rr-3
1338
rr-33

2

C Patent Rights to

Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device
may be simultaneously available through various sales channels. For information about device errata, go to: www.maxim-ic.com/errata

.

1 of 15

REV: 091404

DS1338 I2C RTC with 56-Byte NV RAM

ABSOLUTE MAXIMUM RATINGS

Voltage Range on Any Pin Relative to Ground………………………………………………………..……..-0.3V to +6.0V
Operating Temperature Range…………………………………………………………………………..……-40°C to +85°C
Storage Temperature Range………………………………………………………………………………...-55°C to +125°C

Soldering Temperature…………….....See precautions in the Handling, PC Board Layout, and Assembly Section

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is
not implied. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability.

RECOMMENDED DC OPERATING CONDITIONS

(VCC = V

Supply Voltage VCC

Logic 1 VIH (Note 2) 0.7 x VCC V

Logic 0 VIL (Note 2) -0.3 +0.3 x V

Power-Fail Voltage VPF

V

Battery Voltage V

BAT

CC(MIN)

to V

, TA = -40°C to +85°C.) (Note 1)

CC(MAX)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

DS1338-18 1.71 1.8 1.89
DS1338-3 2.7 3.0 3.3

V

DS1338-33 3.0 3.3 3.63

+ 0.3 V

CC

CC

V

DS1338-18 1.51 1.62 1.71
DS1338-3 2.45 2.59 2.70

V

DS1338-33 2.70 2.82 2.97

(Note 2) 1.3 3.0 3.7 V

BAT

DC ELECTRICAL CHARACTERISTICS

(VCC = V

CC(MIN)

to V

, TA = -40°C to +85°C.) (Note 1)

CC(MAX)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

V

Battery Voltage V

BAT

(Note 2) 1.3 3.7 V

BAT

Input Leakage ILI (Note 3) 1

I/O Leakage ILO (Note 4) 1

SDA Logic 0 Output I

OLSDA

VCC > 2V; VOL = 0.4V 3.0

< 2V; VOL = 0.2 VCC 3.0

V

CC

VCC > 2V; VOL = 0.4V 3.0

SQW/OUT Logic 0 Output I

OLSQW

1.71V < VCC < 2V;
= 0.2 VCC

V

OL

1.3V < V

V

= 0.2 VCC

OL

< 1.71V;

CC

3.0

250

DS1338-18 75 150

Active Supply Current (Note 5) I

CCA

DS1338-3 110 200
DS1338-33 120 200
DS1338-18 60 100

Standby Current (Note 6) I

CCS

DS1338-3 80 125
DS1338-33 85 125

V

Leakage Current

BAT

(V

Active)

CC

25 100 nA

I

BATLKG

mA

mA

mA

mA

mA

mA

mA

2 of 15

DC ELECTRICAL CHARACTERISTICS

(VCC = 0V, TA = -40°C to +85°C.) (Note 1)

PARAMETER SYMBOL MIN TYP MAX UNITS

V

Current (OSC ON); V

BAT

V

Current (OSC ON); V

BAT

= 3.7V, SQW/OUT OFF (Note 7) I

BAT

= 3.7V, SQW/OUT ON (32kHz)

BAT

(Note 7)

V

Data-Retention Current (Osc Off); V

BAT

= 3.7V (Note 7) I

BAT

AC ELECTRICAL CHARACTERISTICS

(TA = -40°C to +85°C) (Note 1)

PARAMETER SYMBOL CONDITION MIN TYP MAX UNITS

SCL Clock Frequency f

Bus Free Time Between STOP
and START Condition

Hold Time (Repeated) START
Condition (Note 8)

t

SCL

t

BUF

HD:STA

Fast mode 100 400

Standard mode 100

Fast mode 1.3

Standard mode 4.7

Fast mode 0.6

Standard mode 4.0

DS1338 I2C RTC with 56-Byte NV RAM

BATOSC1

I

BATOSC2

400 1200 nA

570 1400 nA

10 100 nA

BATDAT

kHz

ms

ms

LOW Period of SCL Clock t

HIGH Period of SCL Clock t

Setup Time for Repeated
START Condition

Data Hold Time (Notes 9, 10) t

Data Setup Time (Note 11) t

Rise Time of Both SDA and
SCL Signals (Note 12)

Fall Time of Both SDA and
SCL Signals (Note 12)

Setup Time for STOP
Condition

Capacitive Load for Each Bus
Line

Fast mode 1.3

LOW

Standard mode 4.7

ms

Fast mode 0.6

HIGH

Standard mode 4.0

ms

Fast mode 0.6

t

SU:STA

Standard mode 4.7

ms

Fast mode 0 0.9

HD:DAT

Standard mode 0

ms

Fast mode 100

SU:DAT

Standard mode 250

ns

Fast mode 20 + 0.1CB 300

t

R

Standard mode 20 + 0.1CB 1000

ns

Fast mode 20 + 0.1CB 300

t

F

t

SU:STO

C

(Note 12) 400 pF

B

Standard mode 20 + 0.1C

Fast mode 0.6

Standard mode 4.0

300

B

ns

ms

I/O Capacitance (SDA, SCL) C

Oscillator Stop Flag (OSF)
Delay

t

OSF

I/O

(Note 13) 10

(Note 14) 100

pF

ms

3 of 15

POWER-UP/POWER-DOWN CHARACTERISTICS

(TA = -40°C to +85°C) (Note 1, Figure 1)

PARAMETER SYMBOL MIN TYP MAX UNITS

DS1338 I2C RTC with 56-Byte NV RAM

Recovery at Power-Up (Note 15) t

VCC Fall Time; V

VCC Rise Time; V

Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Note 8:
Note 9:

Note 10:
Note 11:

Note 12:

Note 13:

Note 14:

Note 15:

Limits at -40°C are guaranteed by design and not production tested.
All voltages are referenced to ground.
SCL only.
SDA and SQW/OUT.
I

—SCL clocking at max frequency = 400kHz.

CCA

Specified with the I
Measured with a 32.768kHz crystal attached to X1 and X2.
After this period, the first clock pulse is generated.
A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the V

the undefined region of the falling edge of SCL.
The maximum t
A fast-mode device can be used in a standard-mode system, but the requirement t

automatically the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW
period of the SCL signal, it must output the next data bit to the SDA line t
is released.

C

—total capacitance of one bus line in pF.

B

Guaranteed by design. Not production tested.

The parameter t

0.0V ≤ V
This delay applies only if the oscillator is enabled and running. If the oscillator is disabled or stopped, no power-up delay occurs.

PF(MAX)

PF(MIN)

≤ V

CC

to V

to V

2

C bus inactive.

HD:DAT

is the time period the oscillator must be stopped for the OSF flag to be set over the voltage range of

OSF

and 1.3V ≤ V

CC MAX

t

PF(MIN)

t

PF(MAX)

need only be met if the device does not stretch the LOW period (t

≤ 3.7V.

BAT

Figure 1. Power-Up/Power-Down Timing

V

V

PF(max)

V

PF(min)

CC

2 ms

REC

300

VCCF

0

VCCR

of the SCL signal) to bridge

IHMIN

) of the SCL signal.

LOW

≥ to 250ns must then be met. This is

SU:DAT

R MAX

+ t

= 1000 + 250 = 1250ns before the SCL line

SU:DAT

ms

ms

INPUTS

OUTPUTS

t

VCCF

RECOGNIZED

VALID

t

VCCR

t

REC

DON'T CARE

RECOGNIZED

HIGH-Z

VALID

4 of 15

Figure 2. Timing Diagram

A

A

8

DS1338 I2C RTC with 56-Byte NV RAM

Figure 3. Block Diagram

"C" VERSION

ONLY

X1

OSCILLATOR AND

X2

DIVIDER

POWER CONTROL

SCL

SDA

SERIAL BUS

INTERFACE AND

DDRESS

REGISTER

1Hz/4.096kHz/8.192kHz/32.768kHz

1Hz

CONTROL

LOGIC

Dallas

Semiconductor

DS133

MUX/

BUFFER

RAM

(56 x 8)

CLOCK,

CALENDAR,
ND CONTROL
REGISTERS

USER BUFFER

(7 BYTES)

SQW/OUT

5 of 15

TYPICAL OPERATING CHARACTERISTICS

(VCC = 3.3V, TA = +25°C, unless otherwise noted.)

I

vs. V

BAT0SC1

1000

950

900

850

800

750

SUPPLY CURRENT (nA)

700

650

600

850

800

SUPPLY CURRENT (nA)

750

700

SQUARE-WAVE OFF

VCC = 0V

1.3 5.3

I

BAT0SC1

V

VCC = 0V

-40 80
TEMPERATURE ( C)

CC

V

(V)

BAT

vs. TEMPERATURE

= 3.0V

BAT

6040200-20

DS1338 toc01

4.84.31.8 2.3 2.8 3.3 3.8

DS1338 toc03

DS1338 I2C RTC with 56-Byte NV RAM

I

vs. V

1400

VCC = 0V

1350
1300
1250
1200
1150
1100
1050
1000

950

SUPPLY CURRENT (nA)

900
850
800
750
700

275

250

225

200

175

150

125

SUPPLY CURRENT (mA)

100

75

50

1.8

BAT0SC2

SQUARE-WAVE ON

I

CCA

SQUARE-WAVE ON

V

BAT

vs. V

VCC (V)

CC

DS1338 toc02

4.84.31.8 2.3 2.8 3.3 3.81.3 5.3

(V)

CC

DS1338 toc04

5.34.83.8 4.32.8 3.32.3

OSCILLATOR FREQUENCY vs. V

32767.75
VCC = 0V

32767.74

32767.73

32767.72

32767.71

32767.70

32767.69

FREQUENCY (Hz)

32767.68

32767.67

32767.66

32767.65

1.3

6 of 15

BAT

DS1338 toc05

V

(V)

BAT

5.34.83.8 4.32.3 2.8 3.31.8

PIN DESCRIPTION

PIN

8 16

1 — X1

2 — X2

3 14 V

4 15 GND

5 16 SDA

NAME FUNCTION

BAT

DS1338 I2C RTC with 56-Byte NV RAM

32.768kHz Crystal Connections. The internal oscillator circuitry is designed for
operation with a crystal having a specified load capacitance (C

) of 12.5pF. Pin

L

X1 is the input to the oscillator and can optionally be connected to an external

32.768kHz oscillator. The output of the internal oscillator, pin X2, is floated if an
external oscillator is connected to pin X1. An external 32.768kHz oscillator can
also drive the DS1338. In this configuration, the X1 pin is connected to the
external oscillator signal and the X2 pin is floated.

Note: For more information about crystal selection and crystal layout considerations,
refer to Application Note 58: Crystal Considerations with Dallas Real-Time Clocks.

+3V Battery Input. Backup supply input for any standard 3V lithium cell or other
energy source. Battery voltage must be held between the minimum and
maximum limits for proper operation. If a backup supply is not required, V
must be grounded. UL recognized to ensure against reverse charging when
used with a lithium battery.

Ground. DC power is provided to the device on these pins. V

is the primary

CC

power input. When voltage is applied within normal limits, the device is fully
accessible and data can be written and read. When a backup supply is
connected to the device and V

is below VPF, reads and writes are inhibited.

CC

However, the timekeeping function continues unaffected by the lower input
voltage.

2

Serial Data. Input/output pin for the I

C serial interface. It is open drain and

requires an external pullup resistor.

BAT

6 1 SCL Serial Clock. Used to synchronize data movement on the serial interface

Square-Wave/Output Driver. When enabled and the SQWE bit set to 1, the

7 2 SQW/OUT

SQW/OUT pin outputs one of four square-wave frequencies (1Hz, 4kHz, 8kHz,
32kHz). It is open drain and requires an external pullup resistor. Operates with
either V

CC

or V

applied.

BAT

Primary Power Supply. When voltage is applied within normal limits, the device
is fully accessible and data can be written and read. When a backup supply is

8 3 VCC

connected to the device and VCC is below VPF, reads and writes are inhibited.
However, the timekeeping function continues unaffected by the lower input
voltage.

— 4–13 N.C.

No Connect. These pins are not connected internally, but must be grounded for
proper operation.

DETAILED DESCRIPTION

The DS1338 serial RTC is a low-power, full BCD clock/calendar plus 56 bytes of NV SRAM. Address and data are
transferred serially through an I
month, and year information. The end of the month date is automatically adjusted for months with fewer than 31
days, including corrections for leap year. The clock operates in either the 24-hour or 12-hour format with AM/PM
indicator. The DS1338 has a built-in power-sense circuit that detects power failures and automatically switches to
the battery supply.

2

C interface. The clock/calendar provides seconds, minutes, hours, day, date,

7 of 15

DS1338 I2C RTC with 56-Byte NV RAM

OPERATION

The DS1338 operates as a slave device on the serial bus. Access is obtained by implementing a START condition
and providing a device identification code, followed by data. Subsequent registers can be accessed sequentially
until a STOP condition is executed. The device is fully accessible and data can be written and read when V
greater than V

V

is less than V

PF

than V

, the device power is switched from VCC to V

BAT

from the V

. However, when VCC falls below VPF, the internal clock registers are blocked from any access. If

PF

, the device power is switched from VCC to V

BAT

source until VCC is returned to nominal levels. The block diagram (Figure 3) shows the main elements

BAT

when VCC drops below V

BAT

when VCC drops below VPF. If VPF is greater

BAT

. The registers are maintained

BAT

CC

is

of the DS1338.

An enable bit in the seconds register controls the oscillator. Oscillator startup times are highly dependent upon
crystal characteristics, PC board leakage, and layout. High ESR and excessive capacitive loads are the major
contributors to long start-up times. A circuit using a crystal with the recommended characteristics and proper layout
usually starts within 1 second.

OSCILLATOR CIRCUIT

The DS1338 uses an external 32.768kHz crystal. The oscillator circuit does not require any external resistors or
capacitors to operate. Table 1 specifies several crystal parameters for the external crystal. Figure 4 shows a
functional schematic of the oscillator circuit. The startup time is usually less than 1 second when using a crystal
with the specified characteristics.

Table 1. Crystal Specifications*

PARAMETER SYMBOL MIN TYP MAX UNITS

Nominal Frequency fO 32.768 kHz

Series Resistance ESR 45

kW

Load Capacitance CL 12.5 pF

*The crystal, traces, and crystal input pins should be isolated from RF generating signals. Refer to

Application Note 58: Crystal Considerations for Dallas Real-Time Clocks for additional specifications.

Figure 4. Oscillator Circuit Showing Internal Bias Network

C L 1 C L 2

X1

CRYSTAL

RTC

COUNTDOWN

CHAIN

RTC

REGISTERS

X2

8 of 15

DS1338 I2C RTC with 56-Byte NV RAM

CLOCK ACCURACY

The accuracy of the clock is dependent upon the accuracy of the crystal and the accuracy of the match between
the capacitive load of the oscillator circuit and the capacitive load for which the crystal was trimmed. Crystal
frequency drift caused by temperature shifts creates additional error. External circuit noise coupled into the
oscillator circuit can result in the clock running fast. Figure 5 shows a typical PC board layout for isolating the
crystal and oscillator from noise. Refer to Application Note 58: Crystal Considerations with Dallas Real-Time Clocks
for detailed information.

DS1338C ONLY

The DS1338C integrates a standard 32,768Hz crystal in the package. Typical accuracy at nominal VCC and +25°C
is approximately 10ppm. Refer to Application Note 58 for information about crystal accuracy vs. temperature.

Figure 5. Typical PC Board Layout for Crystal

LOCAL GROUND PLANE (LAYER 2)

X1

CRYSTAL

X2

GND

NOTE: AVOID ROUTING SIGNALS IN THE CROSSHATCHED

AREA (UPPER LEFT-HAND QUADRANT) OF THE PACKAGE
UNLESS THERE IS A GROUND PLANE BETWEEN THE SIGNAL
LINE AND THE PACKAGE.

RTC AND RAM ADDRESS MAP

Figure 6 shows the address map for the RTC and RAM registers. The RTC registers and control register are
located in address locations 00h to 07h. The RAM registers are located in address locations 08h to 3Fh. During a
multibyte access, when the register pointer reaches 3Fh (the end of RAM space) it wraps around to location 00h
(the beginning of the clock space). On an I
current time and date is transferred to a second set of registers. The time and date in the secondary registers are
read in a multibyte data transfer, while the clock continues to run. This eliminates the need to re-read the registers
in case of an update of the main registers during a read.

2

C START, STOP, or register pointer incrementing to location 00h, the

9 of 15

DS1338 I2C RTC with 56-Byte NV RAM

CLOCK AND CALENDAR

The time and calendar information is obtained by reading the appropriate register bytes. See Figure 6 for the RTC
registers. The time and calendar are set or initialized by writing the appropriate register bytes. The contents of the
time and calendar registers are in the BCD format. Bit 7 of Register 0 is the clock halt (CH) bit. When this bit is set
to 1, the oscillator is disabled. When cleared to 0, the oscillator is enabled. The clock can be halted whenever the
timekeeping functions are not required, which decreases V

The day-of-week register increments at midnight. Values that correspond to the day of week are user-defined but
must be sequential (i.e., if 1 equals Sunday, then 2 equals Monday, and so on). Illogical time and date entries
result in undefined operation.

When reading or writing the time and date registers, secondary (user) buffers are used to prevent errors when the
internal registers update. When reading the time and date registers, the user buffers are synchronized to the
internal registers on any start or stop and when the register pointer rolls over to zero. The countdown chain is reset
whenever the seconds register is written. Write transfers occur on the acknowledge from the DS1338. Once the
countdown chain is reset, to avoid rollover issues the remaining time and date registers must be written within
1 second. The 1Hz square-wave output, if enabled, transitions high 500ms after the seconds data transfer,
provided the oscillator is already running.

Note that the initial power-on state of all registers, unless otherwise specified, is not defined. Therefore, it
is important to enable the oscillator (CH = 0) during initial configuration.

The DS1338 runs in either 12-hour or 24-hour mode. Bit 6 of the hours register is defined as the 12-hour or 24-hour
mode-select bit. When high, the 12-hour mode is selected. In the 12-hour mode, bit 5 is the
high being PM. In the 24-hour mode, bit 5 is the second 10-hour bit (20–23 hours). If the 12/
changed, the hours register must be re-initialized to the new format.

On an I2C START, the current time is transferred to a second set of registers. The time information is read from
these secondary registers, while the clock continues to run. This eliminates the need to re-read the registers in
case of an update of the main registers during a read.

Figure 6. RTC and RAM Address Map

current.

BAT

AM/PM bit, with logic

24-hour mode select is

ADDRESS BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 FUNCTION RANGE

00H CH 10 Seconds Seconds Seconds 00–59
01H 0 10 Minutes Minutes Minutes 00–59

02H 0

03H 0 0 0 0 0 Day Day 1–7
04H 0 0 10 Date Date Date 01–31

05H 0 0 0

06H 10 Year Year Year 00–99
07H OUT 0 OSF SQWE 0 0 RS1 RS0 Control

08H–3FH RAM 56 x 8 00H–FFH

Note: Bits listed as “0” always read as a 0.

12/24

AM/PM

10 Hour

10

Hour

10

Month

Hour Hours

Month Month 01–12

1–12

+AM/PM

00–23

10 of 15

DS1338 I2C RTC with 56-Byte NV RAM

Control Register (07h)

The control register controls the operation of the SQW/OUT pin and provides oscillator status.

BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

OUT 0 OSF SQWE 0 0 RS1 RS0

Bit 7: Output Control (OUT). Controls the output level of the SQW/OUT pin when the square-wave output is
disabled. If SQWE = 0, the logic level on the SQW/OUT pin is 1 if OUT = 1; it is 0 if OUT = 0.

Bit 5: Oscillator Stop Flag (OSF). A logic 1 in this bit indicates that the oscillator has stopped or was stopped for
some time period and can be used to judge the validity of the clock and calendar data. This bit is edge triggered,
and is set to logic 1 when the internal circuitry senses the oscillator has transitioned from a normal run state to a
STOP condition. The following are examples of conditions that may cause the OSF bit to be set:

1) The first time power is applied.

2) The voltage present on V

and V

CC

3) The CH bit is set to 1, disabling the oscillator.

4) External influences on the crystal (i.e., noise, leakage, etc.).

This bit remains at logic 1 until written to logic 0. This bit can only be written to logic 0. Attempting to write OSF to
logic 1 leaves the value unchanged.

Bit 4: Square-Wave Enable (SQWE). When set to logic 1, this bit enables the oscillator output to operate with
either V

CC

or V

applied. The frequency of the square-wave output depends upon the value of the RS0 and RS1

BAT

bits.

Bits 1 and 0: Rate Select (RS1 and RS0). These bits control the frequency of the square-wave output when the
square-wave output has been enabled. The table below lists the square-wave frequencies that can be selected
with the RS bits.

Square-Wave Output Frequency

RS1 RS0

0 0 1Hz
0 1 4.096kHz
1 0 8.192kHz
1 1 32.768kHz

SQW OUTPUT

FREQUENCY

are insufficient to support oscillation.

BAT

11 of 15

DS1338 I2C RTC with 56-Byte NV RAM

I2C SERIAL DATA BUS

The DS1338 supports the I2C protocol. A device that sends data onto the bus is defined as a transmitter and a
device receiving data is a receiver. The device that controls the message is called a master. The devices that are
controlled by the master are referred to as slaves. The bus must be controlled by a master device, which generates
the serial clock (SCL), controls the bus access, and generates the START and STOP conditions. The DS1338
operates as a slave on the I
mode (400kHz cycle rate) are defined. The DS1338 works in both modes. Connections to the bus are made
through the open-drain I/O lines SDA and SCL.

The following bus protocol has been defined (Figure 7).

§ Data transfer can be initiated only when the bus is not busy.

§ During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in the data

line while the clock line is HIGH are interpreted as control signals.

Accordingly, the following bus conditions have been defined:

Bus not busy: Both data and clock lines remain HIGH.

Start data transfer: A change in the state of the data line, from HIGH to LOW, while the clock is HIGH, defines a

START condition.

Stop data transfer: A change in the state of the data line, from LOW to HIGH, while the clock line is HIGH, defines
the STOP condition.

2

C bus. Within the bus specifications, a standard mode (100kHz cycle rate) and a fast

Data valid: The state of the data line represents valid data when, after a START condition, the data line is stable
for the duration of the HIGH period of the clock signal. The data on the line must be changed during the LOW
period of the clock signal. There is one clock pulse per bit of data.

Each data transfer is initiated with a START condition and terminated with a STOP condition. The number of data
bytes transferred between START and STOP conditions is not limited and is determined by the master device. The
information is transferred byte-wise and each receiver acknowledges with a ninth bit.

Acknowledge: Each receiving device, when addressed, is obliged to generate an acknowledge after the reception
of each byte. The master device must generate an extra clock pulse that is associated with this acknowledge bit.

A device that acknowledges must pull down the SDA line during the acknowledge clock pulse in such a way that
the SDA line is stable LOW during the HIGH period of the acknowledge-related clock pulse. Of course, setup and
hold times must be taken into account. A master must signal an end of data to the slave by not generating an
acknowledge bit on the last byte that has been clocked out of the slave. In this case, the slave must leave the data
line HIGH to enable the master to generate the STOP condition.

Figure 7. Data Transfer on I2C Serial Bus

12 of 15

DS1338 I2C RTC with 56-Byte NV RAM

Depending upon the state of the R/

W bit, two types of data transfer are possible:

1) Data transfer from a master transmitter to a slave receiver. The master transmits the first byte (the slave
address). Next follows a number of data bytes. The slave returns an acknowledge bit after each received byte.
Data is transferred with the most significant bit (MSB) first.

2) Data transfer from a slave transmitter to a master receiver. The master transmits the first byte (the slave
address). The slave then returns an acknowledge bit, which is followed by the slave transmitting a number of
data bytes. The master returns an acknowledge bit after all received bytes other than the last byte. At the end
of the last received byte, a “not acknowledge” is returned. The master device generates all of the serial clock
pulses and the START and STOP conditions. A transfer is ended with a STOP condition or with a repeated
START condition. Since a repeated START condition is also the beginning of the next serial transfer, the bus is
not released. Data is transferred with the most significant bit (MSB) first.

The DS1338 can operate in the following two modes:

1) Slave receiver mode (write mode): Serial data and clock are received through SDA and SCL. An
acknowledge bit is transmitted after each byte is received. START and STOP conditions are recognized as the
beginning and end of a serial transfer. Hardware performs address recognition after reception of the slave
address and direction bit (Figure 8). The slave address byte is the first byte received after the master
generates the START condition. The slave address byte contains the 7-bit DS1338 address—1101000—
followed by the direction bit (R/

W), which, for a write, is 0. After receiving and decoding the slave address byte,

the slave outputs an acknowledge on the SDA line. After the DS1338 acknowledges the slave address and
write bit, the master transmits a register address to the DS1338. This sets the register pointer on the DS1338,
with DS1338 acknowledging the transfer. The master may then transmit zero or more bytes of data, with the
DS1338 acknowledging each byte received. The register pointer increments after each data byte is transferred.
The master generates a STOP condition to terminate the data write.

2) Slave transmitter mode (read mode): The first byte is received and handled as in the slave receiver mode.
However, in this mode, the direction bit indicates that the transfer direction is reversed. The DS1338 transmits
serial data on SDA while the serial clock is input on SCL. START and STOP conditions are recognized as the
beginning and end of a serial transfer (Figure 9). The slave address byte is the first byte received after the
master generates the START condition. The slave address byte contains the 7-bit DS1338 address—
1101000—followed by the direction bit (R/

W), which, for a read, is 1. After receiving and decoding the slave

address byte, the slave outputs an acknowledge on the SDA line. The DS1338 then starts transmitting data
using the register address pointed to by the register pointer. If the register pointer is not set before the initiation
of a read mode, the first address that is read is the last one stored in the register pointer. The register pointer is
incremented after each byte is transferred. The DS1338 must receive a “not acknowledge” to end a read.

13 of 15

Figure 8. Data Write—Slave Receiver Mode

A

A

A

W

A

A

A

W

slave address

1101000

S

W

R/

register address (n)

0

XXXXXXXX AXXXXXXXX

Data (n) Data (n+1) Data (n+x)

S - START
A - ACKNOWLEDGE

P - STOP

- READ/WRITE OR DIRECTION BIT

R/

Figure 9. Data Read—Slave Transmitter Mode

DS1338 I2C RTC with 56-Byte NV RAM

XXXXXXXX

DATA TRANSFERRED

(X+1 BYTES + ACKNOWLEDGE)

XXXXXXXX

P

slave address

1101000

S

1

W

R/

Data (n) Data (n+1) Data (n+x) Data (n+2)

XXXXXXXX AXXXXXXXX

XXXXXXXX

XXXXXXXX /A

S - START

A - ACKNOWLEDGE

P - STOP

/A - NOT ACKNOWLEDGE

R/

- READ/WRITE OR DIRECTION BIT

DATA TRANSFERRED

(X+1 BYTES + ACKNOWLEDGE)

HANDLING, PC BOARD LAYOUT, AND ASSEMBLY

The DS1338C package contains a quartz tuning-fork crystal. Pick-and-place equipment may be used, but
precautions should be taken to ensure that excessive shocks are avoided. Ultrasonic cleaning should be avoided to
prevent damage to the crystal.

Avoid running signal traces under the package, unless a ground plane is placed between the package and the
signal line. All N.C. (no connect) pins must be connected to ground.

The SO package may be reflowed as long as the peak temperature does not exceed 240°C. Peak reflow
temperature (≥ 230°C) duration should not exceed 10 seconds, and the total time above 200°C should not exceed
40 seconds (30 seconds nominal). Exposure to reflow is limited to 2 times maximum.

Moisture-sensitive packages are shipped from the factory dry-packed. Handling instructions listed on the package
label must be followed to prevent damage during reflow. Refer to the IPC/JEDEC J-STD-020B standard for
moisture-sensitive device (MSD) classifications.

14 of 15

DS1338 I2C RTC with 56-Byte NV RAM

T

c

3

8

SO (300

PIN CONFIGURATIONS

TOP VIEW

X1

X2

V

BA

GND

1

8

3

6

DS1338

4

5

SO, µSOP

V

CC

SQW/OUT

SCL

SDA

TOP VIEW

SCL

SQW/OUT

V

N.C.

N.C.

N.C.

N.C.

N.C.

DS13

C

c

mils)

CHIP INFORMATION

TRANSISTOR COUNT: 12,231
PROCESS: CMOS

THERMAL INFORMATION

PART

THETA-J

(°C/W)

A

THETA-JC

(°C/W)

8 SO 170 40
8 µSOP 229 39
16 SO 73 23

PACKAGE INFORMATION

For the latest package outline information, go to www.maxim-ic.com/DallasPackInfo.

SDA
GND

V

BAT

N.C.
N.C.
N.C.
N.C.
N.C.

15 of 15

Maxim/Dallas Semiconductor cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim/Dallas Semiconductor product.
No circuit patent licenses are implied. Maxim/Dallas Semiconductor reserves the right to change the circuitry and specifications without notice at any time.

Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600

© 2004 Maxim Integrated Products · Printed USA

are registered trademarks of Maxim Integrated Products, Inc., and Dallas Semiconductor Corporation.