Rainbow Electronics DS1337 User Manual

www.maxim-ic.com

GENERAL DESCRIPTION

The DS1337 serial real-time clock is a low-power clock/calendar with two programmable time-of-day alarms and a programmable square-wave output. Address and data are transferred serially through an

C™ bus. The clock/calendar provides seconds, minutes, hours, day, date, month, and year information. The date at the end of the month is automatically adjusted for months with fewer than 31 days, including corrections for leap year. The clock operates in either the 24-hour or 12-hour format with AM/PM indicator.

APPLICATIONS

Handhelds (GPS, POS Terminal, MP3 Player)

Consumer Electronics (Set-Top Box, VCR/Digital

Recording) Office Equipment (Fax/Printer, Copier)

Medical (Glucometer, Medicine Dispenser)

Telecommunications (Router, Switch, Server)

Other (Utility Meter, Vending Machine, Thermostat,

Modem)

TYPICAL OPERATING CIRCUIT

RPU

CRYSTAL

DS1337

C Serial Real-Time Clock

FEATURES

§ Real-Time Clock (RTC) Counts Seconds, Minutes, Hours, Day, Date, Month, and Year with Leap-Year Compensation Valid Up to 2100

§ Available in a Surface-Mount Package with an Integrated Crystal (DS1337C)

§ I

C Serial Interface

§ Two Time-of-Day Alarms

§ Oscillator Stop Flag

§ Programmable Square-Wave Output

Defaults to 32kHz on Power-Up

§ Available in 8-Pin DIP, SO, or mSOP

ORDERING INFORMATION

PART TEMP RANGE PIN-PACKAGE

DS1337 -40°C to +85°C 8 DIP (300 mils) DS1337

DS1337S -40°C to +85°C 8 SO (150 mils) DS1337

DS1337U -40°C to +85°C DS1337C -40°C to +85°C 16 SO (300 mils) DS1337C

Pin Configurations appear at end of data sheet.

8 mSOP

TOP

MARK

1337

X2 X1

SCL

CPU

RPU = tR / CB

Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device may be simultaneously available through various sales channels. For information about device errata, go to: www.maxim-ic.com/errata

DS1337

SDA

GND

SQW/INT

INT

I2C is a trademark of Philips Corp. Purchase of I2C components from Maxim Integrated Products, Inc., or one of its sublicensed Associated Companies, conveys a license under the Philips I use these components in an I conforms to the I

C Standard Specification as defined by Philips.

C system, provided that the system

C Patent Rights to

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REV: 091404

DS1337 I2C Serial Real-Time Clock

ABSOLUTE MAXIMUM RATINGS

Voltage Range on Any Pin Relative to Ground…………………………………………………………...…-0.3V to +6.0V Operating Temperature Range……………………………………………………………………………….-40°C to +85°C Storage Temperature Range………………………………………………………………………………..-55°C to +125°C Soldering Temperature…………………..See precautions in the Handling, PC Board Layout, and Assembly section.

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability.

RECOMMENDED DC OPERATING CONDITIONS

(TA = -40°C to +85°C)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Supply Voltage

VCC 1.8 5.5 V

1.3 5.5 V

OSC

Logic 1 VIH

Logic 0 VIL

SCL, SDA 0.7 x VCC VCC + 0.3

INTA, SQW/INTB

-0.3 +0.3 x V

5.5

DC ELECTRICAL CHARACTERISTICS

(VCC = 1.8V to 5.5V, TA = -40°C to +85°C.) (Note 1)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Input Leakage ILI (Note 2) -1 +1

I/O Leakage ILO (Note 3) -1 +1

Logic 0 Output (VOL = 0.4V) IOL (Note 3) 3 mA

Active Supply Current I

Standby Current I

(Note 4) 150

CCA

(Notes 5, 6) 1.5

CCS

DC ELECTRICAL CHARACTERISTICS

(VCC = 1.3V to 1.8V, TA = -40°C to +85°C.) (Note 1)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Timekeeping Current (Oscillator Enabled)

Data-Retention Current (Oscillator Disabled)

(Notes 5, 7, 8, 9) 600 nA

OSC

(Note 5) 50 nA

DDR

2 of 15

AC ELECTRICAL CHARACTERISTICS

(VCC = 1.8V to 5.5V, TA = -40°C to +85°C.) (Note 1)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

DS1337 I2C Serial Real-Time Clock

SCL Clock Frequency f

Bus Free Time Between a STOP and START Condition

Hold Time (Repeated) START Condition (Note 10)

LOW Period of SCL Clock t

HIGH Period of SCL Clock t

Setup Time for a Repeated START Condition

(Notes 11, 12)

Data Setup Time (Note 13) t

Rise Time of Both SDA and SCL Signals (Note 14)

Fall Time of Both SDA and SCL Signals (Note 14)

Setup Time for STOP Condition

Capacitive Load for Each Bus Line

Fast mode 100 400

SCL

BUF

Standard mode 100 Fast mode 1.3

Standard mode 4.7

kHz

Fast mode 0.6

HD:STA

LOW

HIGH

SU:STA

HD:DAT

SU:DAT

SU:STO

Standard mode 4.0

Fast mode 1.3

Standard mode 4.7

Fast mode 0.6 Standard mode 4.0 Fast mode 0.6 Standard mode 4.7 Fast mode 0 0.9 Data Hold Time

Standard mode 0 Fast mode 100 Standard mode 250 Fast mode 20 + 0.1CB 300 Standard mode 20 + 0.1CB 1000 Fast mode 20 + 0.1CB 300

Standard mode 20 + 0.1C Fast mode 0.6 Standard mode 4.0

300

(Note 14) 400 pF

I/O Capacitance (SDA, SCL) C

Note 1:

Note 2: Note 3: Note 4: Note 5: Note 6: Note 7: Note 8: Note 9:

Note 10:

Note 11:

Note 12:

Note 13:

Note 14:

Note 15:

Limits at -40°C are guaranteed by design and are not production tested. SCL only. SDA, INTA, and SQW/INTB.

—SCL clocking at max frequency = 400kHz, VIL = 0.0V, VIH = V

CCA

Specified with the I2C bus inactive, VIL = 0.0V, VIH = V SQW enabled. Specified with the SQW function disabled by setting INTCN = 1. Using recommended crystal on X1 and X2.

The device is fully accessible when 1.8 £ VCC £ 5.5V. Time and date are maintained when 1.3V £ VCC £ 1.8V.

After this period, the first clock pulse is generated

A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the V bridge the undefined region of the falling edge of SCL.

The maximum t

A fast-mode device can be used in a standard-mode system, but the requirement t automatically the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line t line is released.

—total capacitance of one bus line in pF.

Guaranteed by design. Not production tested.

need only be met if the device does not stretch the LOW period (t

HD:DAT

(Note 15) 10 pF

I/O

CC.

of the SCL signal) to

IHMIN

) of the SCL signal.

LOW

³ to 250ns must then be met. This is

SU:DAT

R max + tSU:DAT

= 1000 + 250 = 1250ns before the SCL

3 of 15

TYPICAL OPERATING CHARACTERISTICS

VS. V

500

(SQUARE-WAVE OFF)

450

400

SUPPLY CURRENT (nA)

350

300

1.8

1.3

OSC

2.3

2.8

VCC (V)

DS1337 toc01

3.3

4.3

3.8

4.8

850

800

750

700

650

600

550

500

SUPPLY CURRENT (nA)

450

400

350

1.8

1.3

DS1337 I2C Serial Real-Time Clock

VS. V

OSC

(SQUARE-WAVE ON)

VCC (V)

DS1337 toc02

3.8

3.32.3 2.8

4.84.3

OSC

(SQUARE-WAVE OFF)

475

450

425

SUPPLY CURRENT (nA)

375

350

-40

VS. TEMPERATURE

VCC = 3.0V

TEMPERATURE (°C)

32767.75

32767.70

32767.65

32767.60

FREQUENCY (Hz)

32767.55

DS1337 toc03

806040200-20

SUPPLY CURRENT (µA)

1.8 5.3

OSCILLATOR FREQUENCY vs. V

VCC = 0V

vs. V

CCA

(SQUARE-WAVE ON)

VCC (V)

DS1337 toc05

DS1337 toc04

4.84.33.3 3.82.82.3

32767.50

32767.45

1.3 4.8 VCC (V)

5of16

4.33.83.32.82.31.8

PIN DESCRIPTION

8 16

1 — X1

2 — X2

3 14

4 15 GND DC power is provided to the device on these pins.

5 16 SDA

6 1 SCL

7 2

8 3 VCC DC power is provided to the device on these pins.

NAME FUNCTION

Connections for a Standard 32.768kHz Quartz Crystal. The internal oscillator circuitry is designed for operation with a crystal having a specified

INTA

SQW/

INTB

load capacitance (C and crystal layout considerations, refer to Application Note 58: Crystal Considerations with Dallas Real-Time Clocks. An external 32.768kHz oscillator can also drive the DS1337. In this configuration, the X1 pin is connected to the external oscillator signal and the X2 pin is floated.

Interrupt Output. When enabled, INTA is asserted low when the time/day/date matches the values set in the alarm registers. This pin is an open-drain output and requires an external pullup resistor.

Serial Data Input/Output. SDA is the input/output pin for the I interface. The SDA pin is open-drain output and requires an external pullup resistor.

Serial Clock Input. SCL is used to synchronize data movement on the serial interface.

Square-Wave/Interrupt Output. Programmable square-wave or interrupt output signal. It is an open-drain output and requires an external pullup resistor.

) of 6pF. For more information about crystal selection

DS1337 I2C Serial Real-Time Clock

C serial

— 4–13 N.C.

TIMING DIAGRAM

No Connect. These pins are not connected internally, but must be grounded for proper operation.

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DS1337 I2C Serial Real-Time Clock

INTA

BLOCK DIAGRAM

"C" VERSION

ONLY

SCL

SDA

OSCILLATOR

AND

DIVIDER

SERIAL BUS

INTERFACE AND

DDRESS

Dallas

Semiconductor

DS1337

1Hz/4.096kHz/8.192kHz/32.768kHz

1Hz

CONTROL

LOGIC

MUX/

BUFFER

LARM,

TRICKLE

CHARGE, AND

CONTROL

REGISTERS

CLOCK AND

CALENDAR

REGISTERS

USER BUFFER

(7 BYTES)

SQW/INT

OPERATION

The Block Diagram shows the main elements of the DS1337. As shown, communications to and from the DS1337 occur serially over an I implementing a START condition and providing a device identification code, followed by data. Subsequent registers can be accessed sequentially until a STOP condition is executed. The device is fully accessible when V is ³ 1.8V. The DS1337 maintains the time and date when V

C bus. The DS1337 operates as a slave device on the serial bus. Access is obtained by

is as low as 1.3V.

OSCILLATOR CIRCUIT

The DS1337 uses an external 32.768kHz crystal. The oscillator circuit does not require any external resistors or capacitors to operate. Table 1 specifies several crystal parameters for the external crystal. Figure 1 shows a functional schematic of the oscillator circuit. The startup time is usually less than 1 second when using a crystal with the specified characteristics.

Table 1. Crystal Specifications*

PARAMETER SYMBOL MIN TYP MAX UNITS

Nominal Frequency fO 32.768 kHz

Series Resistance ESR 45

Load Capacitance CL 6 pF

*The crystal, traces, and crystal input pins should be isolated from RF generating signals. Refer to

Application Note 58: Crystal Considerations for Dallas Real-Time Clocks for additional specifications.

6 of 15

DS1337 I2C Serial Real-Time Clock

Figure 1. Oscillator Circuit Showing Internal Bias Network

COUNTDOWN

CHAIN

DS1337

RTC

REGISTERS

CRYSTAL

CLOCK ACCURACY

The accuracy of the clock is dependent upon the accuracy of the crystal and the accuracy of the match between the capacitive load of the oscillator circuit and the capacitive load for which the crystal was trimmed. Crystal frequency drift caused by temperature shifts creates additional error. External circuit noise coupled into the oscillator circuit can result in the clock running fast. Figure 2 shows a typical PC board layout for isolating the crystal and oscillator from noise. Refer to Application Note 58: Crystal Considerations with Dallas Real-Time Clocks for detailed information.

Figure 2. Typical PC Board Layout for Crystal

LOCAL GROUND PLANE (LAYER 2)

CRYSTAL

NOTE: AVOID ROUTING SIGNALS IN THE CROSSHATCHED

AREA (UPPER LEFT-HAND QUADRANT) OF THE PACKAGE UNLESS THERE IS A GROUND PLANE BETWEEN THE SIGNAL LINE AND THE PACKAGE.

DS1337C ONLY

The DS1337C integrates a standard 32,768Hz crystal in the package. Typical accuracy at nominal VCC and +25°C is approximately 35ppm. Refer to Application Note 58 for information about crystal accuracy vs. temperature.

GND

7 of 15

DS1337 I2C Serial Real-Time Clock

ADDRESS MAP

Table 2 shows the address map for the DS1337 registers. During a multibyte access, when the address pointer reaches the end of the register space (0Fh) it wraps around to location 00h. On an I pointer incrementing to location 00h, the current time is transferred to a second set of registers. The time information is read from these secondary registers, while the clock may continue to run. This eliminates the need to re-read the registers in case of an update of the main registers during a read.

Table 2. Timekeeper Registers

ADDRESS BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 FUNCTION RANGE

00H 0 10 Seconds Seconds Seconds 00–59

01H 0 10 Minutes Minutes Minutes 00–59

02H 0

03H 0 0 0 0 0 Day Day 1–7

04H 0 0 10 Date Date Date 01–31

05H Century 0 0 10 Month Month

06H 10 Year Year Year 00–99

12/24

AM/PM

10 Hour

10 Hour Hour Hours

C START, STOP, or address

1–12

+AM/PM

00–23

Month/

Century

01–12 + Century

07H A1M1 10 Seconds Seconds

08H A1M2 10 Minutes Minutes

09H A1M3

0AH A1M4

0BH A2M2 10 Minutes Minutes

0CH A2M3

0DH A2M4

0EH

0FH OSF 0 0 0 0 0 A2F A1F Status —

EOSC

12/24

DY/DT

12/24

DY/DT

0 0 RS2 RS1 INTCN A2IE A1IE Control —

AM/PM

10 Hour

10 Date

AM/PM

10 Hour

10 Date

10 Hour Hour

Day

Date

10 Hour Hour

Day

Date

Note: Unless otherwise specified, the state of the registers is not defined when power is first applied or VCC falls below the V

Alarm 1

Seconds

Alarm 1

Minutes

Alarm 1

Hours

Alarm 1

Day

Alarm 1

Date

Alarm 2

Minutes

Alarm 2

Hours

Alarm 2

Day

Alarm 2

Date

00–59

1–12 +

AM/PM

00–23

1–7

1–31

00–59

1–12 +

AM/PM

00–23

1–7

1–31

OSC

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DS1337 I2C Serial Real-Time Clock

CLOCK AND CALENDAR

The time and calendar information is obtained by reading the appropriate register bytes. The RTC registers are illustrated in Table 2. The time and calendar are set or initialized by writing the appropriate register bytes. The contents of the time and calendar registers are in the binary-coded decimal (BCD) format.

The day-of-week register increments at midnight. Values that correspond to the day of week are user-defined but must be sequential (i.e., if 1 equals Sunday, then 2 equals Monday, and so on.). Illogical time and date entries result in undefined operation.

When reading or writing the time and date registers, secondary (user) buffers are used to prevent errors when the internal registers update. When reading the time and date registers, the user buffers are synchronized to the internal registers on any start or stop and when the register pointer rolls over to zero.

The countdown chain is reset whenever the seconds register is written. Write transfers occur on the acknowledge pulse from the device. To avoid rollover issues, once the countdown chain is reset, the remaining time and date registers must be written within 1 second. The 1Hz square-wave output, if enable, transitions high 500ms after the seconds data transfer, provided the oscillator is already running.

The DS1337 can be run in either 12-hour or 24-hour mode. Bit 6 of the hours register is defined as the 12- or 24-hour mode-select bit. When high, the 12-hour mode is selected. In the 12-hour mode, bit 5 is the with logic high being PM. In the 24-hour mode, bit 5 is the second 10-hour bit (20–23 hours). All hours values, including the alarms, must be reinitialized whenever the 12/ the month register) is toggled when the years register overflows from 99–00.

24-hour mode bit is changed. The century bit (bit 7 of

AM/PM bit

ALARMS

The DS1337 contains two time-of-day/date alarms. Alarm 1 can be set by writing to registers 07h–0Ah. Alarm 2 can be set by writing to registers 0Bh–0Dh. The alarms can be programmed (by the INTCN bit of the control register) to operate in two different modes—each alarm can drive its own separate interrupt output or both alarms can drive a common interrupt output. Bit 7 of each of the time-of-day/date alarm registers are mask bits (Table 2). When all of the mask bits for each alarm are logic 0, an alarm only occurs when the values in the timekeeping registers 00h–06h match the values stored in the time-of-day/date alarm registers. The alarms can also be programmed to repeat every second, minute, hour, day, or date. Table 3 shows the possible settings. Configurations not listed in the table result in illogical operation.

The DY/ register reflects the day of the week or the date of the month. If DY/ a match with date of the month. If DY/ week.

When the RTC register values match alarm register settings, the corresponding alarm flag (A1F or A2F) bit is set to logic 1. If the corresponding alarm interrupt enable (A1IE or A2IE) is also set to logic 1, the alarm condition activates one of the interrupt output ( update of the time and date registers.

DT bits (bit 6 of the alarm day/date registers) control whether the alarm value stored in bits 0–5 of that

DT is written to logic 0, the alarm is the result of

DT is written to logic 1, the alarm is the result of a match with day of the

INTA or SQW/INTB) signals. The match is tested on the once-per-second

9 of 15

DS1337 I2C Serial Real-Time Clock

Table 3. Alarm Mask Bits

ALARM 1 REGISTER MASK BITS

DY/DT

A1M4 A1M3 A1M2 A1M1

X 1 1 1 1 Alarm once per second X 1 1 1 0 Alarm when seconds match X 1 1 0 0 Alarm when minutes and seconds match X 1 0 0 0 Alarm when hours, minutes, and seconds match

0 0 0 0 0

1 0 0 0 0 Alarm when day, hours, minutes, and seconds match

ALARM 2 REGISTER MASK BITS

DY/DT

A2M4 A2M3 A2M2

X 1 1 1 Alarm once per minute (00 seconds of every minute) X 1 1 0 Alarm when minutes match X 1 0 0 Alarm when hours and minutes match

0 0 0 0 Alarm when date, hours, and minutes match 1 0 0 0 Alarm when day, hours, and minutes match

(BIT 7)

Alarm when date, hours, minutes, and seconds match

(BIT 7)

ALARM RATE

SPECIAL-PURPOSE REGISTERS

The DS1337 has two additional registers (control and status) that control the RTC, alarms, and square-wave output.

Control Register (0Eh)

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

EOSC

Enable Oscillator (EOSC). This active-low bit when set to logic 0 starts the oscillator. When this bit is set to

Bit 7:

logic 1, the oscillator is stopped. This bit is enabled (logic 0) when power is first applied.

Bits 4 and 3: Rate Select (RS2 and RS1). These bits control the frequency of the square-wave output when the square wave has been enabled. The table below shows the square-wave frequencies that can be selected with the RS bits. These bits are both set to logic 1 (32kHz) when power is first applied.

0 0 RS2 RS1 INTCN A2IE A1IE

Square-Wave Output Frequency

RS2 RS1

0 0 1Hz 0 1 4.096kHz 1 0 8.192kHz 1 1 32.768kHz

SQUARE-WAVE

OUTPUT FREQUENCY

Bit 2: Interrupt Control (INTCN). This bit controls the relationship between the two alarms and the interrupt output

pins. When the INTCN bit is set to logic 1, a match between the timekeeping registers and the alarm 1 registers l activates the alarm 2 registers activates the SQW/ logic 0, a match between the timekeeping registers and either alarm 1 or alarm 2 registers activates the

INTA pin (provided that the alarm is enabled) and a match between the timekeeping registers and the

INTB pin (provided that the alarm is enabled). When the INTCN bit is set to

INTA pin

10 of 15

DS1337 I2C Serial Real-Time Clock

(provided that the alarms are enabled). In this configuration, a square wave is output on the SQW/ bit is set to logic 0 when power is first applied.

Bit 1: Alarm 2 Interrupt Enable (A2IE). When set to logic 1, this bit permits the alarm 2 flag (A2F) bit in the status register to assert logic 0, the A2F bit does not initiate an interrupt signal. The A2IE bit is disabled (logic 0) when power is first applied.

Bit 0: Alarm 1 Interrupt Enable (A1IE). When set to logic 1, this bit permits the alarm 1 flag (A1F) bit in the status register to assert bit is disabled (logic 0) when power is first applied.

INTA (when INTCN = 0) or to assert SQW/INTB (when INTCN = 1). When the A2IE bit is set to

INTA. When the A1IE bit is set to logic 0, the A1F bit does not initiate the INTA signal. The A1IE

INTB pin. This

Status Register (0Fh)

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

OSF 0 0 0 0 0 A2F A1F

Bit 7: Oscillator Stop Flag (OSF). A logic 1 in this bit indicates that the oscillator either is stopped or was stopped for some period of time and may be used to judge the validity of the clock and calendar data. This bit is set to logic 1 anytime that the oscillator stops. The following are examples of conditions that can cause the OSF bit to be set:

1) The first time power is applied.

2) The voltage present on V

3) The

4) External influences on the crystal (e.g., noise, leakage, etc.).

This bit remains at logic 1 until written to logic 0.

Bit 1: Alarm 2 Flag (A2F). A logic 1 in the alarm 2 flag bit indicates that the time matched the alarm 2 registers. This flag can be used to generate an interrupt on either bit in the control register. If the INTCN bit is set to logic 0 and A2F is at logic 1 (and A2IE bit is also logic 1), the

INTA pin goes low. If the INTCN bit is set to logic 1 and A2F is logic 1 (and A2IE bit is also logic 1), the SQW/INTB

pin goes low. A2F is cleared when written to logic 0. This bit can only be written to logic 0. Attempting to write to logic 1 leaves the value unchanged.

EOSC bit is turned off.

is insufficient to support oscillation.

INTA or SQW/INTB depending on the status of the INTCN

Bit 0: Alarm 1 Flag (A1F). A logic 1 in the alarm 1 flag bit indicates that the time matched the alarm 1 registers. If the A1IE bit is also logic 1, the written to logic 0. Attempting to write to logic 1 leaves the value unchanged.

INTA pin goes low. A1F is cleared when written to logic 0. This bit can only be

11 of 15

DS1337 I2C Serial Real-Time Clock

I2C SERIAL DATA BUS

The DS1337 supports the I2C bus protocol. A device that sends data onto the bus is defined as a transmitter and a device receiving data as a receiver. The device that controls the message is called a master. The devices that are controlled by the master are referred to as slaves. A master device that generates the serial clock (SCL), controls the bus access, and generates the START and STOP conditions must control the bus. The DS1337 operates as a slave on the I (400kHz maximum clock rate) are defined. The DS1337 works in both modes. Connections to the bus are made through the open-drain I/O lines SDA and SCL.

The following bus protocol has been defined (Figure 3):

· Data transfer may be initiated only when the bus is not busy.

· During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in the data

line while the clock line is HIGH are interpreted as control signals.

Accordingly, the following bus conditions have been defined:

Bus not busy: Both data and clock lines remain HIGH.

Start data transfer: A change in the state of the data line, from HIGH to LOW, while the clock is HIGH, defines a

START condition.

Stop data transfer: A change in the state of the data line, from LOW to HIGH, while the clock line is HIGH, defines the STOP condition.

Data valid: The state of the data line represents valid data when, after a START condition, the data line is stable for the duration of the HIGH period of the clock signal. The data on the line must be changed during the LOW period of the clock signal. There is one clock pulse per bit of data.

Each data transfer is initiated with a START condition and terminated with a STOP condition. The number of data bytes transferred between START and STOP conditions are not limited, and are determined by the master device. The information is transferred byte-wise and each receiver acknowledges with a ninth bit.

Acknowledge: Each receiving device, when addressed, is obliged to generate an acknowledge after the reception of each byte. The master device must generate an extra clock pulse that is associated with this acknowledge bit.

A device that acknowledges must pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is stable LOW during the HIGH period of the acknowledge-related clock pulse. Of course, setup and hold times must be taken into account. A master must signal an end of data to the slave by not generating an acknowledge bit on the last byte that has been clocked out of the slave. In this case, the slave must leave the data line HIGH to enable the master to generate the STOP condition.

C bus. Within the bus specifications a standard mode (100kHz maximum clock rate) and a fast mode

12 of 15

DS1337 I2C Serial Real-Time Clock

Figure 3. Data Transfer on I2C Serial Bus

Depending upon the state of the R/W bit, two types of data transfer are possible:

1) Data transfer from a master transmitter to a slave receiver. The first byte transmitted by the master is the slave address. Next follows a number of data bytes. The slave returns an acknowledge bit after each received byte. Data is transferred with the most significant bit (MSB) first.

2) Data transfer from a slave transmitter to a master receiver. The master transmits the first byte (the slave address). The slave then returns an acknowledge bit, followed by the slave transmitting a number of data bytes. The master returns an acknowledge bit after all received bytes other than the last byte. At the end of the last received byte, a “not acknowledge” is returned. The master device generates all of the serial clock pulses and the START and STOP conditions. A transfer is ended with a STOP condition or with a repeated START condition. Since a repeated START condition is also the beginning of the next serial transfer, the bus is not released. Data is transferred with the most significant bit (MSB) first.

The DS1337 can operate in the following two modes:

1) Slave Receiver Mode (Write Mode): Serial data and clock are received through SDA and SCL. After each byte is received an acknowledge bit is transmitted. START and STOP conditions are recognized as the beginning and end of a serial transfer. Address recognition is performed by hardware after reception of the slave address and direction bit (Figure 4). The slave address byte is the first byte received after the master generates the START condition. The slave address byte contains the 7-bit DS1337 address, which is 1101000, followed by the direction bit (R/ the device outputs an acknowledge on the SDA line. After the DS1337 acknowledges the slave address + write bit, the master transmits a register address to the DS1337. This sets the register pointer on the DS1337. The master may then transmit zero or more bytes of data, with the DS1337 acknowledging each byte received. The address pointer will increment after each data byte is transferred. The master generates a STOP condition to terminate the data write.

2) Slave Transmitter Mode (Read Mode): The first byte is received and handled as in the slave receiver mode. However, in this mode, the direction bit indicates that the transfer direction is reversed. Serial data is transmitted on SDA by the DS1337 while the serial clock is input on SCL. START and STOP conditions are recognized as the beginning and end of a serial transfer (Figure 5). The slave address byte is the first byte received after the master generates a START condition. The slave address byte contains the 7-bit DS1337 address, which is 1101000, followed by the direction bit (R/ decoding the slave address byte the device outputs an acknowledge on the SDA line. The DS1337 then begins to transmit data starting with the register address pointed to by the register pointer. If the register pointer is not written to before the initiation of a read mode the first address that is read is the last one stored in the register pointer. The DS1337 must receive a “not acknowledge” to end a read.

W), which, for a write, is 0. After receiving and decoding the slave address byte

W), which, for a read, is 1. After receiving and

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DS1337 I2C Serial Real-Time Clock

Figure 4. Data Write—Slave Receiver Mode

Data (n) Data (n+1) Data (n+x)

XXXXXXXX

slave address

1101000

XXXXXXXX

S - START A - ACKNOWLEDGE P - STOP

- READ/WRITE OR DIRECTION BIT

DATA TRANSFERRED

(X + 1 BYTES + ACKNOWLEDGE)

Figure 5. Data Read—Slave Transmitter Mode

slave address

1101000

1 A

Data (n) Data (n+1) Data (n+x) Data (n+2)

XXXXXXXX

S - START A - ACKNOWLEDGE P - STOP /A - NOT ACKNOWLEDGE

- READ/WRITE OR DIRECTION BIT

DATA TRANSFERRED

(X + 1 BYTES + ACKNOWLEDGE)

HANDLING, PC BOARD LAYOUT, AND ASSEMBLY

The DS1337C package contains a quartz tuning-fork crystal. Pick-and-place equipment may be used, but precautions should be taken to ensure that excessive shocks are avoided. Ultrasonic cleaning should be avoided to prevent damage to the crystal.

Avoid running signal traces under the package, unless a ground plane is placed between the package and the signal line. All N.C. (no connect) pins must be connected to ground.

The SO package may be reflowed as long as the peak temperature does not exceed 240°C. Peak reflow temperature (≥ 230°C) duration should not exceed 10 seconds, and the total time above 200°C should not exceed 40 seconds (30 seconds nominal). Exposure to reflow is limited to 2 times maximum.

Moisture-sensitive packages are shipped from the factory dry-packed. Handling instructions listed on the package label must be followed to prevent damage during reflow. Refer to the IPC/JEDEC J-STD-020B standard for moisture-sensitive device (MSD) classifications.

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INTA

PIN CONFIGURATIONS

TOP VIEW

INT

GND

DS1337

DIP

DS1337

INT

GND

SO, mSOP

CHIP INFORMATION

TRANSISTOR COUNT: 10,950 PROCESS: CMOS

THERMAL INFORMATION

SQW/INTB

SCL

SDA

SQW/INT

SCL

SDA

DS1337 I2C Serial Real-Time Clock

SCL

SQW/INT

N.C.

DS1337C

SDA GND

N.C. N.C.

N.C.

SO (300 mils)

PACKAGE

THETA-J

(°C/W)

THETA-JC

(°C/W)

8 DIP 110 40 8 SO 170 40 8 µSOP 229 39 16 SO 73 23

PACKAGE INFORMATION

For the latest package outline information, go to www.maxim-ic.com/DallasPackInfo.

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Maxim/Dallas Semiconductor cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim/Dallas Semiconductor product. No circuit patent licenses are implied. Maxim/Dallas Semiconductor reserves the right to change the circuitry and specifications without notice at any time.

Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600

are registered trademarks of Maxim Integrated Products, Inc., and Dallas Semiconductor Corporation.

Rainbow Electronics DS1337 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual