Rainbow Electronics DS1315 User Manual

DS1315

PRELIMINARY

DS1315

Phantom Time Chip

FEATURES

• Real time clock keeps track of hundredths of seconds,

seconds, minutes, hours, days, date of the month,
months, and years

• Adjusts for months with fewer than 31 days

• Automatic leap year correction valid up to 2100

• No address space required to communicate with RTC

• Provides nonvolatile controller functions for battery

backup of SRAM

• Supports redundant battery attachment for high–reli-

ability applications

• Full ±10% V

operating range

CC

• +3.3 volt or +5 volt operation

• Industrial (–45°C to +85°C) operating temperature

ranges available

• Drop in replacement for DS1215

ORDERING INFORMATION

DS1315XX–XX

33–3.3 volt operation
5–5 volt operation

blank–commercial temp range
N–industrial temp range

blank–16–pin DIP
S–16–pin SOIC
E–20–pin TSSOP

PIN ASSIGNMENT

X1
X2

WE

BAT1

GND

D
Q

GND

16–PIN DIP (300 MIL)

X1
X2

WE

BAT1

GND

D
Q

GND

16–PIN SOIC (300 MIL)

X1

X2
WE
NC

BAT1

GND

NC

D

Q

GND

1

16

2

15

3

14

4

13

5

12

6

11

7

10

8

1
2
3
4
5
6
7
8

16
15
14
13
12
11
10

1
2
3
4
5
6
7
8
9
10

20–PIN TSSOP

9

20
19
18
17
16
15
14
13
12
11

9

V

CCI

V

CCO

BAT2
RST
OE
CEI
CEO
ROM/RAM

V

CCI

V

CCO

BAT2
RST
OE
CEI
CEO
ROM/RAM

V

CCI

V

CCO

BAT2
NC
RST
OE
NC
CEI
CEO
ROM/RAM

Copyright 1995 by Dallas Semiconductor Corporation.
All Rights Reserved. For important information regarding
patents and other intellectual property rights, please refer to
Dallas Semiconductor data books.

041697 1/22

DS1315

PIN DESCRIPTION

X1, X2 – 32.768 KHz Crystal Connection
WE – Write Enable
BAT1 – Battery 1 Input
GND – Ground
D – Data Input
Q – Data Output
ROM/RAM

– ROM/RAM Mode Select
CEO – Chip Enable Output
CEI – Chip Enable Input
OE

– Output Enable
RST – Reset
BAT2 – Battery 2 Input
V
V

CCO
CCI

– Switched Supply Output

– Power Supply Input

DESCRIPTION

The DS1315 Phantom Time Chip is a combination of a
CMOS timekeeper and a nonvolatile memory controller.

TIMING BLOCK DIAGRAM Figure 1

32.768 KHz

ROM/RAM

CEO

CEI

OE

WE

RST

CONTROL

LOGIC

POWER–FAIL

READ

WRITE

X

1

X

2

In the absence of power, an external battery maintains
the timekeeping operation and provides power for a
CMOS static RAM. The watch keeps track of hun­dredths of seconds, seconds, minutes, hours, day, date,
month, and year information. The last day of the month
is automatically adjusted for months with less than
31 days, including leap year correction. The watch oper­ates in one of two formats: a 12–hour mode with an
AM/PM indicator or a 24–hour mode. The nonvolatile
controller supplies all the necessary support circuitry to
convert a CMOS RAM to a nonvolatile memory. The
DS1315 can be interfaced with either RAM or ROM
without leaving gaps in memory .

OPERATION

The block diagram of Figure 1 illustrates the main ele­ments of the Time Chip. The following paragraphs
describe the signals and functions.

CLOCK/CALENDAR LOGIC

UPDATE

TIMEKEEPING REGISTER

041697 2/22

ACCESS

ENABLE
SEQUENCE
DETECTOR

D

Q

I/O BUFFERS

V

CCI

DATA

POWER–FAIL

DETECT

LOGIC

BAT

1

BAT

INTERNAL V

2

COMPARISON REGISTER

CC

V

CCO

DS1315

Communication with the Time Chip is established by
pattern recognition of a serial bit stream of 64 bits which
must be matched by executing 64 consecutive write
cycles containing the proper data on data in (D). All
accesses which occur prior to recognition of the 64–bit
pattern are directed to memory via the chip enable out­put pin (CEO

).

After recognition is established, the next 64 read or write
cycles either extract or update data in the Time Chip and
CEO

remains high during this time, disabling the con-

nected memory.

Data transfer to and from the timekeeping function is
accomplished with a serial bit stream under control of
chip enable input (CEI

), output enable (OE), and write
enable (WE). Initially , a read cycle using the CEI and OE
control of the Time Chip starts the pattern recognition
sequence by moving pointer to the first bit of the 64–bit
comparison register. Next, 64 consecutive write cycles
are executed using the CEI

and WE control of the Time
Chip. These 64 write cycles are used only to gain
access to the Time Chip.

When the first write cycle is executed, it is compared to
bit 1 of the 64–bit comparison register. If a match is

found, the pointer increments to the next location of the
comparison register and awaits the next write cycle. If a
match is not found, the pointer does not advance and all
subsequent write cycles are ignored. If a read cycle oc­curs at any time during pattern recognition, the present
sequence is aborted and the comparison register point­er is reset. Pattern recognition continues for a total of 64
write cycles as described above until all the bits in the
comparison register have been matched. (This bit pat­tern is shown in Figure 2). With a correct match for
64 bits, the Time Chip is enabled and data transfer to or
from the timekeeping registers may proceed. The next
64 cycles will cause the Time Chip to either receive data
on D, or transmit data on Q, depending on the level of
OE

pin or the WE pin. Cycles to other locations outside

the memory block can be interleaved with CEI

cycles
without interrupting the pattern recognition sequence or
data transfer sequence to the Time Chip.

A standard 32,768 KHz quartz crystal can be directly
connected to the DS1315 via pins 1 and 2 (X1, X2). The
crystal selected for use should have a specified load ca­pacitance (C

) of 6 pF . For more information on crystal

L

selection and crystal layout considerations, please con­sult Application Note 58, “Crystal Considerations with
Dallas Real Time Clocks”.

041697 3/22

DS1315

TIME CHIP COMPARISON REGISTER DEFINITION Figure 2

76543210

BYTE 0

BYTE 1

BYTE 2

BYTE 3

BYTE 4

BYTE 5

BYTE 6

11000101

00111010

10100011

01011100

11000101

00111010

10100011

C5

3A

A3

5C

C5

3A

A3

BYTE 7

01011100

5C

NOTE:

The pattern recognition in Hex is C5, 3A, A3, 5C, C5, 3A, A3, 5C. The odds of this pattern being accidentally duplicated
and causing inadvertent entry to the Phantom Time Chip are less than 1 in 10

NONVOLATILE CONTROLLER OPERATION

The operation of the nonvolatile controller circuits within
the Time Chip is determined by the level of the
ROM/RAM select pin. When ROM/RAM is connected to
ground, the controller is set in the RAM mode and per­forms the circuit functions required to make CMOS RAM
and the timekeeping function nonvolatile. A switch is
provided to direct power from the battery inputs or V
to V

with a maximum voltage drop of 0.3 volts. The

CCO

V

output pin is used to supply uninterrupted power

CCO

to CMOS SRAM. The DS1315 also performs redundant
battery control for high reliability. On power–fail, the bat­tery with the highest voltage is automatically switched to

. If only one battery is used in the system, the un-

V

CCO

The DS1315 safeguards the Time Chip and RAM data
by power–fail detection and write protection. Power–fail
detection occurs when V
by an internal bandgap reference. The DS1315 con­stantly monitors the V
than VPF, power–fail circuitry forces the chip enable out­put (CEO
write protection. During nominal supply conditions,

CCI

) to V

CEO will track CEI with a maximum propagation delay
of 5 ns. Internally, the DS1315 aborts any data transfer
in progress without changing any of the Time Chip regis­ters and prevents future access until V
A typical RAM/Time Chip interface is illustrated in
Figure 3.

used battery input should be connected to ground.

041697 4/22

CCI

19

.

falls below VPF which is set

CCI

supply pin. When V

CCI

or V

–0.2 volts for external RAM

BAT

CCI

exceeds VPF.

CCI

is less

DS1315

When the ROM/RAM pin is connected to V

CCO

, the con­troller is set in the ROM mode. Since ROM is a read–
only device that retains data in the absence of power,
battery backup and write protection is not required. As a
result, the chip enable logic will force CEO

low when

DS1315 TO RAM/TIME CHIP INTERFACE Figure 3

CMOS STATIC RAM

A0 – AN

WE

OE

CE

RST

BAT

1

A0 – AN

DATA I/O

WE

OE

CE

V

CC

DS1315

CEO

V

CCO

OE

WE

CEI

RST

BAT

X

12

32.768 KHz

D

Q

V

CCI

ROM/

RAM

BAT

1

2

X

1

2

power fails. However, the Time Chip does retain the
same internal nonvolatility and write protection as de­scribed in the RAM mode. A typical ROM/Time Chip in­terface is illustrated in Figure 4.

D0 – D7

V

CC

++

BAT

2

041697 5/22

DS1315

ROM/TIME CHIP INTERFACE Figure 4

A0 – AN

ROM

A1, A3 – AN

DATA I/O

A2

V

CC

V

CC

D0 – D7

OE

A0

DS1315

D
OE
WE

CEI
RST

BAT

1

X

1

32.768 KHz

CE

RST

OE

BAT

1

TIME CHIP REGISTER INFORMATION

Time Chip information is contained in eight registers of
8 bits, each of which is sequentially accessed one bit at
a time after the 64–bit pattern recognition sequence has
been completed. When updating the Time Chip regis­ters, each must be handled in groups of 8 bits. Writing
and reading individual bits within a register could pro­duce erroneous results. These read/write registers are
defined in Figure 5.

Data contained in the Time Chip registers is in binary
coded decimal format (BCD). Reading and writing the
registers is always accomplished by stepping though all
eight registers, starting with bit 0 of register 0 and ending
with bit 7 of register 7.

CE

CEO

Q

V

CCI

V

CCO

ROM/

RAM

BAT

2

X

2

V

CC

++

BAT

2

with logic high being PM. In the 24–hour mode, bit 5 is
the second 10–hour bit (20–23 hours).

OSCILLATOR AND RESET BITS

Bits 4 and 5 of the day register are used to control the
reset and oscillator functions. Bit 4 controls the reset pin
input. When the reset bit is set to logic 1, the reset input
pin is ignored. When the reset bit is set to logic 0, a low
input on the reset pin will cause the Time Chip to abort
data transfer without changing data in the timekeeping
registers. Reset operates independently of all other in­puts. Bit 5 controls the oscillator. When set to logic 0, the
oscillator turns on and the real time clock/calendar
begins to increment.

AM–PM/12/24 MODE

Bit 7 of the hours register is defined as the 12– or
24–hour mode select bit. When high, the 12–hour mode
is selected. In the 12–hour mode, bit 5 is the AM/PM bit

041697 6/22

ZERO BITS

Registers 1, 2, 3, 4, 5, and 6 contain one or more bits that
will always read logic 0. When writing these locations,
either a logic 1 or 0 is acceptable.

TIME CHIP REGISTER DEFINITION Figure 5

REGISTER

7654 3210

0

0.1 SEC

0.01 SEC

RANGE

(BCD)

00–99

DS1315

1

2

3

4

5

6

7

0

0

12/24 0

00 0

00

0 0 0 10 MONTH

10 SEC SECONDS

10 MIN MINUTES

10

OSC RST

10 YEAR YEAR

HR

A/P

10 DATE DATE

MONTH

HOUR

DAY

00–59

00–59

01–12
00–23

01–07

01–31

01–12

00–99

041697 7/22