Rainbow Electronics DS1306 User Manual
www.maxim-ic.com
DS1306
Serial Alarm Real-Time Clock
FEATURES
§ Real-time clock (RTC) counts seconds,
minutes, hours, date of the month, month,
day of the week, and year with leap-year
compensation valid up to 2100
§ 96-byte, battery-backed NV RAM for data
storage
§ Two time-of-day alarms, programmable on
combination of seconds, minutes, hours, and
day of the week
§ 1Hz and 32.768kHz clock outputs
§ Serial interface supports Motorola SPI
(serial peripheral interface) serial data ports
or standard 3-wire interface
§ Burst mode for reading/writing successive
addresses in clock/RAM
§ Dual-power supply pins for primary and
backup power supplies
§ Optional trickle charge output to backup
supply
§ 2.0V to 5.5V operation
§ Optional industrial temperature range:
-40°C to +85°C
§ Available in space-efficient, 20-pin TSSOP
package
§ Underwriters Laboratory (UL) recognized
™
PIN ASSIGNMENT
V
CC2
V
BAT
X1
NC
X2
NC
INT0
INT1
1Hz
GND
1
2
3
4
5
6
7
8
9
10
DS1306 20-Pin TSSOP (4.4mm)
CC2
BAT
X1
X2
1Hz
1
2
3
4
5
6
7
8
V
V
INT0
INT1
GND
DS1306 16-Pin DIP (300mil)
20
19
18
17
16
15
14
13
12
11
16
15
14
13
12
11
10
9
V
CC1
NC
32kHz
V
CCIF
SDO
SDI
SCLK
NC
CE
SERMODE
V
CC1
32kHz
V
CCIF
SDO
SDI
SCLK
CE
SERMODE
Package Dimension Information
http://www.maxim-ic.com/TechSupport/DallasPackInfo.htm
ORDERING INFORMATION
DS1306 16-Pin DIP (300mil)
DS1306N 16-Pin DIP (Industrial)
DS1306E 20-Pin TSSOP (4.4mm)
DS1306EN 20-Pin TSSOP (Industrial)
SPI is a trademark of Motorola, Inc.
TYPICAL OPERATING CIRCUIT
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DS1306
PIN DESCRIPTION
V
- Primary Power Supply
CC1
V
- Backup Power Supply
CC2
V
- +3V Battery Input
BAT
V
- Interface Logic Power-Supply Input
CCIF
GND - Ground
X1, X2 - 32.768kHz Crystal Connection
INT0 - Interrupt 0 Output
INT1 - Interrupt 1 Output
SDI - Serial Data In
SDO - Serial Data Out
CE - Chip Enable
SCLK - Serial Clock
SERMODE - Serial Interface Mode
1Hz - 1Hz Output
32kHz - 32.768kHz Output
DESCRIPTION
The DS1306 serial alarm real-time clock (RTC) provides a full binary coded decimal (BCD) clock
calendar that is accessed by a simple serial interface. The clock/calendar provides seconds, minutes,
hours, day, date, month, and year information. The end of the month date is automatically adjusted for
months with fewer than 31 days, including corrections for leap year. The clock operates in either the 24hour or 12-hour format with AM/PM indicator. In addition, 96 bytes of NV RAM are provided for data
storage.
An interface logic-power supply input pin (V
) allows the DS1306 to drive SDO and 32kHz pins to a
CCIF
level that is compatible with the interface logic. This allows an easy interface to 3V logic in mixed supply
systems. The DS1306 offers dual-power supplies as well as a battery-input pin. The dual-power supplies
support a programmable trickle charge circuit that allows a rechargeable energy source (such as a super
cap or rechargeable battery) to be used for a backup supply. The V
pin allows the device to be backed
BAT
up by a non-rechargeable battery. The DS1306 is fully operational from 2.0V to 5.5V.
Two programmable time-of-day alarms are provided by the DS1306. Each alarm can generate an
interrupt on a programmable combination of seconds, minutes, hours, and day. “Don’t care” states can be
inserted into one or more fields if it is desired for them to be ignored for the alarm condition. A 1Hz and a
32kHz clock output are also available.
The DS1306 supports a direct interface to SPI serial data ports or standard 3-wire interface. An easy-touse address and data format is implemented in which data transfers can occur 1 byte at a time or in
multiple-byte burst mode.
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DS1306
OPERATION
The block diagram in Figure 1 shows the main elements of the serial alarm RTC. The following
paragraphs describe the function of each pin.
Figure 1. BLOCK DIAGRAM
OSCILLAT OR AND
COUNTDOWN CHAIN
1Hz
SIGNAL DESCRIPTIONS
V
– DC power is provided to the device on this pin. V
CC1
V
– This is the secondary power supply pin. In systems using the trickle charger, the rechargeable
CC2
energy source is connected to this pin.
V
– Battery input for any standard 3V lithium cell or other energy source. UL recognized to ensure
BAT
against reverse charging current when used in conjunction with a lithium battery.
See “Conditions of Acceptability” at http://www.maxim-ic.com/TechSupport/QA/ntrl.htm.
V
(Interface Logic Power Supply Input) – The V
CCIF
32kHz output pins to a level that is compatible with the interface logic, thus allowing an easy interface to
3V logic in mixed supply systems. This pin is physically connected to the source connection of the pchannel transistors in the output buffers of the SDO and 32kHz pins.
SERMODE (Serial Interface Mode Input) – The SERMODE pin offers the flexibility to choose
between two serial interface modes. When connected to GND, standard 3-wire communication is
selected. When connected to V
, SPI communication is selected.
CC
SCLK (Serial Clock Input) – SCLK is used to synchronize data movement on the serial interface for
either the SPI or 3-wire interface.
is the primary power supply.
CC1
pin allows the DS1306 to drive SDO and
CCIF
SDI (Serial Data Input) – When SPI communication is selected, the SDI pin is the serial data input for
the SPI bus. When 3-wire communication is selected, this pin must be tied to the SDO pin (the SDI and
SDO pins function as a single I/O pin when tied together).
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DS1306
SDO (Serial Data Output) – When SPI communication is selected, the SDO pin is the serial data output
for the SPI bus. When 3-wire communication is selected, this pin must be tied to the SDI pin (the SDI and
SDO pins function as a single I/O pin when tied together). V
provides the logic high level.
CCIF
CE (Chip Enable) – The chip enable signal must be asserted high during a read or a write for both 3wire and SPI communication. This pin has an internal 55k pulldown resistor (typical).
INT0 (Interrupt 0 Output) – The INT0 pin is an active-low output of the DS1306 that can be used as an
interrupt input to a processor. The
INT0 pin can be programmed to be asserted by Alarm 0. The INT0 pin
remains low as long as the status bit causing the interrupt is present and the corresponding interrupt
enable bit is set. The INT0 pin operates when the DS1306 is powered by V
CC1
, V
CC2
, or V
. The INT0
BAT
pin is an open-drain output and requires an external pullup resistor.
1Hz (1Hz Clock Output) – The 1Hz pin provides a 1Hz square wave output. This output is active when
the 1 Hz bit in the control register is a logic 1.
Both INT0 and 1Hz pins are open-drain outputs. The interrupt, 1Hz signal, and the internal clock continue
to run regardless of the level of VCC (as long as a power source is present).
INT1 (Interrupt 1 Output) – The INT1 pin is an active high output of the DS1306 that can be used as an
interrupt input to a processor. The INT1 pin can be programmed to be asserted by Alarm 1. When an
alarm condition is present, the INT1 pin generates a 62.5ms active-high pulse. The INT1 pin operates
only when the DS1306 is powered by V
V
CC2
or V
. When inactive, the INT1 pin is internally pulled low.
BAT
CC2
or V
. When active, the INT1 pin is internally pulled up to
BAT
32kHz (32.768kHz Clock Output) – The 32kHz pin provides a 32.768kHz output. This signal is always
present. V
provides the logic high level.
CCIF
X1, X2 – Connections for a standard 32.768kHz quartz crystal. The internal oscillator is designed for
operation with a crystal having a specified load capacitance of 6pF. For more information on crystal
selection and crystal layout considerations, refer to Application Note 58, “Crystal Considerations with
Dallas Real-Time Clocks.” The DS1306 can also be driven by an external 32.768kHz oscillator. In this
configuration, the X1 pin is connected to the external oscillator signal and the X2 pin is floated.
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DS1306
RECOMMENDED LAYOUT FOR CRYSTAL
CLOCK ACCURACY
The accuracy of the clock is dependent upon the accuracy of the crystal and the accuracy of the match
between the capacitive load of the oscillator circuit and the capacitive load for which the crystal was
trimmed. Additional error is added by crystal frequency drift caused by temperature shifts. External
circuit noise coupled into the oscillator circuit can result in the clock running fast. Refer to Application
Note 58, “Crystal Considerations with Dallas Real-Time Clocks” for detailed information.
CLOCK, CALENDAR, AND ALARM
The time and calendar information is obtained by reading the appropriate register bytes. The RTC
registers are illustrated in Figure 2. The time, calendar, and alarm are set or initialized by writing the
appropriate register bytes. Note that some bits are set to 0. These bits always read 0 regardless of how
they are written. Also note that registers 12h to 1Fh (read) and registers 92h to 9Fh are reserved. These
registers always read 0 regardless of how they are written. The contents of the time, calendar, and alarm
registers are in the BCD format.
WRITING TO THE CLOCK REGISTERS
The internal time and date registers continue to increment during write operations. However, the
countdown chain is reset when the seconds register is written. Writing the time and date registers within
one second after writing the seconds register ensures consistent data.
Terminating a write before the last bit is sent aborts the write for that byte.
READING FROM THE CLOCK REGISTERS
Buffers are used to copy the time and date register at the beginning of a read. When reading in burst
mode, the user copy is static while the internal registers continue to increment.
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Figure 2. RTC REGISTERS AND ADDRESS MAP
DS1306
HEX ADDRESS
READ
00H 80H 0 10 SEC SEC 00–59
01H 81H 0 10 MIN MIN 00–59
02H 82H 0
03H 83H 0 0 0 0 0 DAY 01–07
04H 84H 0 0 10-DATE DATE 1–31
05H 85H 0 0 10-MONTH MONTH 01–12
06H 86H 10-YEAR YEAR 00–99
07H 87H M 10-SEC ALARM 0 SEC ALARM 0 00–59
08H 88H M 10-MIN ALARM 0 MIN ALARM 0 00–59
09H 89H M
0AH 8AH M 0 0 0 0 DAY ALARM 0 01–07
0BH 8BH M 10 SEC ALARM 1 SEC ALARM 1 00–59
0CH 8CH M 10 MIN ALARM 1 MIN ALARM 1 00–59
0DH 8DH M
0EH 8EH M 0 0 0 0 DAY ALARM 1 01–07
0FH 8FH CONTROL REGISTER —
10H 90H STATUS REGISTER —
11H 91H TRICKLE CHARGER REGISTER —
12–1FH 92–9FH RESERVED —
20–7FH A0–FFH 96-BYTES USER RAM —
WRITE
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 RANGE
12
24 10
12
24 10
12
24 10
P
A
10-HR HOURS
P
A
10-HR HOUR ALARM 0
P
A
10-HR HOUR ALARM 1
—
01–12 + P/A
00–23
01–12 + P/A
00–23
01–12 + P/A
00–23
Note: Range for alarm registers does not include mask’m’ bits.
The DS1306 can be run in either 12-hour or 24-hour mode. Bit 6 of the hours register is defined as the
12- or 24-hour mode select bit. When high, the 12-hour mode is selected. In the 12-hour mode, bit 5 is
the AM/PM bit with logic high being PM. In the 24-hour mode, bit 5 is the second 10-hour bit (20 to 23
hours).
The DS1306 contains two time-of-day alarms. Time-of-day alarm 0 can be set by writing to registers 87h
to 8Ah. Time-of-day Alarm 1 can be set by writing to registers 8 Bh to 8 Eh. Bit 7 of each of the time-ofday alarm registers are mask bits (Table 1). When all of the mask bits are logic 0, a time-of-day alarm
only occurs once per week when the values stored in timekeeping registers 00h to 03h match the values
stored in the time-of-day alarm registers. An alarm is generated every day when bit 7 of the day alarm
register is set to a logic 1. An alarm is generated every hour when bit 7 of the day and hour alarm
registers is set to a logic 1. Similarly, an alarm is generated every minute when bit 7 of the day, hour, and
minute alarm registers is set to a logic 1. When bit 7 of the day, hour, minute, and seconds alarm registers
is set to a logic 1, an alarm occurs every second.
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DS1306
During each clock update, the RTC compares the Alarm 0 and Alarm 1 registers with the corresponding
clock registers. When a match occurs, the corresponding alarm flag bit in the status register is set to a 1. If
the corresponding alarm interrupt enable bit is enabled, an interrupt output is activated.
Table 1. TIME-OF-DAY ALARM MASK BITS
ALARM REGISTER MASK BITS (BIT 7)
SECONDS MINUTES HOURS DAYS
1 1 1 1 Alarm once per second
0 1 1 1 Alarm when seconds match
0 0 1 1 Alarm when minutes and seconds match
0 0 0 1 Alarm hours, minutes, and seconds match
0 0 0 0 Alarm day, hours, minutes and seconds match
FUNCTION
SPECIAL PURPOSE REGISTERS
The DS1306 has three additional registers (control register, status register, and trickle charger register)
that control the real-time clock, interrupts, and trickle charger.
CONTROL REGISTER (READ 0FH, WRITE 8FH)
BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0
0 WP 0 0 0 1 Hz AIE1 AIE0
WP (Write Protect) – Before any write operation to the clock or RAM, this bit must be logic 0. When
high, the write protect bit prevents a write operation to any register, including bits 0, 1, and 2 of the
control register. Upon initial power-up, the state of the WP bit is undefined. Therefore, the WP bit should
be cleared before attempting to write to the device. When WP is set, it must be cleared before any other
control register bit can be written.
1Hz (1Hz Output Enable) – This bit controls the 1Hz output. When this bit is a logic 1, the 1Hz output
is enabled. When this bit is a logic 0, the 1Hz output is high-Z.
AIE0 (Alarm Interrupt Enable 0) – When set to a logic 1, this bit permits the interrupt 0 request flag
(IRQF0) bit in the status register to assert
INT0 . When the AIE0 bit is set to logic 0, the IRQF0 bit does
not initiate the INT0 signal.
AIE1 (Alarm Interrupt Enable 1) – When set to a logic 1, this bit permits the interrupt 1 request flag
(IRQF1) bit in the status register to assert INT1. When the AIE1 bit is set to logic 0, the IRQF1 bit does
not initiate an interrupt signal, and the INT1 pin is set to a logic 0 state.
STATUS REGISTER (READ 10H)
BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0
000000IRQF1IRQF0
IRQF0 (Interrupt 0 Request Flag) – A logic 1 in the interrupt request flag bit indicates that the current
time has matched the Alarm 0 registers. If the AIE0 bit is also a logic 1, the INT0 pin goes low. IRQF0 is
cleared when the address pointer goes to any of the Alarm 0 registers during a read or write. IRQF0 is
activated when the device is powered by V
CC1
, V
CC2
, or V
BAT
.
IRQF1 (Interrupt 1 Request Flag) – A logic 1 in the interrupt request flag bit indicates that the current
time has matched the Alarm 1 registers. If the AIE1 bit is also a logic 1, the INT1 pin generates a 62.5ms
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