Rainbow Electronics DS1302 User Manual
www.maxim-ic.com
CI/ONCNCNC
C
3
512910
DS1302
Trickle Charge Timekeeping Chip
FEATURES
§ Real-time clock (RTC) counts seconds,
minutes hours, date of the month, month, day
of the week, and year with leap-year
compensation valid up to 2100
§ 31-byte, battery-backed, nonvolatile (NV)
RAM for data storage
§ Serial I/O for minimum pin count
§ 2.0V to 5.5V full operation
§ Uses less than 300nA at 2.0V
§ Burst mode for reading/writing successive
addresses in clock/RAM
§ 8-pin DIP or optional 8-pin SOICs for surface
mount
§ Simple 3-wire interface
§ TTL-compatible (VCC = 5V)
§ Optional industrial temperature range:
-40°C to +85°C
§ DS1202 compatible
§ Underwriters Laboratory (UL) recognized
ORDERING INFORMATION
DS1302 8-Pin DIP (300-mil)
DS1302N 8-Pin DIP (Industrial)
DS1302S 8-Pin SOIC (200-mil)
DS1302SN 8-Pin SOIC (Industrial)
DS1302Z 8-Pin SOIC (150-mil)
DS1302ZN 8-Pin SOIC (Industrial)
DS1302S-16 16-Pin SOIC (300-mil)
DS1302SN-16 16-Pin SOIC (Industrial)
PIN ASSIGNMENT
V
GND
CC2
X1
X2
1
2
3
4
DS1302 8-Pin DIP (300-mil)
CC2
X1
X2
1
2
3
4
V
GND
DS1302 8-Pin SOIC (200-mil)
DS1302 8-Pin SOIC (150-mil)
V
CC2
X1
N
X2
GND
1
2
4
5
6
8
DS1302 16-Pin SOIC (300-mil)
V
8
CC1
7
SCLK
I/O
6
RST
5
V
8
CC1
SCLK
7
I/O
6
RST
5
V
CC1
1
N
RST
PIN DESCRIPTION
X1, X2 - 32.768kHz Crystal Pins
GND - Ground
RST - Reset
I/O - Data Input/Output
SCLK - Serial Clock
V
CC1
, V
CC2
- Power Supply Pins
DESCRIPTION
The DS1302 Trickle Charge Timekeeping Chip contains an RTC/calendar and 31 bytes of static RAM. It
communicates with a microprocessor via a simple serial interface. The RTC/calendar provides seconds,
minutes, hours, day, date, month, and year information. The end of the month date is automatically
adjusted for months with fewer than 31 days, including corrections for leap year. The clock operates in
either the 24-hour or 12-hour format with an AM/PM indicator.
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DS1302
Interfacing the DS1302 with a microprocessor is simplified by using synchronous serial communication.
Only three wires are required to communicate with the clock/RAM: 1) RST (reset), 2) I/O (data line), and
3) SCLK (serial clock). Data can be transferred to and from the clock/RAM 1 byte at a time or in a burst
of up to 31 bytes. The DS1302 is designed to operate on very low power and retain data and clock
information on less than 1 microwatt.
The DS1302 is the successor to the DS1202. In addition to the basic timekeeping functions of the
DS1202, the DS1302 has the additional features of dual-power pins for primary and back-up power
supplies, programmable trickle charger for V
, and seven additional bytes of scratchpad memory.
CC1
TYPICAL OPERATING CIRCUIT
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DS1302
OPERATION
The main elements of the serial timekeeper (i.e., shift register, control logic, oscillator, RTC, and RAM)
are shown in Figure 1.
DS1302 BLOCK DIAGRAM Figure 1
SIGNAL DESCRIPTIONS
V
– V
CC1
power battery backup. In systems using the trickle charger, the rechargeable energy source is connected
to this pin. UL recognized to ensure against reverse charging current when used in conjunction with a
lithium battery.
See “Conditions of Acceptability” at http://www.maxim-ic.com/TechSupport/QA/ntrl.htm.
V
– V
CC2
backup source to maintain the time and date in the absence of primary power.
The DS1302 will operate from the larger of V
will power the DS1302. When V
SCLK (Serial Clock Input) – SCLK is used to synchronize data movement on the serial interface. This
pin has a 40kΩ internal pull-down resistor.
I/O (Data Input/Output) – The I/O pin is the bi-directional data pin for the 3-wire interface. This pin has
a 40kΩ internal pull-down resistor.
RST (Reset) – The reset signal must be asserted high during a read or a write. This pin has a 40kΩ
internal pull-down resistor.
provides low-power operation in single supply and battery-operated systems as well as low-
CC1
is the primary power supply pin in a dual-supply configuration. V
CC2
is less than V
CC2
CC1
or V
CC1
. When V
CC2
, V
will power the DS1302.
CC1
CC2
is greater than V
is connected to a
CC1
+ 0.2V, V
CC1
CC2
X1, X2 – Connections for a standard 32.768kHz quartz crystal. The internal oscillator is designed for
operation with a crystal having a specified load capacitance of 6pF. For more information on crystal
selection and crystal layout considerations, please consult Application Note 58, “Crystal Considerations
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DS1302
CO
OU
with Dallas Real-Time Clocks.” The DS1302 can also be driven by an external 32.768kHz oscillator. In
this configuration, the X1 pin is connected to the external oscillator signal and the X2 pin is floated.
RE
MMENDED LAY
T FOR CRYSTAL
CLOCK ACCURACY
The accuracy of the clock is dependent upon the accuracy of the crystal and the accuracy of the match
between the capactive load of the oscillator circuit and the capacitive load for which the crystal was
trimmed. Additional error will be added by crystal frequency drift caused by temperature shifts. External
circuit noise coupled into the oscillator circuit may result in the clock running fast. See Application Note
58, “Crystal Considerations with Dallas Real-Time Clocks” for detailed information.
COMMAND BYTE
The command byte is shown in Figure 2. Each data transfer is initiated by a command byte. The MSB
(Bit 7) must be a logic 1. If it is 0, writes to the DS1302 will be disabled. Bit 6 specifies clock/calendar
data if logic 0 or RAM data if logic 1. Bits 1 through 5 specify the designated registers to be input or
output, and the LSB (bit 0) specifies a write operation (input) if logic 0 or read operation (output) if logic
1. The command byte is always input starting with the LSB (bit 0).
ADDRESS/COMMAND BYTE Figure 2
RESET AND CLOCK CONTROL
All data transfers are initiated by driving the RST input high. The RST input serves two functions. First,
RST turns on the control logic, which allows access to the shift register for the address/command
sequence. Second, the
data transfer.
A clock cycle is a sequence of a falling edge followed by a rising edge. For data inputs, data must be
valid during the rising edge of the clock and data bits are output on the falling edge of clock. If the
input is low all data transfer terminates and the I/O pin goes to a high impedance state. Data transfer is
illustrated in Figure 3. At power-up,
logic 0 when
RST is driven to a logic 1 state.
RST signal provides a method of terminating either single byte or multiple byte
RST
RST must be a logic 0 until V
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> 2.0V. Also SCLK must be at a
CC
DS1302
DATA INPUT
Following the eight SCLK cycles that input a write command byte, a data byte is input on the rising edge
of the next eight SCLK cycles. Additional SCLK cycles are ignored should they inadvertently occur.
Data is input starting with bit 0.
DATA OUTPUT
Following the eight SCLK cycles that input a read command byte, a data byte is output on the falling
edge of the next eight SCLK cycles. Note that the first data bit to be transmitted occurs on the first falling
edge after the last bit of the command byte is written. Additional SCLK cycles retransmit the data bytes
should they inadvertently occur so long as RST remains high. This operation permits continuous burst
mode read capability. Also, the I/O pin is tri-stated upon each rising edge of SCLK. Data is output
starting with bit 0.
BURST MODE
Burst mode may be specified for either the clock/calendar or the RAM registers by addressing location 31
decimal (address/command bits 1 through 5 = logic 1). As before, bit 6 specifies clock or RAM and bit 0
specifies read or write. There is no data storage capacity at locations 9 through 31 in the Clock/Calendar
Registers or location 31 in the RAM registers. Reads or writes in burst mode start with bit 0 of address 0.
When writing to the clock registers in the burst mode, the first eight registers must be written in order for
the data to be transferred. However, when writing to RAM in burst mode it is not necessary to write all
31 bytes for the data to transfer. Each byte that is written to will be transferred to RAM regardless of
whether all 31 bytes are written or not.
CLOCK/CALENDAR
The clock/calendar is contained in seven write/read registers as shown in Figure 4. Data contained in the
clock/ calendar registers is in binary coded decimal format (BCD).
CLOCK HALT FLAG
Bit 7 of the seconds register is defined as the clock halt flag. When this bit is set to logic 1, the clock
oscillator is stopped and the DS1302 is placed into a low-power standby mode with a current drain of less
than 100 nanoamps. When this bit is written to logic 0, the clock will start. The initial power on state is
not defined.
AM-PM/12-24 MODE
Bit 7 of the hours register is defined as the 12- or 24-hour mode select bit. When high, the 12-hour mode
is selected. In the 12-hour mode, bit 5 is the AM/PM bit with logic high being PM. In the 24-hour mode,
bit 5 is the second 10-hour bit (20–23 hours).
WRITE PROTECT BIT
Bit 7 of the control register is the write-protect bit. The first seven bits (bits 0–6) are forced to 0 and will
always read a 0 when read. Before any write operation to the clock or RAM, bit 7 must be 0. When high,
the write protect bit prevents a write operation to any other register. The initial power on state is not
defined. Therefore the WP bit should be cleared before attempting to write to the device.
TRICKLE CHARGE REGISTER
This register controls the trickle charge characteristics of the DS1302. The simplified schematic of
Figure 5 shows the basic components of the trickle charger. The trickle charge select (TCS) bits
(bits 4–7) control the selection of the trickle charger. In order to prevent accidental enabling, only a
pattern of 1010 will enable the trickle charger. All other patterns will disable the trickle charger. The
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