Rainbow Electronics DS1302 User Manual

DS1302

DS1302

Trickle Charge Timekeeping Chip

FEATURES

• Real time clock counts seconds, minutes, hours, date

of the month, month, day of the week, and year with
leap year compensation valid up to 2100

• 31 x 8 RAM for scratchpad data storage

• Serial I/O for minimum pin count

• 2.5–5.5 volt full operation

– Optional 2.0–5.5 volt full operation also available

• Uses less than 300 nA at 2.5 volts

• Single–byte or multiple–byte (burst mode) data trans-

fer for read or write of clock or RAM data

• 8–pin DIP or optional 8–pin SOIC’s for surface mount

• Simple 3–wire interface

• TTL–compatible (V

CC

= 5V)

• Optional industrial temperature range –40°C to +85°C

• DS1202 compatible

• Added features over DS1202

– Optional trickle charge capability to V
– Dual power supply pins for primary and backup

power supplies

– Backup power supply pin can be used for battery

or super cap input

– Additional scratchpad memory (7 bytes)

CC1

PIN ASSIGNMENT

V

1

CC2

X1

2

X2

3

GND

4

DS1302

8–PIN DIP (300 MIL)

1

V

CC2

2

X1

3

X2

4

GND

DS1302S 8–PIN SOIC (200 MIL)
DS1302Z 8–PIN SOIC (150 MIL)

V

8

CC1

SCLK

7

I/O

6

RST

5

8

V

CC1

7

SCLK

6

I/O

5

RST

PIN DESCRIPTION

X1, X2 – 32.768 kHz Crystal Pins
GND – Ground
RST – Reset
I/O – Data Input/Output
SCLK – Serial Clock

, V

V

CC1

– Power Supply Pins

CC2

ORDERING INFORMATION

PART # DESCRIPTION

DS1302 Serial T imekeeping Chip; 8–pin DIP
DS1302S Serial Timekeeping Chip;

8–pin SOIC (200 mil)

DS1302Z Serial Timekeeping Chip;

8–pin SOIC (150 mil)

DESCRIPTION

The DS1302 Trickle Charge Timekeeping Chip contains
a real time clock/calendar and 31 bytes of static RAM. It
communicates with a microprocessor via a simple serial
interface. The real time clock/calendar provides
seconds, minutes, hours, day, date, month, and year
information. The end of the month date is automatically
adjusted for months with less than 31 days, including
corrections for leap year. The clock operates in either
the 24–hour or 12–hour format with an AM/PM indicator.

Copyright 1995 by Dallas Semiconductor Corporation.
All Rights Reserved. For important information regarding
patents and other intellectual property rights, please refer to
Dallas Semiconductor data books.

Interfacing the DS1302 with a microprocessor is simpli­fied by using synchronous serial communication. Only
three wires are required to communicate with the clock/
RAM: (1) RST (Reset), (2) I/O (Data line), and (3) SCLK
(Serial clock). Data can be transferred to and from the
clock/RAM one byte at a time or in a burst of up to 31
bytes. The DS1302 is designed to operate on very low
power and retain data and clock information on less
than 1 microwatt.

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DS1302

The DS1302 is the successor to the DS1202. In addi­tion to the basic timekeeping functions of the DS1202,
the DS1302 has the additional features of dual power
pins for primary and back–up power supplies, program­mable trickle charger for V

, and seven additional

CC1

bytes of scratchpad memory.

OPERATION

The main elements of the Serial Timekeeper are shown
in Figure 1: shift register, control logic, oscillator, real
time clock, and RAM. To initiate any transfer of data,
RST is taken high and eight bits are loaded into the shift
register providing both address and command informa­tion. Data is serially input on the rising edge of the SCLK.
The first eight bits specify which of 40 bytes will be
accessed, whether a read or write cycle will take place,
and whether a byte or burst mode transfer is to occur.

DS1302 BLOCK DIAGRAM Figure 1

V
V

GND

CC1

CC2

I/O

POWER

CONTROL

REAL TIME

CLOCK

After the first eight clock cycles have loaded the com­mand word into the shift register, additional clocks will
output data for a read or input data for a write. The num­ber of clock pulses equals eight plus eight for byte mode
or eight plus up to 248 for burst mode.

COMMAND BYTE

The command byte is shown in Figure 2. Each data
transfer is initiated by a command byte. The MSB (Bit 7)
must be a logic “1”. If it is zero, writes to the DS1302 will
be disabled. Bit 6 specifies clock/calendar data if logic
“0” or RAM data if logic “1”. Bits one through five specify
the designated registers to be input or output, and the
LSB (Bit 0) specifies a write operation (input) if logic “0”
or read operation (output) if logic “1”. The command
byte is always input starting with the LSB (Bit 0).

32.768 kHz

X2X1

OSCILLATOR
AND DIVIDER

INPUT SHIFT

REGISTERS

SCLK

RST

ADDRESS/COMMAND BYTE Figure 2

RAM

6

CK

5

A4

7

1

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COMMAND AND

CONTROL LOGIC

4

A3

DATA BUS

3

A2

ADDRESS BUS

2

A1

31 X 8 RAM

1

A0

0

RD

W

DS1302

RESET AND CLOCK CONTROL

All data transfers are initiated by driving the RST input
high. The RST input serves two functions. First, RST
turns on the control logic which allows access to the shift
register for the address/command sequence. Second,

signal provides a method of terminating either

the RST
single byte or multiple byte data transfer.

A clock cycle is a sequence of a falling edge followed by
a rising edge. For data inputs, data must be valid during
the rising edge of the clock and data bits are output on
the falling edge of clock. If the RST
transfer terminates and the I/O pin goes to a high imped­ance state. Data transfer is illustrated in Figure 3. At
power–up, RST
Also SCLK must be at a logic “0” when RST is driven to a
logic “1” state.

must be a logic “0” until VCC2.5 volts.

input is low all data

DATA INPUT

Following the eight SCLK cycles that input a write com­mand byte, a data byte is input on the rising edge of the
next eight SCLK cycles. Additional SCLK cycles are
ignored should they inadvertently occur. Data is input
starting with bit 0.

DATA OUTPUT

Following the eight SCLK cycles that input a read com­mand byte, a data byte is output on the falling edge of
the next eight SCLK cycles. Note that the first data bit to
be transmitted occurs on the first falling edge after the
last bit of the command byte is written. Additional SCLK
cycles retransmit the data bytes should they inadver­tently occur so long as RST
tion permits continuous burst mode read capability.
Also, the I/O pin is tri–stated upon each rising edge of
SCLK. Data is output starting with bit 0.

remains high. This opera-

BURST MODE

Burst mode may be specified for either the clock/calen­dar or the RAM registers by addressing location 31 deci­mal (address/command bits one through five = logical
one). As before, bit six specifies clock or RAM and bit 0
specifies read or write. There is no data storage capac­ity at locations 9 through 31 in the Clock/Calendar Reg­isters or location 31 in the RAM registers. Reads or
writes in burst mode start with bit 0 of address 0.

As in the case with the DS1202, when writing to the
clock registers in the burst mode, the first eight registers
must be written in order for the data to be transferred.

However, when writing to RAM in burst mode it is not
necessary to write all 31 bytes for the data to transfer.
Each byte that is written to will be transferred to RAM
regardless of whether all 31 bytes are written or not.

CLOCK/CALENDAR

The clock/calendar is contained in seven write/read reg­isters as shown in Figure 4. Data contained in the clock/
calendar registers is in binary coded decimal format
(BCD).

CLOCK HALT FLAG

Bit 7 of the seconds register is defined as the clock halt
flag. When this bit is set to logic “1”, the clock oscillator is
stopped and the DS1302 is placed into a low–power
standby mode with a current drain of less than 100
nanoamps. When this bit is written to logic “0”, the clock
will start.

AM-PM/12-24 MODE

Bit 7 of the hours register is defined as the 12– or
24–hour mode select bit. When high, the 12–hour mode
is selected. In the 12–hour mode, bit 5 is the AM/PM bit
with logic high being PM. In the 24–hour mode, bit 5 is
the second 10 hour bit (20 – 23 hours).

WRITE PROTECT BIT

Bit 7 of the control register is the write protect bit. The
first seven bits (bits 0 – 6) are forced to zero and will
always read a zero when read. Before any write opera­tion to the clock or RAM, bit 7 must be zero. When high,
the write protect bit prevents a write operation to any
other register.

TRICKLE CHARGE REGISTER

This register controls the trickle charge characteristics
of the DS1302. The simplified schematic of Figure 5
shows the basic components of the trickle charger. The
trickle charge select (TCS) bits (bits 4 – 7) control the
selection of the trickle charger. In order to prevent acci­dental enabling, only a pattern of 1010 will enable the
trickle charger. All other patterns will disable the trickle
charger. The DS1302 powers up with the trickle charger
disabled. The diode select (DS) bits (bits 2 – 3) select
whether one diode or two diodes are connected
between V
selected or if DS is 10, two diodes are selected. If DS is
00 or 11, the trickle charger is disabled independent of

CC2

and V

. If DS is 01, one diode is

CC1

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DS1302

TCS. The RS bits (bits 0 – 1) select the resistor that is
connected between V

CC2

and V

. The resistor

CC1

selected by the resistor select (RS) bits is as follows:

RS Bits

Resistor Typical Value

00 None None
01 R1 2KΩ
10 R2 4KΩ
11 R3 8KΩ

If RS is 00, the trickle charger is disabled independent
of TCS.

Diode and resistor selection is determined by the user
according to the maximum current desired for battery or
super cap charging. The maximum charging current
can be calculated as illustrated in the following example.
Assume that a system power supply of 5V is applied to
V

and a super cap is connected to V

CC2

CC1

. Also
assume that the trickle charger has been enabled with 1
diode and resistor R1 between V
maximum current I

would therefore be calculated as

max

CC2

and V

CC1

. The

follows:

I

= (5.0V – diode drop) / R1

max

~ (5.0V – 0.7V) / 2KΩ
~ 2.2 mA

Obviously, as the super cap charges, the voltage drop
between V

CC2

and V

will decrease and therefore the

CC1

charge current will decrease.

CLOCK/CALENDAR BURST MODE

The clock/calendar command byte specifies burst
mode operation. In this mode the first eight clock/calen­dar registers can be consecutively read or written (see
Figure 4) starting with bit 0 of address 0.

to any of the eight clock/calendar registers (this includes
the control register). The trickle charger is not accessi­ble in burst mode.

RAM

The static RAM is 31 x 8 bytes addressed consecutively
in the RAM address space.

RAM BURST MODE

The RAM command byte specifies burst mode opera­tion. In this mode, the 31 RAM registers can be consec­utively read or written (see Figure 4) starting with bit 0 of
address 0.

REGISTER SUMMARY

A register data format summary is shown in Figure 4.

CRYSTAL SELECTION

A 32.768 kHz crystal can be directly connected to the
DS1302 via pins 2 and 3 (X1, X2). The crystal selected
for use should have a specified load capacitance (CL) of
6 pF.

POWER CONTROL

V

provides low power operation in single supply and

CC1

battery operated systems as well as low power battery
backup.

V

provides the primary power in dual supply sys-

CC2

tems where V
maintain the time and data in the absence of primary
power.

The DS1302 will operate from the larger of V
V

. When V

CC2

power the DS1302. When V
will power the DS1302.

is connected to a backup source to

CC1

is greater than V

CC2

CC2

+ 0.2V , V

CC1

is less than V

CC1

CC1

CC2

, V

or

will

CC1

If the write protect bit is set high when a write clock/cal­endar burst mode is specified, no data transfer will occur

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