DS1302
DS1302
Trickle Charge Timekeeping Chip
FEATURES
• Real time clock counts seconds, minutes, hours, date
of the month, month, day of the week, and year with
leap year compensation valid up to 2100
• 31 x 8 RAM for scratchpad data storage
• Serial I/O for minimum pin count
• 2.5–5.5 volt full operation
– Optional 2.0–5.5 volt full operation also available
• Uses less than 300 nA at 2.5 volts
• Single–byte or multiple–byte (burst mode) data trans-
fer for read or write of clock or RAM data
• 8–pin DIP or optional 8–pin SOIC’s for surface mount
• Simple 3–wire interface
• TTL–compatible (V
CC
= 5V)
• Optional industrial temperature range –40°C to +85°C
• DS1202 compatible
• Added features over DS1202
– Optional trickle charge capability to V
– Dual power supply pins for primary and backup
power supplies
– Backup power supply pin can be used for battery
or super cap input
– Additional scratchpad memory (7 bytes)
CC1
PIN ASSIGNMENT
V
1
CC2
X1
2
X2
3
GND
4
DS1302
8–PIN DIP (300 MIL)
1
V
CC2
2
X1
3
X2
4
GND
DS1302S 8–PIN SOIC (200 MIL)
DS1302Z 8–PIN SOIC (150 MIL)
V
8
CC1
SCLK
7
I/O
6
RST
5
8
V
CC1
7
SCLK
6
I/O
5
RST
PIN DESCRIPTION
X1, X2 – 32.768 kHz Crystal Pins
GND – Ground
RST – Reset
I/O – Data Input/Output
SCLK – Serial Clock
, V
V
CC1
– Power Supply Pins
CC2
ORDERING INFORMATION
PART # DESCRIPTION
DS1302 Serial T imekeeping Chip; 8–pin DIP
DS1302S Serial Timekeeping Chip;
8–pin SOIC (200 mil)
DS1302Z Serial Timekeeping Chip;
8–pin SOIC (150 mil)
DESCRIPTION
The DS1302 Trickle Charge Timekeeping Chip contains
a real time clock/calendar and 31 bytes of static RAM. It
communicates with a microprocessor via a simple serial
interface. The real time clock/calendar provides
seconds, minutes, hours, day, date, month, and year
information. The end of the month date is automatically
adjusted for months with less than 31 days, including
corrections for leap year. The clock operates in either
the 24–hour or 12–hour format with an AM/PM indicator.
Copyright 1995 by Dallas Semiconductor Corporation.
All Rights Reserved. For important information regarding
patents and other intellectual property rights, please refer to
Dallas Semiconductor data books.
Interfacing the DS1302 with a microprocessor is simplified by using synchronous serial communication. Only
three wires are required to communicate with the clock/
RAM: (1) RST (Reset), (2) I/O (Data line), and (3) SCLK
(Serial clock). Data can be transferred to and from the
clock/RAM one byte at a time or in a burst of up to 31
bytes. The DS1302 is designed to operate on very low
power and retain data and clock information on less
than 1 microwatt.
041697 1/12
DS1302
The DS1302 is the successor to the DS1202. In addition to the basic timekeeping functions of the DS1202,
the DS1302 has the additional features of dual power
pins for primary and back–up power supplies, programmable trickle charger for V
, and seven additional
CC1
bytes of scratchpad memory.
OPERATION
The main elements of the Serial Timekeeper are shown
in Figure 1: shift register, control logic, oscillator, real
time clock, and RAM. To initiate any transfer of data,
RST is taken high and eight bits are loaded into the shift
register providing both address and command information. Data is serially input on the rising edge of the SCLK.
The first eight bits specify which of 40 bytes will be
accessed, whether a read or write cycle will take place,
and whether a byte or burst mode transfer is to occur.
DS1302 BLOCK DIAGRAM Figure 1
V
V
GND
CC1
CC2
I/O
POWER
CONTROL
REAL TIME
CLOCK
After the first eight clock cycles have loaded the command word into the shift register, additional clocks will
output data for a read or input data for a write. The number of clock pulses equals eight plus eight for byte mode
or eight plus up to 248 for burst mode.
COMMAND BYTE
The command byte is shown in Figure 2. Each data
transfer is initiated by a command byte. The MSB (Bit 7)
must be a logic “1”. If it is zero, writes to the DS1302 will
be disabled. Bit 6 specifies clock/calendar data if logic
“0” or RAM data if logic “1”. Bits one through five specify
the designated registers to be input or output, and the
LSB (Bit 0) specifies a write operation (input) if logic “0”
or read operation (output) if logic “1”. The command
byte is always input starting with the LSB (Bit 0).
32.768 kHz
X2X1
OSCILLATOR
AND DIVIDER
INPUT SHIFT
REGISTERS
SCLK
RST
ADDRESS/COMMAND BYTE Figure 2
RAM
6
CK
5
A4
7
1
041697 2/12
COMMAND AND
CONTROL LOGIC
4
A3
DATA BUS
3
A2
ADDRESS BUS
2
A1
31 X 8 RAM
1
A0
0
RD
W
DS1302
RESET AND CLOCK CONTROL
All data transfers are initiated by driving the RST input
high. The RST input serves two functions. First, RST
turns on the control logic which allows access to the shift
register for the address/command sequence. Second,
signal provides a method of terminating either
the RST
single byte or multiple byte data transfer.
A clock cycle is a sequence of a falling edge followed by
a rising edge. For data inputs, data must be valid during
the rising edge of the clock and data bits are output on
the falling edge of clock. If the RST
transfer terminates and the I/O pin goes to a high impedance state. Data transfer is illustrated in Figure 3. At
power–up, RST
Also SCLK must be at a logic “0” when RST is driven to a
logic “1” state.
must be a logic “0” until VCC2.5 volts.
input is low all data
DATA INPUT
Following the eight SCLK cycles that input a write command byte, a data byte is input on the rising edge of the
next eight SCLK cycles. Additional SCLK cycles are
ignored should they inadvertently occur. Data is input
starting with bit 0.
DATA OUTPUT
Following the eight SCLK cycles that input a read command byte, a data byte is output on the falling edge of
the next eight SCLK cycles. Note that the first data bit to
be transmitted occurs on the first falling edge after the
last bit of the command byte is written. Additional SCLK
cycles retransmit the data bytes should they inadvertently occur so long as RST
tion permits continuous burst mode read capability.
Also, the I/O pin is tri–stated upon each rising edge of
SCLK. Data is output starting with bit 0.
remains high. This opera-
BURST MODE
Burst mode may be specified for either the clock/calendar or the RAM registers by addressing location 31 decimal (address/command bits one through five = logical
one). As before, bit six specifies clock or RAM and bit 0
specifies read or write. There is no data storage capacity at locations 9 through 31 in the Clock/Calendar Registers or location 31 in the RAM registers. Reads or
writes in burst mode start with bit 0 of address 0.
As in the case with the DS1202, when writing to the
clock registers in the burst mode, the first eight registers
must be written in order for the data to be transferred.
However, when writing to RAM in burst mode it is not
necessary to write all 31 bytes for the data to transfer.
Each byte that is written to will be transferred to RAM
regardless of whether all 31 bytes are written or not.
CLOCK/CALENDAR
The clock/calendar is contained in seven write/read registers as shown in Figure 4. Data contained in the clock/
calendar registers is in binary coded decimal format
(BCD).
CLOCK HALT FLAG
Bit 7 of the seconds register is defined as the clock halt
flag. When this bit is set to logic “1”, the clock oscillator is
stopped and the DS1302 is placed into a low–power
standby mode with a current drain of less than 100
nanoamps. When this bit is written to logic “0”, the clock
will start.
AM-PM/12-24 MODE
Bit 7 of the hours register is defined as the 12– or
24–hour mode select bit. When high, the 12–hour mode
is selected. In the 12–hour mode, bit 5 is the AM/PM bit
with logic high being PM. In the 24–hour mode, bit 5 is
the second 10 hour bit (20 – 23 hours).
WRITE PROTECT BIT
Bit 7 of the control register is the write protect bit. The
first seven bits (bits 0 – 6) are forced to zero and will
always read a zero when read. Before any write operation to the clock or RAM, bit 7 must be zero. When high,
the write protect bit prevents a write operation to any
other register.
TRICKLE CHARGE REGISTER
This register controls the trickle charge characteristics
of the DS1302. The simplified schematic of Figure 5
shows the basic components of the trickle charger. The
trickle charge select (TCS) bits (bits 4 – 7) control the
selection of the trickle charger. In order to prevent accidental enabling, only a pattern of 1010 will enable the
trickle charger. All other patterns will disable the trickle
charger. The DS1302 powers up with the trickle charger
disabled. The diode select (DS) bits (bits 2 – 3) select
whether one diode or two diodes are connected
between V
selected or if DS is 10, two diodes are selected. If DS is
00 or 11, the trickle charger is disabled independent of
CC2
and V
. If DS is 01, one diode is
CC1
041697 3/12
DS1302
TCS. The RS bits (bits 0 – 1) select the resistor that is
connected between V
CC2
and V
. The resistor
CC1
selected by the resistor select (RS) bits is as follows:
RS Bits
Resistor Typical Value
00 None None
01 R1 2KΩ
10 R2 4KΩ
11 R3 8KΩ
If RS is 00, the trickle charger is disabled independent
of TCS.
Diode and resistor selection is determined by the user
according to the maximum current desired for battery or
super cap charging. The maximum charging current
can be calculated as illustrated in the following example.
Assume that a system power supply of 5V is applied to
V
and a super cap is connected to V
CC2
CC1
. Also
assume that the trickle charger has been enabled with 1
diode and resistor R1 between V
maximum current I
would therefore be calculated as
max
CC2
and V
CC1
. The
follows:
I
= (5.0V – diode drop) / R1
max
~ (5.0V – 0.7V) / 2KΩ
~ 2.2 mA
Obviously, as the super cap charges, the voltage drop
between V
CC2
and V
will decrease and therefore the
CC1
charge current will decrease.
CLOCK/CALENDAR BURST MODE
The clock/calendar command byte specifies burst
mode operation. In this mode the first eight clock/calendar registers can be consecutively read or written (see
Figure 4) starting with bit 0 of address 0.
to any of the eight clock/calendar registers (this includes
the control register). The trickle charger is not accessible in burst mode.
RAM
The static RAM is 31 x 8 bytes addressed consecutively
in the RAM address space.
RAM BURST MODE
The RAM command byte specifies burst mode operation. In this mode, the 31 RAM registers can be consecutively read or written (see Figure 4) starting with bit 0 of
address 0.
REGISTER SUMMARY
A register data format summary is shown in Figure 4.
CRYSTAL SELECTION
A 32.768 kHz crystal can be directly connected to the
DS1302 via pins 2 and 3 (X1, X2). The crystal selected
for use should have a specified load capacitance (CL) of
6 pF.
POWER CONTROL
V
provides low power operation in single supply and
CC1
battery operated systems as well as low power battery
backup.
V
provides the primary power in dual supply sys-
CC2
tems where V
maintain the time and data in the absence of primary
power.
The DS1302 will operate from the larger of V
V
. When V
CC2
power the DS1302. When V
will power the DS1302.
is connected to a backup source to
CC1
is greater than V
CC2
CC2
+ 0.2V , V
CC1
is less than V
CC1
CC1
CC2
, V
or
will
CC1
If the write protect bit is set high when a write clock/calendar burst mode is specified, no data transfer will occur
041697 4/12
DATA TRANSFER SUMMARY Figure 3
SINGLE BYTE TRANSFER
SCLK
RST
0123456 701 23456 7
R/W
I/O
BURST MODE TRANSFER
SCLK
RST
I/O
A0 A1 A2 A3 A4 1
ADDRESS COMMAND DATA INPUT/OUTPUT
0123456 701 2 456 7
R/W
11111 1
ADDRESS COMMAND DATA I/O BYTE N
DS1302
R/C
R/C
DATA I/O BYTE 1
FUNCTION BYTE N SCLK n
CLOCK 8 72
RAM 31 256
041697 5/12
DS1302
REGISTER ADDRESS/DEFINITION Figure 4
REGISTER ADDRESS REGISTER DEFINITION
A. CLOCK
0
1
RD
W
00–59
CH SEC10 SEC
SEC
7
6
1
050403020
0
MIN
HR
DATE
MONTH
DAY
YEAR
CONTROL
TRICKLE
CHARGER
CLOCK
BURST
1 0 0 0 0 1
0
1 0 0 0 1 0
0
1 0 0 0 1 1
0
1 0 0 1 0 0
0
1 0 0 1 0 1
0
1 0 0 1 1 0
0
1 0 0 1 1 1
0
1 0 1 0 0 0
0
111111
0
RD
RD
RD
RD
RD
RD
RD
RD
RD
0
W
W
W
W
W
W
W
W
W
00–59
01–12
00–23 24
01–28/29
01–30
01–31
01–12
01–07
00–99
12/
0 10 DATE0
0 0
0 0 00
WP 0 0 0 0 000
TCS TCS TCS DS DS RSTCS RS
0
10 YEAR
10
A/P
MIN10 MIN
HR HR0
DATE
10
M
MONTH
DAY0
YEAR
B. RAM
RAM 0
RAM 30
RAM
BURST
041697 6/12
1 0 0 0 0 0
1
1 1 1 1 1 0
1
1 1 1 1 1 1
1
RD
RD
RD
W
W
W
RAM DATA 0
RAM DATA 30
DS1302 PROGRAMMABLE TRICKLE CHARGER Figure 5
V
CC2
PIN #1
R1
2KΩ
R2
4KΩ
R3
8KΩ
DS1302
V
CC1
PIN #8
TRICKLE
CHARGE
REGISTER
1 OF 16 SELECT
(NOTE: ONLY 1010 CODE ENABLES CHARGER
1 OF 2
SELECT
1 OF 3
SELECT
TCS TCS TCS TCS DS DS RS RS
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
TCS
DS
RS
TRICKLE CHARGER SELECT
=
DIODE SELECT
=
RESISTOR SELECT
=
041697 7/12
DS1302
Logic 0 I
t
V
V
1
Logic 1 Output
V
V
2
Logic 0 Output
V
V
3
Acti
t
I
A
5, 12
Timek
t
I
A
4,12
Standby C
t
I
A
10, 12
Acti
t
I
A
5, 13
ABSOLUTE MAXIMUM RATINGS*
Voltage on Any Pin Relative to Ground –0.5V to +7.0V
Operating Temperature 0°C to 70°C
Storage Temperature –55°C to +125°C
Soldering Temperature 260°C for 10 seconds
* This is a stress rating only and functional operation of the device at these or any other conditions above those
indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods of time may affect reliability.
The Dallas Semiconductor DS1302 is built to the highest quality standards and manufactured for long term reliability.
All Dallas Semiconductor devices are made using the same quality materials and manufacturing methods. However,
standard versions of the DS1302 are not exposed to environmental stresses, such as burn–in, that some industrial
applications require. Products which have successfully passed through this series of environmental stresses are
marked IND or N, denoting their extended operating temperature and reliability rating. For specific reliability information on this product, please contact the factory in Dallas at (972) 371–4448.
RECOMMENDED DC OPERATING CONDITIONS (0°C to 70°C)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Supply Voltage V
Logic 1 Input V
npu
CC1
, V
CC2
V
V
CC1
CC2
IH
,
2.5 5.5 V 1, 11
2.0 VCC+0.3 V 1
VCC=2.5V –0.3 +0.3
IL
VCC=5V –0.3 +0.8
DC ELECTRICAL CHARACTERISTICS (0°C to 70°C; VCC = 2.5 to 5.5V*)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Input Leakage I
I/O Leakage I
ve Supply Curren
eeping Curren
urren
ve Supply Curren
*Unless otherwise noted.
041697 8/12
LI
LO
OH
OL
CC1A
CC1T
CC1S
CC2A
VCC=2.5V 1.6
VCC=5V 2.4
VCC=2.5V 0.4
VCC=5V 0.4
V
=2.5V
CC1
V
=5V 1.2
CC1
V
=2.5V
CC1
V
=5V 1
CC1
V
=2.5V
CC1
V
=5V 100
CC1
V
=2.5V
CC2
V
=5V 1.28
CC2
100
+500 µA 6
+500 µA 6
0.4
0.3
0.425
m
µ
10, 12,
n
m
,
14
DS1302
Timek
t
I
A
4,13
Standby C
t
I
A
10, 13
Data to CLK Set
t
7
CLK to Data Hold
t
7
CLK to Data Del
t
7, 8, 9
CLK L
t
7
CLK High Ti
t
7
CLK F
t
MHz7
CLK Ri
ll
t
t
RST to CLK Set
t
7
DC ELECTRICAL CHARACTERISTICS (cont’d) (0°C to 70°C; VCC = 2.5 to 5.5V*)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
eeping Curren
urren
CC2T
CC2S
Trickle Charge Resistors R1
R2
R3
Trickle Charger Diode Voltage Drop V
TD
=2.5V
CC2
V
=5V 81
CC2
V
=2.5V
CC2
V
=5V 80
CC2
2
4
8
0.7 V
25.3
25
µ
µ
KΩ
KΩ
KΩ
V
*Unless otherwise noted.
CAPACITANCE (tA = 25°C)
PARAMETER SYMBOL CONDITION TYP MAX UNITS NOTES
Input Capacitance C
I/O Capacitance C
Crystal Capacitance C
I
I/O
X
10 pF
15 pF
6 pF
AC ELECTRICAL CHARACTERISTICS (0°C to 70°C; VCC = +5V ± 10%*)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
up
ay
ow Time
me
requency
se and Fa
up
*Unless otherwise noted.
DC
CDH
CDD
CH
CLK
R
CC
VCC=2.5V 200
VCC=5V 50
VCC=2.5V 280
VCC=5V 70
VCC=2.5V 800
VCC=5V 200
VCC=2.5V 1000
CL
VCC=5V 250
VCC=2.5V 1000
VCC=5V 250
VCC=2.5V 0.5
VCC=5V DC 2.0
VCC=2.5V 2000
,
F
VCC=5V 500
VCC=2.5V 4
VCC=5V 1
ns
ns
ns
ns
ns
ns
µs
041697 9/12
DS1302
CLK to RST Hold
t
7
RST I
t
7
RST to I/O High Z
t
7
SCLK to I/O High Z
t
7
AC ELECTRICAL CHARACTERISTICS (cont’d) (0°C to 70°C; VCC = +5V ± 10%*)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
nactive Time
CCH
CWH
CDZ
CCZ
VCC=2.5V 240
VCC=5V 60
VCC=2.5V 4
VCC=5V 1
VCC=2.5V 280
VCC=5V 70
VCC=2.5V 280
VCC=5V 70
ns
µs
ns
ns
*Unless otherwise noted.
TIMING DIAGRAM: READ DATA TRANSFER Figure 5
RST
SCLK
I/O
t
CC
t
t
DC
017
CDH
WRITE COMMAND BYTE READ DATA BIT
TIMING DIAGRAM: WRITE DATA TRANSFER Figure 6
RST
SCLK
I/O
t
CC
t
CL
t
CDH
t
DC
01
t
CH
t
CCZ
t
CDD
t
R
7
t
CDD
0 1
t
CCH
t
F
0
t
CWH
t
CDZ
041697 10/12
WRITE COMMAND BYTE WRITE DATA
NOTES:
1. All voltages are referenced to ground.
2. Logic one voltages are specified at a source current of 1 mA at V
capacitive loads.
3. Logic zero voltages are specified at a sink current of 4 mA at V
capacitive loads.
CC1T
CC1A
and I
and I
4. I
5. I
VCC=2.5V and clock halt flag=0 (oscillator enabled).
, SCLK, and I/O all have 40KΩ pulldown resistors to ground.
6. RST
7. Measured at V
8. Measured at V
9. Load capacitance = 50 pF.
CC1S
and I
10.I
disabled).
11. V
CC=VCC2
CC2
CC1
=0 volts.
=0 volts.
12.V
13.V
14.Typical values are at 25°C.
are specified with I/O open, RST set to a logic “0”, and clock halt flag=0 (oscillator enabled).
CC2T
are specified with the I/O pin open, RST high, SCLK=2 MHz at VCC=5V; SCLK=500 kHz,
CC2A
=2.0V or VIL=0.8V and 10 ms maximum rise and fall time.
IH
=2.4V or VOL=0.4V.
OH
are specified with RST , I/O, and SCLK open. The clock halt flag must be set to logic one (oscillator
CC2S
, when V
CC2>VCC1
+0.2V; VCC=V
CC1
, when V
CC1>VCC2
DS1302
=5V and 0.4 mA at VCC=2.5V , VOH=VCC for
CC
=5V and 1.5 mA at VCC=2.5V, VOL=GND for
CC
.
DS1302 SERIAL TIMEKEEPER 8–PIN DIP
85
B
14
A
C
F
E
K
D
J
H
G
8–PINPKG
DIM MIN MAX
0.360
A IN.
MM
B IN.
MM
C IN.
MM
D IN.
MM
E IN.
MM
F IN.
MM
G IN.
MM
H IN.
MM
J IN.
MM
K IN.
MM
9.14
0.240
6.10
0.120
3.05
0.300
7.62
0.015
0.38
0.120
3.04
0.090
2.29
0.320
8.13
0.008
0.20
0.015
0.38
0.400
10.16
0.260
6.60
0.140
3.56
0.325
8.26
0.040
1.02
0.140
3.56
0.110
2.79
0.370
9.40
0.012
0.30
0.021
0.53
041697 11/12
DS1302
DS1302S SERIAL TIMEKEEPER 8–PIN SOIC (150 MIL AND 200 MIL)
PKG
DIM MIN MAX
A IN.
MM
B IN.
MM
C IN.
MM
E IN.
MM
F IN.
MM
G IN.
MM
H IN.
MM
J IN.
MM
K IN.
MM
L IN.
MM
phi
56–G2008–001
56–G4010–001
8–PIN
(150 MIL)
0.188
4.78
0.150
3.81
0.048
1.22
0.004
0.10
0.053
1.35
0.230
5.84
0.007
0.18
0.012
0.30
0.016
0.41
0° 8°
0.196
4.98
0.158
4.01
0.062
1.57
0.010
0.25
0.069
1.75
0.050 BSC
1.27 BSC
0.244
6.20
0.011
0.28
0.020
0.51
0.050
1.27
8–PIN
(200 MIL)
MIN MAX
0.203
0.213
5.16
5.41
0.203
0.213
5.16
5.41
0.070
0.074
1.78
1.88
0.004
0.010
0.10
0.25
0.074
0.084
1.88
2.13
0.302
0.318
7.67
8.08
0.006
0.010
0.15
0.25
0.013
0.020
0.33
0.51
0.019
0.030
0.48
0.76
0° 8°
041697 12/12
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