Rainbow Electronics DS12C887 User Manual

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DS12C887

Real Time Clock

FEATURES

 Drop-in replacement for IBM AT computer

clock/calendar

 Pin compatible with the MC146818B and

DS1287

 Totally nonvolatile with over 10 years of

operation in the absence of power

 Self-contained subsystem includes lithium,

quartz, and support circuitry.

 Counts seconds, minutes, hours, days, day of

the week, date, month, and year with leap year compensation valid up to 2100

 Binary or BCD representation of time,

calendar, and alarm

 12– or 24–hour clock with AM and PM in

12–hour mode

 Daylight Savings Time option  Selectable between Motorola and Intel bus

timing

 Multiplex bus for pin efficiency  Interfaced with software as 128 RAM

locations – 15 bytes of clock and control registers – 113 bytes of general purpose RAM

 Programmable square wave output signal  Bus–compatible interrupt signals (IRQ)  Three interrupts are separately software

maskable and testable – Time–of–day alarm once/second to

once/day – Periodic rates from 122 ms to 500 ms – End of clock update cycle

 Century register

PIN ASSIGNMENT

MOT

NC AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7

GND

ENCAPSULATED PACKAGE

2 3 4

5 6

7 8

9 10

11 12

DS12C887 24-Pin

24 23

22 21

20 19

18 17

16 15

14 13

SQW NC

NC NC IRQ RESET DS NC R/W

PIN DESCRIPTION

AD0-AD7 - Multiplexed Address/Data Bus NC - No Connect MOT - Bus Type Selection

CS - RTC Chip Select Input

AS - Address Strobe

R/W - Read/Write Input

DS - Data Strobe

RESET - Reset Input

IRQ - Interrupt Request Output

SQW - Square Wave Output V

GND - Ground

- +5 Volt Main Supply

DESCRIPTION

The DS12C887 Real Time Clock plus RAM is designed as a direct upgrade replacement for the DS12887 in existing IBM compatible personal computers to add hardware year 2000 compliance. A century byte was added to memory location 50, 32h, as called out by the PC AT specification. A lithium energy source, quartz crystal, and write-protection circuitry are contained within a 24–pin dual in-line package. As such, the DS12C887 is a complete subsystem replacing 16 components in a typical application. The functions include a nonvolatile time-of-day clock, an alarm, a one-hundred-year calendar, programmable interrupt, square wave generator, and 113 bytes of nonvolatile static RAM. The real time clock is distinctive in that time-of-day and memory are maintained even in the absence of power.

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DS12C887

OPERATION

The block diagram in Figure 1 shows the pin connections with the major internal functions of the DS12C887. The following paragraphs describe the function of each pin.

SIGNAL DESCRIPTIONS

GND, V

applied within normal limits, the device is fully accessible and data can be written and read. When V below 4.25 volts typical, reads and writes are inhibited. However, the timekeeping function continues unaffected by the lower input voltage. As VCC falls below 3 volts typical, the RAM and timekeeper are switched over to an internal lithium energy source. The timekeeping function maintains an accuracy of ±1 minute per month at 25°C regardless of the voltage input on the V

MOT (Mode Select) – The MOT pin offers the flexibility to choose between two bus types. When

connected to V

bus timing is selected. The pin has an internal pull-down resistance of approximately 20KΩ.

SQW (Square Wave Output) – The SQW pin can output a signal from one of 13 taps provided by the

15 internal divider stages of the Real Time Clock. The frequency of the SQW pin can be changed by programming Register A as shown in Table 1. The SQW signal can be turned on and off using the SQWE bit in Register B. The SQW signal is not available when V

- DC power is provided to the device on these pins. V

, Motorola bus timing is selected. When connected to GND or left disconnected, Intel

is the +5 volt input. When 5 volts are

pin.

is less than 4.25 volts typical.

AD0-AD7 (Multiplexed Bidirectional Address/Data Bus) – Multiplexed buses save pins because

address information and data information time share the same signal paths. The addresses are present during the first portion of the bus cycle and the same pins and signal paths are used for data in the second portion of the cycle. Address/data multiplexing does not slow the access time of the DS12C887 since the bus change from address to data occurs during the internal RAM access time. Addresses must be valid prior to the falling edge of AS/ALE, at which time the DS12C887 latches the address from AD0 to AD6. Valid write data must be present and held stable during the latter portion of the DS or WR pulses. In a read cycle the DS12C887 outputs 8 bits of data during the latter portion of the DS or RD pulses. The read cycle is terminated and the bus returns to a high impedance state as DS transitions low in the case of Motorola timing or as RD transitions high in the case of Intel timing.

AS (Address Strobe Input) – A positive going address strobe pulse serves to demultiplex the bus. The

falling edge of AS/ALE causes the address to be latched within the DS12C887. The next rising edge that

occurs on the AS bus will clear the address regardless of whether CS is asserted. Access commands should be sent in pairs.

DS (Data Strobe or Read Input) – The DS/RD pin has two modes of operation depending on the level

of the MOT pin. When the MOT pin is connected to VCC, Motorola bus timing is selected. In this mode DS is a positive pulse during the latter portion of the bus cycle and is called Data Strobe. During read cycles, DS signifies the time that the DS12C887 is to drive the bidirectional bus. In write cycles the trailing edge of DS causes the DS12C887 to latch the written data. When the MOT pin is connected to GND, Intel bus timing is selected. In this mode the DS pin is called Read(RD). RD identifies the time period when the DS12C887 drives the bus with read data. The RD signal is the same definition as the Output Enable (OE) signal on a typical memory.

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DS12C887

R/W (Read/Write Input) – The R/ W pin also has two modes of operation. When the MOT pin is

connected to V

for Motorola timing, R/W is at a level which indicates whether the current cycle is a

read or write. A read cycle is indicated with a high level on R/W while DS is high. A write cycle is

indicated when R/

W signal is an active low signal called WR. In this mode the R/ W pin has the same meaning as the

W is low during DS. When the MOT pin is connected to GND for Intel timing, the

Write Enable signal (WE) on generic RAMs.

CS (Chip Select Input) – The Chip Select signal must be asserted low for a bus cycle in the DS12C887

to be accessed.

and WR for Intel timing. Bus cycles which take place without asserting access will occur. When V

internally disabling the

CS must be kept in the active state during DS and AS for Motorola timing and during RD

CS will latch addresses but no

is below 4.25 volts, the DS12C887 internally inhibits access cycles by

CS input. This action protects both the real time clock data and RAM data during

power outages.

IRQ (Interrupt Request Output) - The IRQ pin is an active low output of the DS12C887 that can be

used as an interrupt input to a processor. The

interrupt is present and the corresponding interrupt-enable bit is set. To clear the

IRQ output remains low as long as the status bit causing the

IRQ pin the processor

program normally reads the C register. The RESET pin also clears pending interrupts. When no interrupt

conditions are present, the

connected to an

RESET (Reset Input) – The RESET pin has no effect on the clock, calendar, or RAM. On power-up the

IRQ bus. The IRQ bus is an open drain output and requires an external pull-up resistor.

IRQ level is in the high impedance state. Multiple interrupting devices can be

RESET pin can be held low for a time in order to allow the power supply to stabilize. The amount of

time that

the time

DS12C887 on power-up has timed out. When

RESET is held low is dependent on the application. However, if RESET is used on power–up,

RESET is low should exceed 200 ms to make sure that the internal timer that controls the

RESET is low and VCC is above 4.25 volts, the following

occurs:

A. Periodic Interrupt Enable (PEI) bit is cleared to zero. B. Alarm Interrupt Enable (AIE) bit is cleared to zero. C. Update Ended Interrupt Flag (UF) bit is cleared to zero. D. Interrupt Request Status Flag (IRQF) bit is cleared to zero. E. Periodic Interrupt Flag (PF) bit is cleared to zero.

F. The device is not accessible until

RESET is returned high.

G. Alarm Interrupt Flag (AF) bit is cleared to zero.

IRQ pin is in the high impedance state.

H. I. Square Wave Output Enable (SQWE) bit is cleared to zero. J. Update Ended Interrupt Enable (UIE) is cleared to zero.

In a typical application

RESET can be connected to VCC . This connection will allow the DS12C887 to

go in and out of power fail without affecting any of the control registers.

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DS12C887 BLOCK DIAGRAM Figure 1

DS12C887

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DS12C887

POWER-DOWN/POWER-UP CONSIDERATIONS

The Real Time Clock function will continue to operate and all of the RAM, time, calendar, and alarm memory locations remain nonvolatile regardless of the level of the V

input. When VCC is applied to the

DS12C887 and reaches a level of greater than 4.25 volts, the device becomes accessible after 200 ms, provided that the oscillator is running and the oscillator countdown chain is not in reset (see Register A). This time period allows the system to stabilize after power is applied. When V

the chip select input is internally forced to an inactive level regardless of the value of

falls below 4.25 volts,

CS at the input pin.

The DS12C887 is, therefore, write-protected. When the DS12C887 is in a write-protected state, all inputs are ignored and all outputs are in a high impedance state. When V 3 volts, the external V

supply is switched off and an internal lithium energy source supplies power to

falls below a level of approximately

the Real Time Clock and the RAM memory.

RTC ADDRESS MAP

The address map for the DS12C885 is shown in Figure 2. The address map consists of 113 bytes of user RAM, 11 bytes of RAM that contain the RTC time, calendar, and alarm data, and 4 bytes which are used for control and status. All 128 bytes can be directly written or read except for the following:

Registers C and D are read-only.

Bit-7 of Register A is read-only.

The high order bit of the seconds byte is read-only.

DS12C887 REAL TIME CLOCK ADDRESS MAP Figure 2

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DS12C887

TIM E , C ALE N DAR AN D AL AR M LOC AT ION S

The time and calendar information is obtained by reading the appropriate memory bytes. The time, calendar, and alarm are set or initialized by writing the appropriate RAM bytes. The contents of the ten time, calendar, and alarm bytes can be either Binary or Binary-Coded Decimal (BCD) format. Before writing the internal time, calendar, and alarm registers, the SET bit in Register B should be written to a logic one to prevent updates from occurring while access is being attempted. In addition to writing the ten time, calendar, and alarm registers in a selected format (binary or BCD), the data mode bit (DM) of Register B must be set to the appropriate logic level. All ten time, calendar, and alarm bytes must use the same data mode. The set bit in Register B should be cleared after the data mode bit has been written to allow the real time clock to update the time and calendar bytes. Once initialized, the real time clock makes all updates in the selected mode. The data mode cannot be changed without reinitializing the ten data bytes. Table 2 shows the binary and BCD formats of the ten time, calendar, and alarm locations. The 24–12 bit cannot be changed without reinitializing the hour locations. When the 12–hour format is selected, the high order bit of the hours byte represents PM when it is a logic one. The time, calendar, and alarm bytes are always accessible because they are double buffered. Once per second the eleven bytes are advanced by one second and checked for an alarm condition. If a read of the time and calendar data occurs during an update, a problem exists where seconds, minutes, hours, etc. may not correlate. The probability of reading incorrect time and calendar data is low. Several methods of avoiding any possible incorrect time and calendar reads are covered later in this text. The three alarm bytes can be used in two ways. First, when the alarm time is written in the appropriate hours, minutes, and seconds alarm locations, the alarm interrupt is initiated at the specified time each day if the alarm enable bit is high . The second use condition is to insert a “don’t care” state in one or more of the three alarm bytes. The “don’t care” code is any hexadecimal value from C0 to FF. The two most significant bits of each byte set the “don’t care” condition when at logic 1. An alarm will be generated each hour when the “don’t care” bits are set in the hours byte. Similarly, an alarm is generated every minute with “don’t care” codes in the hours and minute alarm bytes. The “don’t care” codes in all three alarm bytes create an interrupt every second.

TIME, CALENDAR AND ALARM DATA MODES Table 1

LOCATION

O Seconds 0-59 00-3B 00-59

1 Seconds Alarm 0-59 00-3B 00-59 2 Minutes 0-59 00-3B 00-59 3 Minutes Alarm 0-59 00-3B 00-59

Hours 12-hr, Mode 1-12 01-0C AM, 81-8C PM 01-12 AM, 81-92 PM4 Hours 24-hr, Mode 0-23 00-17 00-23 Hours Alarm 12-hr, Mode 1-12 01-0C AM, 81-8C PM 01-12 AM, 81-92 PM5

Hours Alarm 24-hr, Mode 0-23 00-17 00-23 6 Day of the week Sunday=1 1-7 01-07 01-07 7 Date of Month 1-31 01-1F 01-31 8 Month 1-12 01-0C 01-12 9 Year 0-99 00-63 00-99

50 Century 0-99 NA 19,20

FUNCTION DECIMAL

RANGE

BINARY DATA MODE BCD DATA MODE

RANGEADDRESS

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