Rainbow Electronics DS1286 User Manual

www.dalsemi.com

(

)

DS1286

Watchdog Timekeepe

FEATURES

 Keeps track of hundredths of seconds,

seconds, minutes, hours, days, date of the month, months, and years; valid leap year compensation up to 2100

 Watchdog timer restarts an out-of-control

processor

 Alarm function schedules real time-related

activities

 Embedded lithium energy cell maintains time,

watchdog, user RAM, and alarm information

 Programmable interrupts and square wave

outputs maintain 28-pin JEDEC footprint

 All registers are individually addressable via

the address and data bus

 Accuracy is better than ±1 minute/month at

25°C

 Greater than 10 years of timekeeping in the

absence of V

 50 bytes of user NV RAM

PIN ASSIGNMENT

INTA

NC NC

A5 A4

A3 A2

A1 A0

DQ0 DQ1

DQ2

GND

1 2

3 4

5 6

7 8

9 10

11 12

13 14

28 27

26 25

24 23

22 21

20 19

18 17

16 15

WE INTB

NC NC

SQW OE

NC CE

DQ7 DQ6

DQ5 DQ4 DQ3

INTB

28-Pin Encapsulated Package

(720-Mil Flush)

PIN DESCRIPTION

INTA - Interrupt Output A (open drain) INTB (INTB) - Interrupt Output B (open drain)

A0-A5 - Address Inputs DQ0-DQ7 - Data Input/Output

CE - Chip Enable OE - Output Enable WE - Write Enable

- +5 Volts

GND - Ground NC - No Connection SQW - Square Wave Output

DESCRIPTION

The DS1286 Watchdog Timekeeper is a self-contained real time clock, alarm, watchdog timer, and interval timer in a 28-pin JEDEC DIP package. The DS1286 contains an embedded lithium energ y source and a quartz crystal which eliminates the need for any external circuitry. Data contained within 64 eightbit registers can be read or written in the same manner as bytewide static RAM. Data is maintained in the Watchdog Timekeeper by intelligent control circuitry which detects the status of V memory when V 10 years in the absence of V

is out of tolerance. The lithium energy source can maintain data and real time for over

. Watchdog Timekeeper information includes hundredths of seconds,

seconds, minutes, hours, day, date, month, and year. The date at the end of the month is automatically

1 of 13 111999

and write protects

DS1286

adjusted for months with less than 31 days, including correction for leap year. The Watchdog Timekeeper operates in either 24-hour or 12-hour format with an AM/PM indicator. The watchdog timer provides alarm windows and interval timing between 0.01 seconds and 99.99 seconds. The real time alarm provides for preset times of up to one week.

OPERATION - READ REGISTERS

The DS1286 executes a read cycle whenever WE (Write Enable) is inactive (High) and CE (Chip Enable) and OE (Output Enable) are active (Low). The unique address specified by the six address inputs

(A0-A5) defines which of the 64 registers is to be accessed. Valid data will be available to the eight data output drivers within t and OE access times are also satisfied. If OE and CE access times are not satisfied, then data access must

(Access Time) after the last address input signal is stable, providing that CE

ACC

be measured from the latter occu rring signal (CE or OE ) and the limiting parameter is either t or t

for OE rather than address access.

for CE

OPERATION - WRITE REGISTERS

The DS1286 is in the write mode whenever the WE (Write Enable) and CE (Chip Enable) signals are i n the active (Low) state after the address inputs are stable. The latter o ccurring falling edge of CE or WE will determine the start of the write cycle. The write cycle is terminated by the earlier rising edge of CE or WE . All address inputs must be kept valid throughout the write cycle. WE must return to the high state

for a minimum recovery state (tWR) before another cycle can be initiated. Data must be valid on the data bus with sufficient Data Set Up (tDS) and Data Hold Time (tDH) with respect to the earlier rising edge of

CE or WE . The OE control signal should be kept inactive (High) during write cycles to avoid bus

contention. However, if the output bus has been enabled (CE and OE active), then WE will disable the outputs in t

from its falling edge.

ODW

DATA RETENTION

The Watchdog Timekeeper provides full functional capability when V write protects the register contents at 4.25 volts typical. Data is maintained in the absence of V any additional support circuitry. The DS1286 constantly monitors V

the Watchdog Timekeeper will automatically write protect itself and all inputs to the registers become “Don’t Care.” Both INTA and INTB (INTB) are open drain outputs. The two interrupts and the internal

clock continue to run regardless of the level of VCC. However, it is important to insure that the pull-up resistors used with the interrupt pins are never pulled up to a value which is greater than V V

falls below approximately 3.0 volts, a power switching circuit turns on the lithium energy source to

maintain the clock, and timer data functionality. It is also required to insure that during this time (battery

is greater than 4.5 volts and

without

. Should the supply voltage decay,

+ 0.3V. As

backup mode), the voltage present at

INTA and INTB (INTB) never exceeds 3.0V. At all times the

current on each should not exceed +2.1 mA or -1.0 mA. However, if the active hi gh mode is selected for

INTB (INTB), this pin will only go high in the presence of V

approximately 3.0 volts, the power switching circuit connects external V lithium energy source. Normal operation can resume after V

. During power-up, when V

and disconnects the internal

exceeds 4.5 volts for a period of 150 ms.

rises above

2 of 13

DS1286

WATCHDOG TIMEKEEPER REGISTERS

The Watchdog Timekeeper has 64 registers which are 8 bits wide that contain all of the Timekeeping, Alarm, Watchdog, Control, and Data information. The Clock, Calendar, Alarm, and Watchdog registers are memory locations which contain external (user-accessible) and internal copies of the data. The external copies are independent of internal functions except that they are updated periodically by the simultaneous transfer of the incremented internal copy (see Figure 1). The Command Register bits are affected by both internal and external functions. This register will be discussed later. The 50 bytes of RAM registers can only be accessed from the external address and data bus. Registers 0, 1, 2, 4, 6, 8, 9, and A contain time of day and date information (see Figure 2). Time of Day information is stored in BCD. Registers 3, 5, and 7 contain the Time of Day Alarm information. Time of Da y Alarm information is stored in BCD. Register B is the Command Register and information in this register is binary. Registers C and D are the Watchdog Alarm registers and information which is stored in these two registers is in BCD. Registers E through 3F are user bytes and can be used to contain data at the user’s discretion.

3 of 13

BLOCK DIAGRAM Figure 1

DS1286

4 of 13

+ 9 hidden pages