Rainbow Electronics DS1251Y User Manual

www.maxim-ic.com

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DS1251/DS1251P

4096k NV SRAM with Phantom Clock

FEATURES

§ Real-time clock keeps track of hundredths of

seconds, minutes, hours, days, date of the month, months, and years

§ 512k x 8 NV SRAM directly replaces

volatile static RAM or EEPROM

§ Embedded lithium energy cell maintains

calendar operation and retains RAM data

§ Watch function is transparent to RAM

operation

§ Month and year determine the number of

days in each month; valid up to 2100

§ Over 10 years of data retention in the

absence of power

§ Full 10% operating range

§ Lithium energy source is electrically

disconnected to retain freshness until power is applied for the first time

§ DIP Module only – Standard 32-pin JEDEC pinout – Upward comparable with the DS1248

§ PowerCap® Module Board only – Surface mountable package for direct

connection to PowerCap containing

battery and crystal – Replaceable battery (PowerCap) – Pin for pin compatible with other densities

of DS124XP phantom clocks

PIN ASSIGNMENT

A18/RST

RST

A15 A16

OE CE

DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0

GND

A16 A14 A12

DQ0

DQ1

DQ2

GND

32-Pin Encapsulated Package

A7 A6 A5 A4 A3 A2 A1

3 4 5

6 7 8 9 10 11 12 13 14 15 16 17

2 3 4

5 6

7 8

9 10

11 12

740mil Flush

X1 GND

32 31

30 29

28 27

26 25

24 23

22 21

BAT

15 17

DQ7

DQ6

DQ5

DQ4

DQ3

34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18

18 17 14 13 12

11 10

6 5

1 0

34-Pin PowerCap Module Board

(Uses DS9034PCX PowerCap)

PowerCap is a registered trademark of Dallas Semiconductor.

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DS1251/DS1251P

ORDERING INFORMATION

DS1251YP–XXXY (5V)

- IND Industrial

- 70 70ns access

blank 32-Pin DIP Module

P 34-Pin PowerCap Module board*

DS1251WP-XXXY (3.3V)

- IND Industrial

- 120 120ns access

blank 32-Pin DIP Module

P 34-Pin PowerCap Module board*

*DS9034PCX (PowerCap) Required:

(Must be ordered separately.)

PIN DESCRIPTION

A0–A18 - Address Inputs

CE - Chip Enable

OE - Output Enable

WE - Write Enable

GND - Ground

–DQ7 - Data In/Data Out

NC - No Connection X1, X2 - Crystal Connection V

BAT

RST - Reset

- Power Supply Input

- Battery Connection

DESCRIPTION

The DS1251 4096k NV SRAM with Phantom Clock is a fully static nonvolatile RAM (organized as 512k words by 8 bits) with a built-in real-time clock. The DS1251Y has a self-contained lithium energy source and control circuitry, which constantly monitors V

for an out-of-tolerance condition. When such a

condition occurs, the lithium energy source is automatically switched on and write protection is unconditionally enabled to prevent garbled data in both the memory and real-time clock.

The phantom clock provides timekeeping information including hundredths of seconds, seconds, minutes, hours, days, dates, months, and years. The date at the end of the month is automatically adjusted for months with fewer than 31 days, including correction for leap years. The phantom clock operates in either 24-hour or 12-hour format with an AM/PM indicator.

PACKAGES

The DS1251 is available in two packages: 32-pin DIP and 34-pin PowerCap module. The 32-pin DIP style module integrates the crystal, lithium energy source, and silicon in one package. The 34-pin PowerCap module board is designed with contacts for connection to a separate PowerCap (DS9034PCX) that contains the crystal and battery. This design allows the PowerCap to be mounted on top of the DS1251P after the completion of the surface mount process. Mounting the PowerCap after the surface mount process prevents damage to the crystal and battery because of the high temperatures required for solder reflow. The PowerCap is keyed to prevent reverse insertion. The PowerCap Module Board and PowerCap are ordered separately and shipped in separate containers.

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DS1251/DS1251P

RAM READ MODE

The DS1251 executes a read cycle whenever WE (write enable) is inactive (high) and CE (chip enable) is active (low). The unique address specified by the 19 address inputs (A0–A18) defines which of the 512k bytes of data is to be accessed. Valid data will be available to the eight data-output drivers within t

(access time) after the last address input signal is stable, providing that CE and OE (output enable) access

times and states are also satisfied. If OE and CE access times are not satisfied, then data access must be

ACC

measured from the later occurring signal ( CE or OE ) and the limiting parameter is either t

for OE , rather than address access.

for CE or

RAM WRITE MODE

The DS1251 is in the write mode whenever the WE and CE signals are in the active (low) state after

address inputs are stable. The latter occurring falling edge of CE or WE will determine the start of the

write cycle. The write cycle is terminated by the earlier rising edge of CE or WE . All address inputs must

be kept valid throughout the write cycle. WE must return to the high state for a minimum recovery time

) before another cycle can be initiated. The OE control signal should be kept inactive (high) during

write cycles to avoid bus contention. However, if the output bus has been enabled ( CE and OE active)

then WE will disable the outputs in t

from its falling edge.

ODW

DATA RETENTION MODE

The 5V device is fully accessible and data can be written or read only when VCC is greater than VPF. However, when VCC is below the power-fail point, VPF (point at which write protection occurs), the internal clock registers and SRAM are blocked from any access. When VCC falls below the battery switch point, V operation and SRAM data are maintained from the battery until VCC is returned to nominal levels.

(battery supply level), device power is switched from the VCC pin to the backup battery. RTC

The 3.3V device is fully accessible and data can be written or read only when V When V the device power is switched from VCC to the backup supply (V greater than V below V

falls below the power-fail point, VPF , access to the device is inhibited. If VPF is less than VBAT,

) when VCC drops below V

BAT

, the device power is switched from V

BAT

. RTC operation and SRAM data are maintained from the battery until VCC is returned to

BAT

to the backup supply (VBAT ) when VCC drops

is greater than V

. If VPF is

PF.

nominal levels.

All control, data, and address signals must be powered down when VCC is powered down.

PHANTOM CLOCK OPERATION

Communication with the phantom clock is established by pattern recognition on a serial bit stream of 64 bits, which must be matched by executing 64 consecutive write cycles containing the proper data on DQ0. All accesses that occur prior to recognition of the 64-bit pattern are directed to memory.

After recognition is established, the next 64 read or write cycles either extract or update data in the phantom clock, and memory access is inhibited.

Data transfer to and from the timekeeping function is accomplished with a serial bit stream under control of chip enable, output enable, and write enable. Initially, a read cycle to any memory location using the

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DS1251/DS1251P

CE and OE control of the phantom clock starts the pattern recognition sequence by moving a pointer to

the first bit of the 64-bit comparison register. Next, 64 consecutive write cycles are executed using the

CE and WE control of the SmartWatch. These 64 write cycles are used only to gain access to the

phantom clock. Therefore, any address to the memory in the socket is acceptable. However, the write cycles generated to gain access to the phantom clock are also writing data to a location in the mated RAM. The preferred way to manage this requirement is to set aside just one address location in RAM as a phantom clock scratch pad. When the first write cycle is executed, it is compared to bit 0 of the 64-bit comparison register. If a match is found, the pointer increments to the next location of the comparison register and awaits the next write cycle. If a match is not found, the pointer does not advance and all subsequent write cycles are ignored. If a read cycle occurs at any time during pattern recognition, the present sequence is aborted and the comparison register pointer is reset. Pattern recognition continues for a total of 64 write cycles as described above until all the bits in the comparison register have been matched (Figure 1). With a correct match for 64 bits, the phantom clock is enabled and data transfer to or from the timekeeping registers can proceed. The next 64 cycles will cause the phantom clock to either

receive or transmit data on DQ0, depending on the level of the OE pin or the WE pin. Cycles to other

locations outside the memory block can be interleaved with CE cycles without interrupting the pattern recognition sequence or data transfer sequence to the phantom clock.

PHANTOM CLOCK REGISTER INFORMATION

The phantom clock information is contained in eight registers of 8 bits, each of which is sequentially accessed 1 bit at a time after the 64-bit pattern recognition sequence has been completed. When updating the phantom clock registers, each register must be handled in groups of 8 bits. Writing and reading individual bits within a register could produce erroneous results. These read/write registers are defined in Figure 2.

Data contained in the phantom clock register is in binary-coded decimal format (BCD). Reading and writing the registers is always accomplished by stepping through all eight registers, starting with bit 0 of register 0 and ending with bit 7 of register 7.

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PHANTOM CLOCK REGISTER DEFINITION Figure 1

DS1251/DS1251P

Note: The pattern recognition in Hex is C5, 3A, A3, 5C, C5, 3A, A3, 5C. The odds of this pattern being accidentally duplicated and causing inadvertent entry to the phantom clock is less than 1 in 1019. This pattern is sent to the phantom clock LSB to MSB.

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PHANTOM CLOCK REGISTER DEFINITION Figure 2

DS1251/DS1251P

AM/PM/12/24 MODE

Bit 7 of the hours register is defined as the 12-hour or 24-hour mode-select bit. When high, the 12-hour mode is selected. In the 12-hour mode, bit 5 is the AM/PM bit with logic high being PM. In the 24-hour mode, bit 5 is the second 10-hour bit (20–23 hours).

OSCILLATOR AND RESET BITS

Bits 4 and 5 of the day register are used to control the RESET and oscillator functions. Bit 4 controls the

RESET (pin 1). When the RESET bit is set to logic 1, the RESET input pin is ignored. When the RESET

bit is set to logic 0, a low input on the RESET pin will cause the phantom clock to abort data transfer without changing data in the watch registers. Bit 5 controls the oscillator. When set to logic 1, the oscillator is off. When set to logic 0, the oscillator turns on and the watch becomes operational. These bits are shipped from the factory set to a logic 1.

ZERO BITS

Registers 1, 2, 3, 4, 5, and 6 contain one or more bits which will always read logic 0. When writing these locations, either a logic 1 or 0 is acceptable.

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DS1251/DS1251P

BATTERY LONGEVITY

The DS1251 has a lithium power source that is designed to provide energy for clock activity, and clock and RAM data retention when the V

supply is not present. The capability of this internal power supply

is sufficient to power the DS1251 continuously for the life of the equipment in which it is installed. For specification purposes, the life expectancy is 10 years at +25°C with the internal clock oscillator running in the absence of V

power. Each DS1251 is shipped from Dallas Semiconductor with its lithium energy

source disconnected, guaranteeing full energy capacity. When VCC is first applied at a level greater than VPF, the lithium energy source is enabled for battery-backup operation. Actual life expectancy of the DS1251 will be much longer than 10 years since no lithium battery energy is consumed when VCC is present.

CLOCK ACCURACY (DIP MODULE)

The DS1251 is guaranteed to keep time accuracy to within ±1 minute per month at +25°C. The clock is calibrated at the factory by Dallas Semiconductor using special calibration nonvolatile tuning elements. The DS1251 does not require additional calibration and temperature deviations will have a negligible effect in most applications. For this reason, methods of field clock calibration are not available and not necessary.

CLOCK ACCURACY (POWERCAP MODULE)

The DS1251P and DS9034PCX are each individually tested for accuracy. Once mounted together, the module is guaranteed to keep time accuracy to within ±1.53 minutes per month (35ppm) at +25°C.

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