Rainbow Electronics DS1250Y-AB User Manual

DS1250Y/AB

DS1250Y/AB

4096K Nonvolatile SRAM

FEATURES

• 10 years minimum data retention in the absence of

external power

• Data is automatically protected during power loss

• Replaces 512K x 8 volatile static RAM, EEPROM or

Flash memory

• Unlimited write cycles

• Low–power CMOS

• Read and write access times as fast as 70 ns

• Lithium energy source is electrically disconnected to

retain freshness until power is applied for the first time

• Full ±10% V

• Optional ±5% V

operating range (DS1250Y)

CC

operating range (DS1250AB)

CC

• Optional industrial temperature range of –40°C to

+85°C, designated IND

• JEDEC standard 32–pin DIP package

• New PowerCap Module (PCM) package

– Directly surface–mountable module
– Replaceable snap–on PowerCap provides lith-

ium backup battery

– Standardized pinout for all nonvolatile SRAM

products

– Detachment feature on PCM allows easy

removal using a regular screwdriver

PIN ASSIGNMENT

1

A18
A16

2
3

A14
A12

4

A7

5

A6

6
7

A5
A4

8
9

A3
A2

10
11

A1
A0

12
13

DQ0
DQ1

14
15

DQ2

GND

16

32–PIN ENCAPSULATED PACKAGE

740 MIL EXTENDED

NC

1
2

NC

3

NC

4

NC

5

V

CC

6

WE

7

OE

8

CE

DQ7

9

DQ6

10

DQ5

11

DQ4

12

DQ3

13

DQ2

14

DQ1

15

DQ0

16

GND

17

34–PIN POWERCAP MODULE (PCM)

(USES DS9034PC POWERCAP)

GND V

BAT

32

V

CC

31

A15
A17

30
29

WE

28

A13

27

A8
A9

26
25

A11
OE

24
23

A10
CE

22
21

DQ7
DQ6

20
19

DQ5
DQ4

18
17

DQ3

NC

34

NC

33

A14

32

A13

31

A12

30

A11

29

A10

28

A9

27

A8

26

A7

25

A6

24

A5

23

A4

22

A3

21

A2

20

A1

19

A0

18

Copyright 1995 by Dallas Semiconductor Corporation.
All Rights Reserved. For important information regarding
patents and other intellectual property rights, please refer to
Dallas Semiconductor data books.

PIN DESCRIPTION

A0 – A14 – Address Inputs
DQ0 – DQ7 – Data In/Data Out
CE – Chip Enable
WE
OE – Output Enable
V

CC

GND – Ground
NC – No Charge

– Write Enable

– Power (+5V)

041497 1/11

DS1250Y/AB

DESCRIPTION

The DS1250 4096K Nonvolatile SRAMs are
4,194,304–bit, fully static, nonvolatile SRAMs orga­nized as 524,288 words by 8 bits. Each complete NV
SRAM has a self–contained lithium energy source and
control circuitry which constantly monitors V

CC

for an
out–of–tolerance condition. When such a condition oc­curs, the lithium energy source is automatically
switched on and write protection is unconditionally en­abled to prevent data corruption. DIP–package
DS1250 devices can be used in place of existing 512K x
8 static RAMs directly conforming to the popular byte­wide 32–pin DIP standard. DS1250 devices in the Pow­erCap Module package are directly surface mountable
and are normally paired with a DS9034PC PowerCap to
form a complete Nonvolatile SRAM module. There is no
limit on the number of write cycles that can be executed
and no additional support circuitry is required for micro­processor interfacing.

READ MODE

The DS1250 devices execute a read cycle whenever
WE (Write Enable) is inactive (high) and CE (Chip En­able) and OE

(Output Enable) are active (low). The
unique address specified by the 19 address inputs (A0 –
A18) defines which of the 524,288 bytes of data is to be
accessed. Valid data will be available to the eight data
output drivers within t
address input signal is stable, providing that CE

(Access Time) after the last

ACC

and OE
(Output Enable) access times are also satisfied. If OE
and CE access times are not satisfied, then data access
must be measured from the later occurring signal (CE or
OE) and the limiting parameter is either tCO for CE or t

OE

for OE rather than address access.

WRITE MODE

The DS1250 devices execute a write cycle whenever
the WE

and CE signals are active (low) after address in­puts are stable. The later occurring falling edge of CE
WE will determine the start of the write cycle. The write
cycle is terminated by the earlier rising edge of CE or
WE. All address inputs must be kept valid throughout
the write cycle. WE
minimum recovery time (t
be initiated. The OE

must return to the high state for a

) before another cycle can

WR

control signal should be kept inac­tive (high) during write cycles to avoid bus contention.
However, if the output drivers are enabled (CE and OE
active) then WE will disable the outputs in t

ODW

falling edge.

or

from its

DATA RETENTION MODE

The DS1250AB provides full functional capability for
VCC greater than 4.75 volts and write protects by

4.5 volts. The DS1250Y provides full functional capabil­ity for V

4.25 volts. Data is maintained in the absence of V

greater than 4.5 volts and write protects by

CC

CC

without any additional support circuitry . The nonvolatile
static RAMs constantly monitor VCC. Should the supply
voltage decay , the NV SRAMs automatically write pro­tect themselves, all inputs become “don’t care,” and all
outputs become high impedance. As V

falls below

CC

approximately 3.0 volts, a power switching circuit con­nects the lithium energy source to RAM to retain data.
During power–up, when VCC rises above approximately

3.0 volts, the power switching circuit connects external
to RAM and disconnects the lithium energy source.

V

CC

Normal RAM operation can resume after VCC exceeds

4.75 volts for the DS1250AB and 4.5 volts for the

DS1250Y.

FRESHNESS SEAL

Each DS1250 device is shipped from Dallas Semicon­ductor with its lithium energy source disconnected,
guaranteeing full energy capacity. When VCC is first
applied at a level greater than 4.25 volts, the lithium en­ergy source is enabled for battery back–up operation.

P ACKAGES

The DS1250 devices are available in two packages:
32–pin DIP and 34–pin PowerCap Module (PCM). The
32–pin DIP integrates a lithium battery, an SRAM
memory and a nonvolatile control function into a single
package with a JEDEC–standard 600 mil DIP pinout.
The 34–pin PowerCap Module integrates SRAM
memory and nonvolatile control along with contacts for
connection to the lithium battery in the DS9034PC Pow­erCap. The PowerCap Module package design allows
a DS1250 PCM device to be surface mounted without
subjecting its lithium backup battery to destructive high–
temperature reflow soldering. After a DS1250 PCM is
reflow soldered, a DS9034PC PowerCap is snapped on
top of the PCM to form a complete Nonvolatile SRAM
module. The DS9034PC is keyed to prevent improper
attachment. DS1250 PowerCap Modules and
DS9034PC PowerCaps are ordered separately and
shipped in separate containers. See the DS9034PC
data sheet for further information.

041497 2/11

DS1250Y/AB

ABSOLUTE MAXIMUM RATINGS*

Voltage on Any Pin Relative to Ground –0.3V to +7.0V
Operating Temperature 0°C to 70°C, –40°C to +85°C for Ind parts
Storage Temperature –40°C to +70°C, –40°C to +85°C for Ind parts
Soldering Temperature 260°C for 10 seconds

* This is a stress rating only and functional operation of the device at these or any other conditions above those

indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods of time may affect reliability.

RECOMMENDED DC OPERATING CONDITIONS (tA: See Note 10)

PARAMETER SYMBOL MIN TYP MAX UNITS NOTES

DS1250AB Power Supply Voltage V
DS1250Y Power Supply Voltage V
Logic 1 V
Logic 0 V

CC
CC

IH
IL

4.75 5.0 5.25 V

4.5 5.0 5.5 V

2.2 V

CC

0.0 +0.8 V

V

(VCC=5V ± 5% for DS1250AB)

DC ELECTRICAL CHARACTERISTICS (t

PARAMETER SYMBOL MIN TYP MAX UNITS NOTES

Input Leakage Current I
I/O Leakage Current

> VIH < V

CE

CC

Output Current @ 2.4V I
Output Current @ 0.4V I
Standby Current CE=2.2V I
Standby Current CE=VCC–0.5V I
Operating Current I
Write Protection Voltage

(DS1250AB)
Write Protection Voltage

(DS1250Y)

IL

I

IO

OH

OL
CCS1
CCS2
CCO1

V

TP

V

TP

–1.0 +1.0 µA
–1.0 +1.0 µA

–1.0 mA

4.50 4.62 4.75 V

4.25 4.37 4.5 V

: See Note 10) (VCC=5V ± 10% for DS1250Y)

A

2.0 mA

5.0 10.0 mA

3.0 5.0 mA
85 mA

CAPACITANCE (tA = 25°C)

PARAMETER SYMBOL MIN TYP MAX UNITS NOTES

Input Capacitance C
Input/Output Capacitance C

IN

I/O

5 10 pF
5 10 pF

041497 3/11

DS1250Y/AB

PARAMETER

SYMBOL

UNITS

NOTES

AC ELECTRICAL CHARACTERISTICS (t

DS1250AB–70

PARAMETER SYMBOL

Read Cycle Time t
Access Time t
OE to Output Valid t
CE to Output Valid t
OE or CE to Output Active t
Output High Z from Deselection t
Output Hold from Address

Change
Write Cycle Time t
Write Pulse Width t
Address Setup Time t
Write Recovery Time t

Output High Z from WE t
Output Active from WE t
Data Setup Time t
Data Hold Time t

RC

ACC

OE
CO

COE

OD

t

OH

WC
WP
AW

WR1

t

WR2
ODW
OEW

DS

DH1

t

DH2

DS1250Y–70

MIN MAX MIN MAX

70 100 ns

5 5 ns 5

5 5 ns

70 100 ns
55 75 ns 3

0 0 ns
5

15

5 5 ns 5

30 40 ns 4

0

10

(VCC=5V ± 5% for DS1250AB)

: See Note 10) (VCC=5V ± 10% for DS1250Y)

A

DS1250AB–100

DS1250Y–100

70 100 ns
35 50 ns
70 100 ns

25 35 ns 5

5

15

25 35 ns 5

0

10

UNITS NOTES

ns
ns

ns
ns

12
13

12
13

041497 4/11