Page 1
DS1249Y/AB
DS1249Y/AB
2048K Nonvolatile SRAM
FEATURES
• 10 years minimum data retention in the absence of
external power
• Data is automatically protected during power loss
• Unlimited write cycles
• Low–power CMOS operation
• Read and write access times as fast as 70 ns
• Lithium energy source is electrically disconnected to
retain freshness until power is applied for the first time
• Full ± 10% V
• Optional ± 5% V
operating range (DS1249Y)
CC
operating range (DS1249AB)
CC
• Optional industrial temperature range of –40°C to
+85°C, designated IND
• JEDEC standard 32–pin DIP package
PIN ASSIGNMENT
1
NC
2
A16
3
A14
4
A12
5
A7
6
A6
7
A5
8
A4
9
A3
10
A2
11
A1
12
A0
13
DQ0
14
DQ1
15
DQ2
16
GND
32–PIN ENCAPSULATED PACKAGE
740 MIL EXTENDED
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
PIN DESCRIPTION
A0 – A17 – Address Inputs
DQ0 – DQ7 – Data In/Data Out
CE
WE – Write Enable
OE – Output Enable
V
CC
GND – Ground
NC – No Connect
– Chip Enable
– Power (+5V)
V
CC
A15
A17
WE
A13
A8
A9
A11
OE
A10
CE
DQ7
DQ6
DQ5
DQ4
DQ3
DESCRIPTION
The DS1249 2048K Nonvolatile SRAMs are
2,097,152–bit, fully static, nonvolatile SRAMs organized as 262,144 words by 8 bits. Each NV SRAM has a
self–contained lithium energy source and control circuitry which constantly monitors V
erance condition. When such a condition occurs, the
Copyright 1995 by Dallas Semiconductor Corporation.
All Rights Reserved. For important information regarding
patents and other intellectual property rights, please refer to
Dallas Semiconductor data books.
for an out–of–tol-
CC
lithium energy source is automatically switched on and
write protection is unconditionally enabled to prevent
data corruption. There is no limit on the number of write
cycles which can be executed and no additional support
circuitry is required for microprocessor interfacing.
021497 1/9
Page 2
DS1249Y/AB
READ MODE
The DS1249 devices execute a read cycle whenever
WE (Write Enable) is inactive (high) and CE (Chip Enable) and OE (Output Enable) are active (low). The
unique address specified by the 18 address inputs (A
0
A17) defines which of the 262,144 bytes of data is accessed. Valid data will be available to the eight data output drivers within t
(Access Time) after the last ad-
ACC
dress input signal is stable, providing that CE and OE
access times are also satisfied. If OE and CE access
times are not satisfied, then data access must be measured from the later occurring signal (CE
or OE) and the
limiting parameter is either tCO for CE or tOE for OE rath-
ACC
.
er than t
WRITE MODE
The DS1249 devices execute a write cycle whenever
the WE and CE signals are active (low) after address inputs are stable. The later occurring falling edge of CE or
will determine the start of the write cycle. The write
WE
cycle is terminated by the earlier rising edge of CE or
WE. All address inputs must be kept valid throughout
the write cycle. WE must return to the high state for a
minimum recovery time (tWR) before another cycle can
be initiated. The OE
tive (high) during write cycles to avoid bus contention.
However, if the output drivers are enabled (CE and OE
active) then WE will disable the outputs in t
falling edge.
control signal should be kept inac-
from its
ODW
DATA RETENTION MODE
The DS1249AB provides full functional capability for
VCC greater than 4.75 volts and write protects by 4.5
volts. The DS1249Y provides full functional capability
–
greater than 4.5 volts and write protects by 4.25
for V
CC
volts. Data is maintained in the absence of VCC without
any additional support circuitry. The nonvolatile static
RAMs constantly monitor VCC. Should the supply voltage decay, the NV SRAMs automatically write protects
themselves, all inputs become “don’t care,” and all outputs become high impedance. As V
CC
proximately 3.0 volts, a power switching circuit connects the lithium energy source to RAM to retain data.
During power–up, when V
rises above approximately
CC
3.0 volts, the power switching circuit connects external
VCC to the RAM and disconnects the lithium energy
source. Normal RAM operation can resume after V
exceeds 4.75 volts for the DS1249AB and 4.5 volts for
the DS1249Y.
FRESHNESS SEAL
Each DS1249 device is shipped from Dallas Semiconductor with its lithium energy source disconnected,
guaranteeing full energy capacity. When VCC is first
applied at a level greater than V
source is enabled for battery backup operation.
, the lithium energy
TP
falls below ap-
CC
021497 2/9
Page 3
DS1249Y/AB
ABSOLUTE MAXIMUM RATINGS*
Voltage on Any Pin Relative to Ground –0.3V to +7.0V
Operating Temperature 0°C to 70°C, –40°C to +85°C for Ind parts
Storage Temperature –40°C to +70°C, –40°C to +85°C for Ind parts
Soldering Temperature 260°C for 10 seconds
* This is a stress rating only and functional operation of the device at these or any other conditions above those
indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods of time may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS (tA: See Note 10)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
DS1249AB Power Supply Voltage V
DS1249Y Power Supply Voltage V
Logic 1 V
Logic 0 V
CC
CC
IH
IL
4.75 5.0 5.25 V
4.5 5.0 5.5 V
2.2 V
CC
0.0 +0.8 V
V
(VCC=5V ± 5% for DS1249AB)
DC ELECTRICAL CHARACTERISTICS (t
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Input Leakage Current I
I/O Leakage Current
> VIH < V
CE
CC
Output Current @ 2.4V I
Output Current @ 0.4V I
Standby Current CE=2.2V I
Standby Current CE=VCC–0.5V I
Operating Current I
Write Protection Voltage
(DS1249AB)
Write Protection Voltage
(DS1249Y)
IL
I
IO
OH
OL
CCS1
CCS2
CCO1
V
TP
V
TP
–2.0 +2.0 µA
–2.0 +2.0 µA
–1.0 mA
4.50 4.62 4.75 V
4.25 4.37 4.50 V
: See Note 10) (VCC=5V ± 10% for DS1249Y)
A
2.0 mA
1.0 1.5 mA
100 150 µA
85 mA
CAPACITANCE (tA = 25°C)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Input Capacitance C
Input/Output Capacitance C
IN
I/O
10 20 pF
10 20 pF
021497 3/9
Page 4
DS1249Y/AB
(VCC=5V ± 5% for DS1249AB)
AC ELECTRICAL CHARACTERISTICS (t
DS1249AB–70
DS1249Y–70
PARAMETER SYMBOL MIN MAX MIN MAX UNITS NOTES
Read Cycle Time t
Access Time t
OE to Output Valid t
CE to Output Valid t
OE or CE to Output Active t
Output High–Z from Deselection t
Output Hold from Address
Change
Write Cycle Time t
Write Pulse Width t
Address Setup Time t
Write Recovery Time t
Output High–Z from WE t
Output Active from WE t
Data Setup Time t
Data Hold Time t
RC
ACC
OE
CO
COE
OD
t
OH
WC
WP
AW
WR1
t
WR2
ODW
OEW
DS
DH1
t
DH2
70 100 ns
5 5 ns 5
5 5 ns
70 100 ns
55 75 ns 3
0 0 ns
5
15
5 5 ns 5
30 40 ns 4
0
10
: See Note 10) (VCC=5V ±10% for DS1249Y)
A
DS1249AB–100
DS1249Y–100
70 100 ns
35 50 ns
70 100 ns
25 35 ns 5
5
15
ns
ns
12
13
25 35 ns 5
0
10
ns
ns
12
13
021497 4/9
Page 5
READ CYCLE
ADDRESSES
CE t
OE
D
OUT
SEE NOTE 1
WRITE CYCLE 1
ADDRESSES
DS1249Y/AB
t
RC
V
IH
V
IL
t
V
ACC
IH
CO
V
IL
V
IH
t
OE
V
IL
t
COE
t
COE
V
V
t
WC
V
IH
V
IL
V
V
IH
OUTPUT
OH
DATA VALID
OL
V
IH
V
IL
IH
V
IH
V
IL
t
OH
t
OD
t
OD
V
OH
V
OL
V
V
IH
V
IH
V
IL
IL
CE
WE
D
OUT
D
IN
SEE NOTES 2, 3, 4, 6, 7, 8, and 12
t
AW
V
V
IH
t
ODW
V
IL
IL
t
WP
HIGH
IMPEDANCE
V
IH
V
IL
t
WR1
V
t
OEW
IH
t
DH1
V
IH
V
IL
t
DS
DATA IN STABLE
V
IL
V
IL
021497 5/9
Page 6
DS1249Y/AB
WRITE CYCLE 2
t
WC
V
ADDRESSES
CE
IH
V
IL
t
AW
V
IH
V
IL
WE
t
COE
D
OUT
D
IN
SEE NOTES 2, 3, 4, 6, 7, 8 AND 13
POWER–DOWN/POWER–UP CONDITION
V
CC
V
IH
V
IL
t
WP
V
IL
V
IL
V
IL
V
IL
t
ODW
t
DS
V
IH
t
WR2
V
IH
V
IH
t
DH2
V
IH
V
IL
V
IH
DATA IN STABLE
V
IL
V
IL
BACKUP CURRENT
SUPPLIED FROM
LITHIUM BATTERY
SEE NOTE 11
021497 6/9
V
TP
3.0V
CE
WE
t
F
t
PD
t
R
t
REC
t
PU
,
t
DR
Page 7
DS1249Y/AB
POWER–DOWN/POWER–UP TIMING (tA: See Note 10)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
VCC Fail Detect to CE and WE
Inactive
VCC Slew from VTP to 0V t
VCC Slew from 0V to V
TP
VCC Valid to CE and WE Inactive t
VCC Valid to End of W rite
Protection
t
t
REC
PD
t
PU
1.5 µs 11
F
R
150 µs
150 µs
2 ms
125 ms
(tA = 25°C)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Expected Data Retention Time t
DR
10 years 9
WARNING:
Under no circumstance are negative undershoots, of any amplitude, allowed when device is in battery backup mode.
NOTES:
1. WE is high throughout read cycle.
= VIH or VIL. If OE = VIH during write cycle, the output buffers remain in a high impedance state.
2. OE
is specified as the logical AND of CE and WE. tWP is measured from the latter of CE or WE going low to the
3. t
WP
earlier of CE
is measured from the earlier of CE or WE going high.
4. t
DS
5. These parameters are sampled with a 5 pF load and are not 100% tested.
6. If the CE
buffers remain in a high impedance state during this period.
7. If the CE
in high impedance state during this period.
8. If WE
remain in a high impedance state during this period.
9. Each DS1249 has a built–in switch that disconnects the lithium source until V
expected t
by the user.
10.All AC and DC electrical characteristics are valid over the full operating temperature range. For commercial prod-
ucts, this range is 0°C to 70°C for industrial products (IND), this range is –40°C to +85°C.
11.In a power down condition the voltage on any pin may not exceed the voltage on V
12.t
WR1
13.t
WR2
or WE going high.
low transition occurs simultaneously with or later than the WE low transition in Write Cycle 1, the output
high transition occurs prior to or simultaneously with the WE high transition, the output buffers remain
is low or the WE low transition occurs prior to or simultaneously with the CE low transition, the output buffers
is first applied by the user. The
is defined as accumulative time in the absence of VCC starting from the time power is first applied
DR
, t
are measured from WE going high.
DH1
, t
are measured from CE going high.
DH2
CC
CC
.
021497 7/9
Page 8
DS1249Y/AB
DC TEST CONDITIONS
Outputs Open
Cycle = 200 ns for operating current
All voltages are referenced to ground
ORDERING INFORMATION
DS1249 TTP–
SSS –
III
Operating Temperature Range
blank: 0° to 70°
IND: –40° to 85°C
Speed
Access
70 ns
70:
100 ns
100:
Package
blank: 32–pin 600 mil DIP
VCC Tolerance
Y: ± 10%
AB: ± 5%
AC TEST CONDITIONS
Output Load: 100 pF + 1TTL Gate
Input Pulse Levels: 0V to 3.0V
Timing Measurement Reference Levels
Input: 1.5V
Output: 1.5V
Input pulse Rise and Fall Times: 5 ns
021497 8/9
Page 9
DS1249Y/AB NONVOLATILE SRAM, 32–PIN 740 MIL EXTENDED MODULE
PKG 32–PIN
1
J
A
C
F
GKD
E
H
B
DIM MIN MAX
A IN.MM2.080
B IN.MM0.715
C IN.MM0.395
D IN.MM0.280
E IN.MM0.015
F IN.MM0.120
G IN.MM0.090
H INMM0.590
J INMM0.008
K IN.MM0.015
52.83
18.16
10.03
7.11
0.38
3.05
2.29
14.99
0.20
0.43
DS1249Y/AB
2.100
53.34
0.740
18.80
0.405
10.29
0.310
7.49
0.030
0.76
0.160
4.06
0.110
2.79
0.630
16.00
0.012
0.30
0.025
0.58
021497 9/9
Loading...