Rainbow Electronics DS1249Y-AB User Manual
DS1249Y/AB
DS1249Y/AB
2048K Nonvolatile SRAM
FEATURES
• 10 years minimum data retention in the absence of
external power
• Data is automatically protected during power loss
• Unlimited write cycles
• Low–power CMOS operation
• Read and write access times as fast as 70 ns
• Lithium energy source is electrically disconnected to
retain freshness until power is applied for the first time
• Full ± 10% V
• Optional ± 5% V
operating range (DS1249Y)
CC
operating range (DS1249AB)
CC
• Optional industrial temperature range of –40°C to
+85°C, designated IND
• JEDEC standard 32–pin DIP package
PIN ASSIGNMENT
1
NC
2
A16
3
A14
4
A12
5
A7
6
A6
7
A5
8
A4
9
A3
10
A2
11
A1
12
A0
13
DQ0
14
DQ1
15
DQ2
16
GND
32–PIN ENCAPSULATED PACKAGE
740 MIL EXTENDED
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
PIN DESCRIPTION
A0 – A17 – Address Inputs
DQ0 – DQ7 – Data In/Data Out
CE
WE – Write Enable
OE – Output Enable
V
CC
GND – Ground
NC – No Connect
– Chip Enable
– Power (+5V)
V
CC
A15
A17
WE
A13
A8
A9
A11
OE
A10
CE
DQ7
DQ6
DQ5
DQ4
DQ3
DESCRIPTION
The DS1249 2048K Nonvolatile SRAMs are
2,097,152–bit, fully static, nonvolatile SRAMs organized as 262,144 words by 8 bits. Each NV SRAM has a
self–contained lithium energy source and control circuitry which constantly monitors V
erance condition. When such a condition occurs, the
Copyright 1995 by Dallas Semiconductor Corporation.
All Rights Reserved. For important information regarding
patents and other intellectual property rights, please refer to
Dallas Semiconductor data books.
for an out–of–tol-
CC
lithium energy source is automatically switched on and
write protection is unconditionally enabled to prevent
data corruption. There is no limit on the number of write
cycles which can be executed and no additional support
circuitry is required for microprocessor interfacing.
021497 1/9
DS1249Y/AB
READ MODE
The DS1249 devices execute a read cycle whenever
WE (Write Enable) is inactive (high) and CE (Chip Enable) and OE (Output Enable) are active (low). The
unique address specified by the 18 address inputs (A
0
A17) defines which of the 262,144 bytes of data is accessed. Valid data will be available to the eight data output drivers within t
(Access Time) after the last ad-
ACC
dress input signal is stable, providing that CE and OE
access times are also satisfied. If OE and CE access
times are not satisfied, then data access must be measured from the later occurring signal (CE
or OE) and the
limiting parameter is either tCO for CE or tOE for OE rath-
ACC
.
er than t
WRITE MODE
The DS1249 devices execute a write cycle whenever
the WE and CE signals are active (low) after address inputs are stable. The later occurring falling edge of CE or
will determine the start of the write cycle. The write
WE
cycle is terminated by the earlier rising edge of CE or
WE. All address inputs must be kept valid throughout
the write cycle. WE must return to the high state for a
minimum recovery time (tWR) before another cycle can
be initiated. The OE
tive (high) during write cycles to avoid bus contention.
However, if the output drivers are enabled (CE and OE
active) then WE will disable the outputs in t
falling edge.
control signal should be kept inac-
from its
ODW
DATA RETENTION MODE
The DS1249AB provides full functional capability for
VCC greater than 4.75 volts and write protects by 4.5
volts. The DS1249Y provides full functional capability
–
greater than 4.5 volts and write protects by 4.25
for V
CC
volts. Data is maintained in the absence of VCC without
any additional support circuitry. The nonvolatile static
RAMs constantly monitor VCC. Should the supply voltage decay, the NV SRAMs automatically write protects
themselves, all inputs become “don’t care,” and all outputs become high impedance. As V
CC
proximately 3.0 volts, a power switching circuit connects the lithium energy source to RAM to retain data.
During power–up, when V
rises above approximately
CC
3.0 volts, the power switching circuit connects external
VCC to the RAM and disconnects the lithium energy
source. Normal RAM operation can resume after V
exceeds 4.75 volts for the DS1249AB and 4.5 volts for
the DS1249Y.
FRESHNESS SEAL
Each DS1249 device is shipped from Dallas Semiconductor with its lithium energy source disconnected,
guaranteeing full energy capacity. When VCC is first
applied at a level greater than V
source is enabled for battery backup operation.
, the lithium energy
TP
falls below ap-
CC
021497 2/9
DS1249Y/AB
ABSOLUTE MAXIMUM RATINGS*
Voltage on Any Pin Relative to Ground –0.3V to +7.0V
Operating Temperature 0°C to 70°C, –40°C to +85°C for Ind parts
Storage Temperature –40°C to +70°C, –40°C to +85°C for Ind parts
Soldering Temperature 260°C for 10 seconds
* This is a stress rating only and functional operation of the device at these or any other conditions above those
indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods of time may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS (tA: See Note 10)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
DS1249AB Power Supply Voltage V
DS1249Y Power Supply Voltage V
Logic 1 V
Logic 0 V
CC
CC
IH
IL
4.75 5.0 5.25 V
4.5 5.0 5.5 V
2.2 V
CC
0.0 +0.8 V
V
(VCC=5V ± 5% for DS1249AB)
DC ELECTRICAL CHARACTERISTICS (t
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Input Leakage Current I
I/O Leakage Current
> VIH < V
CE
CC
Output Current @ 2.4V I
Output Current @ 0.4V I
Standby Current CE=2.2V I
Standby Current CE=VCC–0.5V I
Operating Current I
Write Protection Voltage
(DS1249AB)
Write Protection Voltage
(DS1249Y)
IL
I
IO
OH
OL
CCS1
CCS2
CCO1
V
TP
V
TP
–2.0 +2.0 µA
–2.0 +2.0 µA
–1.0 mA
4.50 4.62 4.75 V
4.25 4.37 4.50 V
: See Note 10) (VCC=5V ± 10% for DS1249Y)
A
2.0 mA
1.0 1.5 mA
100 150 µA
85 mA
CAPACITANCE (tA = 25°C)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Input Capacitance C
Input/Output Capacitance C
IN
I/O
10 20 pF
10 20 pF
021497 3/9
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