DS1248Y
DS1248Y
1024K NV SRAM with Phantom Clock
FEATURES
• Real time clock keeps track of hundredths of seconds,
minutes, hours, days, date of the month, months, and
years
• 128K x 8 NV SRAM directly replaces volatile static
RAM or EEPROM
• Embedded lithium energy cell maintains calendar op-
eration and retains RAM data
• Watch function is transparent to RAM operation
• Month and year determine the number of days in each
month; valid up to 2100
• Standard 28–pin JEDEC pinout
• Full 10% operating range
• Operating temperature range 0°C to 70°C
• Accuracy is better than ±1 minute/month @ 25°C
• Over 10 years of data retention in the absence of
power
• Available in 120, 150 and 200 ns access time
ORDERING INFORMATION
DS1248Y–XXX
–120 120 ns access
–150 150 ns access
–200 200 ns access
PIN ASSIGNMENT
RST
1
A16
2
A14
3
A12
4
A7
5
A6
6
A5
7
A4
8
A3
9
A2
10
A1
11
A0
12
DQ0
13
DQ1
14
DQ2
15
GND
16
32–PIN ENCAPSULATED PACKAGE
740 MIL FLUSH
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
PIN DESCRIPTION
Ao–A
16
CE – Chip Enable
GND – Ground
DQ0–DQ
V
CC
WE – Write Enable
OE – Output Enable
NC – No Connect
RST
– Address Inputs
– Data In/Data Out
7
– Power (+5V)
– Reset
V
CC
A15
NC
WE
A13
A8
A9
A11
OE
A10
CE
DQ7
DQ6
DQ5
DQ4
DQ3
DESCRIPTION
The DS1248Y 1024K NV SRAM with Phantom Clock is
a fully static nonvolatile RAM (organized as 128K words
by 8 bits) with a built–in real time clock. The DS1248Y
has a self–contained lithium energy source and control
circuitry which constantly monitors VCC for an out–of–
tolerance condition. When such a condition occurs, the
lithium energy source is automatically switched on and
write protection is unconditionally enabled to prevent
garbled data in both the memory and real time clock.
Copyright 1997 by Dallas Semiconductor Corporation.
All Rights Reserved. For important information regarding
patents and other intellectual property rights, please refer to
Dallas Semiconductor data books.
The Phantom Clock provides timekeeping information
including hundredths of seconds, seconds, minutes,
hours, day, date, month, and year information. The date
at the end of the month is automatically adjusted for
months with less than 31 days, including correction for
leap years. The Phantom Clock operates in either
24–hour or 12–hour format with an AM/PM indicator.
032697 1/12
DS1248Y
RAM READ MODE
The DS1248Y executes a read cycle whenever WE
(Write Enable) is inactive (high) and CE (Chip Enable) is
active (low). The unique address specified by the 17 address inputs (A0–A16) defines which of the 128K bytes
of data is to be accessed. Valid data will be available to
the eight data output drivers within t
(Access Time)
ACC
after the last address input signal is stable, providing
that CE and OE (Output Enable) access times and
states are also satisfied. If OE and CE access times are
not satisfied, then data access must be measured from
the later occurring signal (CE
or OE) and the limiting parameter is either tCO for CE or tOE for OE rather than address access.
RAM WRITE MODE
The DS1248Y is in the write mode whenever the WE
and CE signals are in the active (low) state after address
inputs are stable. The latter occurring falling edge of CE
or WE will determine the start of the write cycle. The
write cycle is terminated by the earlier rising edge of CE
or WE. All address inputs must be kept valid throughout
the write cycle. WE must return to the high state for a
minimum recovery time (tWR) before another cycle can
be initiated. The OE
control signal should be kept inactive (high) during write cycles to avoid bus contention.
However, if the output bus has been enabled (CE and
OE active) then WE will disable the outputs in t
ODW
from
its falling edge.
DATA RETENTION MODE
The DS1248Y provides full functional capability for V
greater than 4.5 volts and write protects by approximately 4.0 volts. Data is maintained in the absence of
without any additional support circuitry. The non-
V
CC
volatile static RAM constantly monitors V
. Should the
CC
supply voltage decay, the RAM automatically write protects itself. All inputs to the RAM become “don’t care”
and all outputs are high impedance. As V
CC
approximately 3.0 volts, the power switching circuit connects the lithium energy source to RAM to retain data.
During power–up, when V
rises above approximately
CC
3.0 volts, the power switching circuit connects external
VCC to the RAM and disconnects the lithium energy
source. Normal RAM operation can resume after V
exceeds 4.5 volts.
CC
falls below
CC
PHANTOM CLOCK OPERATION
Communication with the Phantom Clock is established
by pattern recognition on a serial bit stream of 64 bits
which must be matched by executing 64 consecutive
write cycles containing the proper data on DQ0. All accesses which occur prior to recognition of the 64–bit pattern are directed to memory.
After recognition is established, the next 64 read or write
cycles either extract or update data in the Phantom
Clock, and memory access is inhibited.
Data transfer to and from the timekeeping function is accomplished with a serial bit stream under control of Chip
Enable (CE
(WE
ing the CE and OE control of the Phantom Clock starts
the pattern recognition sequence by moving a pointer to
the first bit of the 64–bit comparison register. Next, 64
consecutive write cycles are executed using the CE and
WE
are used only to gain access to the Phantom Clock.
Therefore, any address to the memory in the socket is
acceptable. However, the write cycles generated to
gain access to the Phantom Clock are also writing data
to a location in the mated RAM. The preferred way to
manage this requirement is to set aside just one address location in RAM as a Phantom Clock scratch pad.
When the first write cycle is executed, it is compared to
bit 0 of the 64–bit comparison register. If a match is
found, the pointer increments to the next location of the
comparison register and awaits the next write cycle. If a
match is not found, the pointer does not advance and all
subsequent write cycles are ignored. If a read cycle occurs at any time during pattern recognition, the present
sequence is aborted and the comparison register pointer is reset. Pattern recognition continues for a total of 64
write cycles as described above until all the bits in the
comparison register have been matched (this bit pattern
is shown in Figure 1). With a correct match for 64 bits,
the Phantom Clock is enabled and data transfer to or
from the timekeeping registers can proceed. The next
64 cycles will cause the Phantom Clock to either receive
or transmit data on DQ0, depending on the level of the
pin or the WE pin. Cycles to other locations outside
OE
the memory block can be interleaved with CE
without interrupting the pattern recognition sequence or
data transfer sequence to the Phantom Clock.
), Output Enable (OE), and Write Enable
). Initially, a read cycle to any memory location us-
control of the SmartWatch. These 64 write cycles
cycles
032697 2/12
DS1248Y
PHANTOM CLOCK
REGISTER INFORMATION
in a register could produce erroneous results. These
read/write registers are defined in Figure 2.
The Phantom Clock information is contained in 8 registers of 8 bits, each of which is sequentially accessed one
bit at a time after the 64–bit pattern recognition sequence has been completed. When updating the Phantom Clock registers, each register must be handled in
groups of 8 bits. Writing and reading individual bits with-
Data contained in the Phantom Clock register is in
binary coded decimal format (BCD). Reading and writ-
ing the registers is always accomplished by stepping
through all 8 registers, starting with bit 0 of register 0 and
ending with bit 7 of register 7.
PHANTOM CLOCK REGISTER DEFINITION Figure 1
76543210
BYTE 0
BYTE 1
BYTE 2
BYTE 3
11000101
00111010
10100011
01011100
HEX
VALUE
C5
3A
A3
5C
BYTE 4
BYTE 5
BYTE 6
BYTE 7
11000101
00111010
10100011
01011100
C5
3A
A3
5C
NOTE:
The pattern recognition in Hex is C5, 3A, A3, 5C, C5, 3A, A3, 5C. The odds of this pattern being accidentally duplicated and causing inadvertent entry to the Phantom Clock is less than 1 in 10
Clock LSB to MSB.
19
. This pattern is sent to the Phantom
032697 3/12
DS1248Y
PHANTOM CLOCK REGISTER DEFINITION Figure 2
REGISTER
76543210
0
0.1 SEC
0.01 SEC
RANGE
(BCD)
00–99
1
2
3
4
5
6
7
0
0
12/24 0
00 0
00
000
10 SEC SECONDS
10 MIN MINUTES
10
OSC
10 YEAR YEAR
HR
A/P
RST
10 DATE DATE
10
MONTH
AM–PM/12/24 MODE
Bit 7 of the hours register is defined as the 12– or
24–hour mode select bit. When high, the 12–hour mode
is selected. In the 12–hour mode, bit 5 is the AM/PM bit
with logic high being PM. In the 24–hour mode, bit 5 is
the second 10–hour bit (20–23 hours).
00–59
00–59
HOUR
DAY
MONTH
to logic 0, a low input on the RESET
01–12
00–23
01–07
01–31
01–12
00–99
pin will cause the
Phantom Clock to abort data transfer without changing
data in the watch registers. Bit 5 controls the oscillator .
When set to logic 1, the oscillator is off. When set to logic 0, the oscillator turns on and the watch becomes operational. These bits are shipped from the factory set to
a logic 1.
OSCILLATOR AND RESET BITS
Bits 4 and 5 of the day register are used to control the
RESET and oscillator functions. Bit 4 controls the
(pin 1). When the RESET bit is set to logic 1, the
RESET
RESET input pin is ignored. When the RESET bit is set
032697 4/12
ZERO BITS
Registers 1, 2, 3, 4, 5, and 6 contain one or more bits
which will always read logic 0. When writing these locations, either a logic 1 or 0 is acceptable.
DS1248Y
ABSOLUTE MAXIMUM RATINGS*
Voltage on Any Pin Relative to Ground –0.3V to +7.0V
Operating Temperature 0°C to 70°C
Storage Temperature –40°C to +70°C
Soldering Temperature 260°C for 10 seconds (See Note 13)
* This is a stress rating only and functional operation of the device at these or any other conditions above those
indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods of time may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS (0°C to 70°C)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Power Supply Voltage V
Input Logic 1 V
Input Logic 0 V
CC
IH
IL
4.5 5.0 5.5 V
2.2 VCC+0.3 V
–0.3 0.8 V
DC ELECTRICAL CHARACTERISTICS (0°C to 70°C; VCC = 5V ± 10%)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Input Leakage Current I
I/O Leakage Current
VIH V
CE
CC
Output Current @ 2.4V I
Output Current @ 0.4V I
Standby Current CE = 2.2V I
Standby Current CE = VCC – 0.5V I
Operating Current t
= 200 ns I
CYC
IL
I
IO
OH
OL
CCS1
CCS2
CC01
–1.0 +1.0 µA 12
–1.0 +1.0 µA
–1.0 mA
2.0 mA
5.0 10 mA
3.0 5.0 mA
85 mA
DC TEST CONDITIONS
Outputs are open; all voltages are referenced to ground.
CAPACIT ANCE (tA = 25°C)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Input Capacitance C
Input/Output Capacitance C
IN
I/O
5 10 pF
5 10 pF
032697 5/12
DS1248Y
PARAMETER
SYMBOL
UNITS
NOTES
MEMORY AC ELECTRICAL CHARACTERISTICS (0°C to 70°C; VCC = 5.0V ± 10%)
Read Cycle Time t
Access Time t
OE to Output Valid t
CE to Output Valid t
OE or CE to Output Active t
Output High Z from Deselection t
Output Hold from Address
Change
Write Cycle Time t
Write Pulse Width t
Address Setup Time t
Write Recovery Time t
Output High Z from WE t
Output Active from WE t
Data Setup Time t
Data Hold Time from WE t
RC
ACC
OE
CO
COE
OD
t
oH
WC
WP
AW
WR
ODW
OEW
DS
DH
DS1248Y–120
MIN MAX MIN MAX MIN MAX
120 150 200 ns
5 5 5 ns 5
5 5 5 ns
120 150 200 ns
90 100 150 ns 3
0 0 0 ns
20 20 20 ns
5 5 5 ns 5
50 60 80 ns 4
20 20 20 ns 4
DS1248Y–150 DS1248Y–200
120 150 200 ns
60 70 100 ns
120 150 200 ns
40 70 100 ns 5
40 70 80 ns 5
AC TEST CONDITIONS
Output Load: 50 pF + 1TTL Gate
Input Pulse Levels: 0–3V
Timing Measurement Reference Levels
Input: 1.5V
Output: 1.5V
Input Pulse Rise and Fall Times: 5 ns
032697 6/12
DS1248Y
PHANTOM CLOCK AC ELECTRICAL CHARACTERISTICS (0°C to 70°C; VCC = 4.5 to 5.5V)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Read Cycle Time t
CE Access Time t
OE Access Time t
CE to Output Low Z t
OE to Output Low Z t
CE to Output High Z t
OE to Output High Z t
Read Recovery t
Write Cycle Time t
Write Pulse Width t
Write Recovery t
Data Setup Time t
Data Hold Time t
CE Pulse Width t
RESET Pulse Width t
CE High to Power–Fail t
RC
CO
OE
COE
OEE
OD
ODO
RR
WC
WP
WR
DS
DH
CW
RST
PF
120 ns
100 ns
100 ns
10 ns
10 ns
40 ns 5
40 ns 5
20 ns
120 ns
100 ns
20 ns 10
40 ns 11
10 ns 11
100 ns
200 ns
0 ns
POWER-DOWN/POWER-UP TIMING
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
CE at VIH before Power–Down t
VCC Slew from 4.5V to 0V
at VIH)
(CE
VCC Slew from 0V to 4.5V
at VIH)
(CE
CE at VIH after Power–Up t
PD
t
F
t
R
REC
0 µs
300 µs
0 µs
2 ms
(tA = 25°C)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Expected Data Retention Time t
DR
10 years 9
WARNING:
Under no circumstances are negative undershoots, of any amplitude, allowed when device is in battery backup mode.
032697 7/12
DS1248Y
MEMORY READ CYCLE (NOTE 1)
V
ADDRESSES
CE
OE
D
OUT
IH
V
IL
t
ACC
V
IH
t
CO
V
IL
V
IH
t
COE
t
COE
t
OE
V
IL
MEMORY WRITE CYCLE 1 (NOTES 2, 6, AND 7)
V
ADDRESS
IH
V
IL
t
AW
t
RC
V
V
IH
V
V
IH
V
IH
V
OH
OUTPUT
DATA VALID
V
OL
t
WC
IH
V
IL
IL
t
OH
t
OD
t
OD
V
OH
V
OL
V
V
IH
V
IH
V
IL
IL
032697 8/12
CE
WE
DQ0–DQ7
V
IL
t
WP
V
IH
t
ODW
V
IL
t
WR
V
IH
t
OEW
HIGH IMPEDANCE
t
t
DS
V
IH
DATA IN
V
STABLE
IL
DH
V
IH
V
IL
MEMORY WRITE CYCLE 2 (NOTES 2 AND 8)
WE = V
IH
DS1248Y
t
WC
V
ADDRESSES
CE
IH
V
IL
t
AW
V
IH
WE
t
COE
DQ0–DQ7
RESET FOR PHANTOM CLOCK
RST
READ CYCLE TO PHANTOM CLOCK
V
V
IH
V
t
WP
V
IL
V
IL
t
ODW
t
RST
V
IL
V
IL
t
DS
V
IH
DATA IN
V
STABLE
IL
t
WR
V
IH
t
OEW
t
DH
V
IH
V
IL
IH
V
IL
IL
OE
CE
t
RC
t
t
CO
t
OE
t
OEE
t
COE
Q
OUTPUT DATA VALID
RR
t
ODO
t
OD
032697 9/12
DS1248Y
WRITE CYCLE TO PHANTOM CLOCK
= V
OE
IH
WE
t
CE
CW
t
DS
D
POWER–DOWN/POWER–UP CONDITION
V
CC
4.50V
t
WC
t
WP
DATA IN STABLE
t
WR
t
WR
t
DH
t
DH
CE
LEAKAGE CURRENT I
SUPPLIED FROM LITHIUM
CELL
032697 10/12
3.2V
t
F
t
PD
DATA RETENTION TIME
L
t
DR
t
t
R
REC
DS1248Y
NOTES:
1. WE is high for a read cycle.
= VIH or VIL. If OE = VIH during write cycle, the output buffers remain in a high impedance state.
2. OE
is specified as the logical AND of CE and WE. tWP is measured from the latter of CE or WE going low to the
3. t
WP
earlier of CE
, tDS are measured from the earlier of CE or WE going high.
4. t
DH
5. These parameters are sampled with a 50 pF load and are not 100% tested.
6. If the CE
buffers remain in a high impedance state during this period.
7. If the CE
in a high impedance state during this period.
8. If WE
remain in a high impedance state during this period.
9. The expected t
is a function of the latter occurring edge of WE or CE.
10.t
WR
and tDS are a function of the first occurring edge of WE or CE.
11. t
DH
12.RST
13.Real–Time Clock Modules can be successfully processed through conventional wave–soldering techniques as
long as temperature exposure to the lithium energy source contained within does not exceed +85°C. Post solder
cleaning with water washing techniques is acceptable, provided that ultrasonic vibration is not used.
or WE going high.
low transition occurs simultaneously with or later than the WE low transition in Write Cycle 1, the output
high transition occurs prior to or simultaneously with the WE high transition, the output buffers remain
is low or the WE low transition occurs prior to or simultaneously with the CE low transition, the output buffers
is defined as accumulative time in the absence of VCC with the clock oscillator running.
DR
(Pin1) has an internal pull–up resistor.
032697 11/12
DS1248Y
DS1248Y 1024K NV SRAM WITH PHANTOM CLOCK
MIN
32–PIN
MAX
PKG
DIM
A IN. 1.720 1.740
MM 43.69 44.20
B IN. 0.720 0.740
1
J
A
C
F
GKD
E
H
B
MM 18.29 18.80
C IN. 0.395 0.415
MM 10.03 10.54
D IN. 0.090 0.120
MM 2.29 3.05
E IN. 0.017 0.030
MM 0.43 0.76
F IN. 0.120 0.160
MM 3.05 4.06
G IN. 0.090 0.110
MM 2.29 2.79
H IN. 0.590 0.630
MM 14.99 16.00
J IN. 0.008 0.012
MM 0.20 0.30
K IN. 0.015 0.021
MM 0.38 0.53
032697 12/12
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