Rainbow Electronics DS1248Y User Manual

DS1248Y

1024K NV SRAM with Phantom Clock

FEATURES

• Real time clock keeps track of hundredths of seconds,

minutes, hours, days, date of the month, months, and years

• 128K x 8 NV SRAM directly replaces volatile static

RAM or EEPROM

• Embedded lithium energy cell maintains calendar op-

eration and retains RAM data

• Watch function is transparent to RAM operation

• Month and year determine the number of days in each

month; valid up to 2100

• Standard 28–pin JEDEC pinout

• Full 10% operating range

• Operating temperature range 0°C to 70°C

• Accuracy is better than ±1 minute/month @ 25°C

• Over 10 years of data retention in the absence of

power

• Available in 120, 150 and 200 ns access time

ORDERING INFORMATION

DS1248Y–XXX

–120 120 ns access –150 150 ns access –200 200 ns access

PIN ASSIGNMENT

RST

A16

A14

A12

DQ0

DQ1

DQ2

GND

32–PIN ENCAPSULATED PACKAGE

740 MIL FLUSH

32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17

PIN DESCRIPTION

Ao–A

CE – Chip Enable GND – Ground DQ0–DQ V

WE – Write Enable OE – Output Enable NC – No Connect RST

– Address Inputs

– Data In/Data Out

– Power (+5V)

– Reset

A15 NC WE A13 A8 A9 A11 OE A10 CE DQ7 DQ6 DQ5 DQ4 DQ3

DESCRIPTION

The DS1248Y 1024K NV SRAM with Phantom Clock is a fully static nonvolatile RAM (organized as 128K words by 8 bits) with a built–in real time clock. The DS1248Y has a self–contained lithium energy source and control circuitry which constantly monitors VCC for an out–of– tolerance condition. When such a condition occurs, the lithium energy source is automatically switched on and write protection is unconditionally enabled to prevent garbled data in both the memory and real time clock.

Copyright 1997 by Dallas Semiconductor Corporation. All Rights Reserved. For important information regarding patents and other intellectual property rights, please refer to Dallas Semiconductor data books.

The Phantom Clock provides timekeeping information including hundredths of seconds, seconds, minutes, hours, day, date, month, and year information. The date at the end of the month is automatically adjusted for months with less than 31 days, including correction for leap years. The Phantom Clock operates in either 24–hour or 12–hour format with an AM/PM indicator.

032697 1/12

DS1248Y

RAM READ MODE

The DS1248Y executes a read cycle whenever WE (Write Enable) is inactive (high) and CE (Chip Enable) is active (low). The unique address specified by the 17 address inputs (A0–A16) defines which of the 128K bytes of data is to be accessed. Valid data will be available to the eight data output drivers within t

(Access Time)

ACC

after the last address input signal is stable, providing that CE and OE (Output Enable) access times and states are also satisfied. If OE and CE access times are not satisfied, then data access must be measured from the later occurring signal (CE

or OE) and the limiting parameter is either tCO for CE or tOE for OE rather than address access.

RAM WRITE MODE

The DS1248Y is in the write mode whenever the WE and CE signals are in the active (low) state after address inputs are stable. The latter occurring falling edge of CE or WE will determine the start of the write cycle. The write cycle is terminated by the earlier rising edge of CE or WE. All address inputs must be kept valid throughout the write cycle. WE must return to the high state for a minimum recovery time (tWR) before another cycle can be initiated. The OE

control signal should be kept inactive (high) during write cycles to avoid bus contention. However, if the output bus has been enabled (CE and OE active) then WE will disable the outputs in t

ODW

from

its falling edge.

DATA RETENTION MODE

The DS1248Y provides full functional capability for V greater than 4.5 volts and write protects by approximately 4.0 volts. Data is maintained in the absence of

without any additional support circuitry. The non-

volatile static RAM constantly monitors V

. Should the

supply voltage decay, the RAM automatically write protects itself. All inputs to the RAM become “don’t care” and all outputs are high impedance. As V

approximately 3.0 volts, the power switching circuit connects the lithium energy source to RAM to retain data. During power–up, when V

rises above approximately

3.0 volts, the power switching circuit connects external VCC to the RAM and disconnects the lithium energy source. Normal RAM operation can resume after V exceeds 4.5 volts.

falls below

PHANTOM CLOCK OPERATION

Communication with the Phantom Clock is established by pattern recognition on a serial bit stream of 64 bits which must be matched by executing 64 consecutive write cycles containing the proper data on DQ0. All accesses which occur prior to recognition of the 64–bit pattern are directed to memory.

After recognition is established, the next 64 read or write cycles either extract or update data in the Phantom Clock, and memory access is inhibited.

Data transfer to and from the timekeeping function is accomplished with a serial bit stream under control of Chip Enable (CE (WE ing the CE and OE control of the Phantom Clock starts the pattern recognition sequence by moving a pointer to the first bit of the 64–bit comparison register. Next, 64 consecutive write cycles are executed using the CE and WE are used only to gain access to the Phantom Clock. Therefore, any address to the memory in the socket is acceptable. However, the write cycles generated to gain access to the Phantom Clock are also writing data to a location in the mated RAM. The preferred way to manage this requirement is to set aside just one address location in RAM as a Phantom Clock scratch pad. When the first write cycle is executed, it is compared to bit 0 of the 64–bit comparison register. If a match is found, the pointer increments to the next location of the comparison register and awaits the next write cycle. If a match is not found, the pointer does not advance and all subsequent write cycles are ignored. If a read cycle occurs at any time during pattern recognition, the present sequence is aborted and the comparison register pointer is reset. Pattern recognition continues for a total of 64 write cycles as described above until all the bits in the comparison register have been matched (this bit pattern is shown in Figure 1). With a correct match for 64 bits, the Phantom Clock is enabled and data transfer to or from the timekeeping registers can proceed. The next 64 cycles will cause the Phantom Clock to either receive or transmit data on DQ0, depending on the level of the

pin or the WE pin. Cycles to other locations outside

OE the memory block can be interleaved with CE without interrupting the pattern recognition sequence or data transfer sequence to the Phantom Clock.

), Output Enable (OE), and Write Enable

). Initially, a read cycle to any memory location us-

control of the SmartWatch. These 64 write cycles

cycles

032697 2/12

DS1248Y

PHANTOM CLOCK REGISTER INFORMATION

in a register could produce erroneous results. These

read/write registers are defined in Figure 2. The Phantom Clock information is contained in 8 registers of 8 bits, each of which is sequentially accessed one bit at a time after the 64–bit pattern recognition sequence has been completed. When updating the Phantom Clock registers, each register must be handled in groups of 8 bits. Writing and reading individual bits with-

Data contained in the Phantom Clock register is in

binary coded decimal format (BCD). Reading and writ-

ing the registers is always accomplished by stepping

through all 8 registers, starting with bit 0 of register 0 and

ending with bit 7 of register 7.

PHANTOM CLOCK REGISTER DEFINITION Figure 1

76543210

BYTE 0

BYTE 1

BYTE 2

BYTE 3

11000101

00111010

10100011

01011100

HEX

VALUE

BYTE 4

BYTE 5

BYTE 6

BYTE 7

11000101

00111010

10100011

01011100

NOTE:

The pattern recognition in Hex is C5, 3A, A3, 5C, C5, 3A, A3, 5C. The odds of this pattern being accidentally duplicated and causing inadvertent entry to the Phantom Clock is less than 1 in 10 Clock LSB to MSB.

. This pattern is sent to the Phantom

032697 3/12

DS1248Y

PHANTOM CLOCK REGISTER DEFINITION Figure 2

76543210

0.1 SEC

0.01 SEC

RANGE

(BCD)

00–99

12/24 0

00 0

000

10 SEC SECONDS

10 MIN MINUTES

OSC

10 YEAR YEAR

A/P

RST

10 DATE DATE

MONTH

AM–PM/12/24 MODE

Bit 7 of the hours register is defined as the 12– or 24–hour mode select bit. When high, the 12–hour mode is selected. In the 12–hour mode, bit 5 is the AM/PM bit with logic high being PM. In the 24–hour mode, bit 5 is the second 10–hour bit (20–23 hours).

00–59

HOUR

DAY

MONTH

to logic 0, a low input on the RESET

01–12 00–23

01–07

01–31

01–12

00–99

pin will cause the Phantom Clock to abort data transfer without changing data in the watch registers. Bit 5 controls the oscillator . When set to logic 1, the oscillator is off. When set to logic 0, the oscillator turns on and the watch becomes operational. These bits are shipped from the factory set to a logic 1.

OSCILLATOR AND RESET BITS

Bits 4 and 5 of the day register are used to control the RESET and oscillator functions. Bit 4 controls the

(pin 1). When the RESET bit is set to logic 1, the

RESET RESET input pin is ignored. When the RESET bit is set

032697 4/12

ZERO BITS

Registers 1, 2, 3, 4, 5, and 6 contain one or more bits which will always read logic 0. When writing these locations, either a logic 1 or 0 is acceptable.

+ 8 hidden pages