Page 1
DS1220Y
DS1220Y
16K Nonvolatile SRAM
FEATURES
• 10 years minimum data retention in the absence of
external power
• Data is automatically protected during power loss
• Directly replaces 2K x 8 volatile static RAM or
EEPROM
• Unlimited write cycles
• Low-power CMOS
• JEDEC standard 24–pin DIP package
• Read and write access times as fast as 100 ns
• Full + 10% operating range
• Optional industrial temperature range of -40°C to
+85°C, designated IND
PIN ASSIGNMENT
1
A7
2
A6
3
A5
4
A4
5
A3
6
A2
7
A1
8
A0
9
DQ0
10
DQ1
11
DQ2
12 13
GND
24–PIN ENCAPSULATED PACKAGE
720 MIL EXTENDED
PIN DESCRIPTION
A0-A
10
DQ0-DQ
CE
WE
OE
V
CC
GND – Ground
– Address Inputs
– Data In/Data Out
7
– Chip Enable
– Write Enable
– Output Enable
– Power (+5V)
2324A8
22
21
20
19
18
17
16
15
DQ5
14
V
CC
A9
WE
OE
A10
CE
DQ7
DQ6
DQ4
DQ3
DESCRIPTION
The DS1220Y 16K Nonvolatile SRAM is a 16,384-bit,
fully static, nonvolatile RAM organized as 2048 words
by 8 bits. Each NV SRAM has a self-contained lithium
energy source and control circuitry which constantly
monitors VCC for an out-of-tolerance condition. When
such a condition occurs, the lithium energy source is
automatically switched on and write protection is unconditionally enabled to prevent data corruption. The NV
SRAM can be used in place of existing 2K x 8 SRAMs
Copyright 1995 by Dallas Semiconductor Corporation.
All Rights Reserved. For important information regarding
patents and other intellectual property rights, please refer to
Dallas Semiconductor data books.
directly conforming to the popular bytewide 24-pin DIP
standard. The DS1220Y also matches the pinout of the
2716 EPROM or the 2816 EEPROM, allowing direct
substitution while enhancing performance. There is no
limit on the number of write cycles that can be executed
and no additional support circuitry is required for microprocessor interfacing.
091295 1/8
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DS1220Y
READ MODE
The DS1220Y executes a read cycle whenever WE
(Write Enable) is inactive (high) and CE (Chip Enable)
and OE (Output Enable) are active (low). The unique
address specified by the 11 address inputs (A
0-A10
defines which of the 2048 bytes of data is to be
accessed. Valid data will be available to the eight data
output drivers within t
(Access Time) after the last
ACC
address input signal is stable, providing that CE and OE
access times are also satisfied. If OE and CE access
times are not satisfied, then data access must be
measured from the later occurring signal (CE
or OE)
and the limiting parameter is either tCO for CE or tOE for
rather than address access.
OE
WRITE MODE
The DS1220Y executes a write cycle whenever the WE
and CE signals are active (low) after address inputs are
stable. The latter occurring falling edge of CE or WE will
determine the start of the write cycle. The write cycle is
terminated by the earlier rising edge of CE
address inputs must be kept valid throughout the write
cycle. WE must return to the high state for a minimum
or WE. All
recovery time (t
ated. The OE
) before another cycle can be initi-
WR
control signal should be kept inactive
(high) during write cycles to avoid bus contention. However, if the output drivers are enabled (CE and OE ac-
)
tive) then WE will disable the outputs in t
falling edge.
DATA RETENTION MODE
The DS1220Y provides full functional capability for V
greater than 4.5 volts and write protects at 4.25 nominal.
Data is maintained in the absence of V
additional support circuitry. The DS1220Y constantly
monitors VCC. Should the supply voltage decay, the NV
SRAM automatically write protects itself, all inputs become “don’t care,” and all outputs become high impedance. As VCC falls below approximately 3.0 volts, a
power switching circuit connects the lithium energy
source to RAM to retain data. During power-up, when
rises above approximately 3.0 volts, the power
V
CC
switching circuit connects external VCC to RAM and disconnects the lithium energy source. Normal RAM operation can resume after V
exceeds 4.5 volts.
CC
CC
from its
ODW
without any
CC
091295 2/8
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DS1220Y
ABSOLUTE MAXIMUM RATINGS*
Voltage on Any Pin Relative to Ground -0.3V to +7.0V
Operating Temperature 0°C to 70°C; -40°C to +85°C for IND parts
Storage Temperature -40°C to +70°C; -40°C to +85°C for IND parts
Soldering Temperature 260°C for 10 seconds
* This is a stress rating only and functional operation of the device at these or any other conditions above those
indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods of time may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS (0°C to 70°C)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Power Supply Voltage V
Input Logic 1 V
Input Logic 0 V
CC
IH
IL
4.5 5.0 5.5 V
2.2 V
CC
0.0 +0.8 V
V
DC ELECTRICAL CHARACTERISTICS (0°C to 70°C; VCC = 5V ± 10%)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Input Leakage Current I
I/O Leakage Current
> VIH < V
CE
CC
Output Current @ 2.4V I
Output Current @ 0.4V I
Standby Current CE = 2.2V I
Standby Current CE = VCC-0.5V I
Operating Current t
(Commercial)
Operating Current t
(Industrial)
CYC
CYC
=200ns
=200ns
I
I
Write Protection Voltage V
IL
I
IO
OH
OL
CCS1
CCS2
CCO1
CCO1
TP
-1.0 +1.0 µA
-1.0 +1.0 µA
-1.0 mA
2.0 mA
3.0 7.0 mA
2.0 4.0 mA
75 mA
85 mA
4.25 V
CAPACITANCE (tA = 25°C)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Input Capacitance C
Input/Output Capacitance C
IN
I/O
5 10 pF
5 12 pF
091295 3/8
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DS1220Y
AC ELECTRICAL CHARACTERISTICS (0°C to 70°C; VCC=5.0V ± 10%)
DS1220Y-100 DS1220Y-120 DS1220Y-150 DS1220Y-200
PARAMETER SYM
Read Cycle Time t
Access Time t
OE to Output
Valid
CE to Output
Valid
OE or CE to
Output Active
Output High Z
from Deselection
Output Hold from
Address Change
Write Cycle Time t
Write Pulse Width t
Address Setup
Time
Write Recovery
Time
Output High Z
from WE
Output Active
from WE
Data Setup Time t
Data Hold Time t
t
t
MIN MAX MIN MAX MIN MAX MIN MAX
100 120 150 200 ns
RC
ACC
t
OE
t
CO
t
COE
t
OD
t
OH
WC
WP
t
AW
t
WR1
t
WR2
ODW
OEW
DS
DH1
t
DH2
100 120 150 200 ns
50 60 70 100 ns
100 120 150 200 ns
5 5 5 5 ns 5
35 35 35 35 ns 5
5 5 5 5 ns
100 120 150 200 ns
75 90 100 150 ns 3
0 0 0 0 ns
0
10
10
0
10
0
10
35 35 35 35 ns 5
5 5 5 5 ns 5
40 50 60 80 ns 4
0
10
10
0
10
0
10
UNITS NOTE
0
0
ns
ns
ns
ns
11
12
11
12
091295 4/8
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READ CYCLE
DS1220Y
t
RC
SEE NOTE 1
WRITE CYCLE 1
SEE NOTES 2, 3, 4, 6, 7 AND 8
ADDRESSES
CE
OE
D
OUT
ADDRESSES
CE
WE
D
OUT
D
IN
V
IH
V
IL
t
ACC
V
IH
V
V
t
AW
V
IH
t
CO
V
IL
V
IH
t
OE
V
IL
t
COE
t
COE
IH
IL
t
ODW
V
OH
V
OL
t
WC
V
IL
t
WP
V
IL
HIGH
INPEDANCE
V
IH
V
IL
V
OUTPUT
DATA VALID
V
IL
V
IL
t
DS
DATA IN
STABLE
V
V
V
IH
IH
t
V
t
OEW
t
DH1
IH
IL
V
V
WR1
IH
V
IH
V
IL
t
OH
t
OD
t
OD
V
OH
V
OL
V
IH
IL
IH
V
IL
V
IH
V
IL
WRITE CYCLE 2
SEE NOTES 2, 3, 4, 6, 7 AND 8
ADDRESSES
CE
WE
D
OUT
D
IN
t
COE
t
WC
V
IH
V
IL
t
AW
V
IH
V
IL
t
WP
VILV
VILV
t
ODW
t
V
IH
V
IL
V
V
t
WR2
IL
V
IH
IL
DStDH2
DATA IN
STABLE
V
IH
IL
V
IH
V
IL
IH
V
IH
V
IL
091295 5/8
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DS1220Y
POWER-DOWN/POWER-UP CONDITION
V
CC
V
TP
3.2V
t
F
t
PD
WE, CE
t
REC
t
R
LEAKAGE CURRENT
SUPPLIED FROM
I
L
LITHIUM CELL
DATA RETENTION TIME
t
DR
POWER-DOWN/POWER-UP TIMING
PARAMETER SYMBOL MIN MAX UNITS NOTES
CE at VIH before Power-Down t
VCC Slew from VTP to 0V (CE at VIH) t
VCC Slew from 0V to V
(CE at VIH) t
TP
CE at VIH after Power-Up t
PD
F
R
REC
0 µs 10
100 µs
0 µs
2 ms
(tA = 25°C)
PARAMETER SYMBOL MIN MAX UNITS NOTES
Expected Data Retention Time t
DR
10 years 9
WARNING:
Under no circumstance are negative undershoots, of any amplitude, allowed when device is in battery backup mode.
NOTES:
1. WE is high for a read cycle.
= VIH or VIL. If OE = VIH during a write cycle, the output buffers remain in a high impedance state.
2. OE
is specified as the logical AND of CE and WE. tWP is measured from the latter of CE or WE going low to
3. t
WP
the earlier of CE or WE going high.
are measured from the earlier of CE or WE going high.
4. t
DS
5. These parameters are sampled with a 5 pF load and are not 100% tested.
6. If the CE
output buffers remain in a high impedance state during this period.
low transition occurs simultaneously with or later than the WE low transition in write cycle 1, the
091295 6/8
Page 7
DS1220Y
7. If the CE high transition occurs prior to or simultaneously with the WE high transition, the output buffers remain in a high impedance state during this period.
8. If WE
is low or the WE low transition occurs prior to or simultaneously with the CE low transition, the output
buffers remain in a high impedance state during this period.
9. Each DS1220Y is marked with a 4-digit date code AABB. AA designates the year of manufacture. BB designates the week of manufacture. The expected t
10.In a power down condition the voltage on any pin may not exceed the voltage of V
, t
11. t
12.t
WR1
WR2
are measured from WE going high.
DH1
, t
are measured from CE going high.
DH2
is defined as starting at the date of manufacture.
DR
.
CC
13.DS1220Y modules are recongnized by Underwriters Laboratory (U.L.) under file E99151 (R).
DC TEST CONDITIONS
Outputs open.
All voltages are referenced to ground.
ORDERING INFORMATION
DS1220 TTP–
SSS –
III
Operating Temperature Range
Blank: 0° to 70°
IND: –40° to +85°C
Speed
Access
100 ns
100:
120 ns
120:
150 ns
150:
200 ns
200:
Package Type
Blank: 24–pin 600 mil DIP
V
T olerance
CC
Y: 10%
AC TEST CONDITIONS
Output Load: 100pF + 1TTL Gate
Input Pulse Levels: 0-3.0V
Timing Measurement Reference Levels
Input:1.5V
Output: 1.5V
Input Pulse Rise and Fall Times: 5ns
091295 7/8
Page 8
DS1220Y
DS1220Y NONVOLATILE SRAM, 24-PIN 720 MIL EXTENDED MODULE
24
114
11 EQUAL SPACES AT
A
KD G
.100 ± .010 TNA
15
DIM MIN MAX
IN.
A
MM
IN.
B
MM
C IN.
MM
IN.
D
MM
E IN.
MM
F IN.
E
C
F
MM
G IN.
MM
H
MM
J IN.
MM
K
MM
IN.
IN.
1.320
33.53
0.695
17.65
0.390
9.91
0.100
2.54
0.017
0.43
0.120
3.05
0.090
2.29
0.590
14.99
0.008
0.20
0.015
0.38
24–PINPKG
1.340
34.04
0.720
18.29
0.415
10.54
0.130
3.30
0.030
0.76
0.160
4.06
0.110
2.79
0.630
16.00
0.012
0.30
0.021
0.53
091295 8/8
J
H
B
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