Rainbow Electronics DS1215 User Manual

DS1215

Phantom Time Chip

FEATURES

• Keeps track of hundredths of seconds, seconds, min-

utes, hours, days, date of the month, months, and years

• Adjusts for months with fewer than 31 days

• Leap year automatically corrected up to 2100

• No address space required

• Provides nonvolatile controller functions for battery

backup of RAM

• Supports redundant batteries for high–reliability

applications

• Uses a 32.768 KHz watch crystal

• Full ±10% operating range

• Operating temperature range 0°C to 70°C

• Space-saving, 16–pin DIP package and SOIC

• Optional industrial temperature range –40°C to +85°C

(IND)

DESCRIPTION

The DS1215 Phantom Time Chip is a combination of a CMOS timekeeper and a nonvolatile memory controller. In the absence of power, an external battery maintains the timekeeping operation and provides power for a CMOS static RAM. The watch keeps track of hundredths of seconds, seconds, minutes, hours, day, date, month, and year information. The last day of the month is automatically adjusted for months with less than 31 days, including correction for leap year every four years. The watch operates in one of two formats: a 12–hour mode with an AM/PM indicator or a 24–hour mode. The nonvolatile controller supplies all the necessary support circuitry to convert a CMOS RAM to a nonvolatile memory. The DS1215 can be interfaced with either RAM or ROM without leaving gaps in memory.

PIN ASSIGNMENT

X1 X2

BAT1

GND

D Q

GND

16–PIN DIP (300 MIL)

BAT1

GND

4 5 6

16–PIN SOIC (300 MIL)

V 2 3 4 5 6 7 8

CCI

CCO

BAT2

RST

CEI

11 10

CEO

ROM/RAM

V 15 14 13 12 11 10

CCI

CCO

BAT2

RST

CEI

CEO

ROM/RAM

PIN DESCRIPTION

X1, X2 – 32.768 KHz Crystal Connections WE – Write Enable BAT1 – Battery 1 Input GND – Ground D – Data In Q – Data Out ROM/RAM CEO

– ROM/RAM Select

– Chip Enable Out CEI – Chip Enable Input OE – Output Enable RST – Reset BAT2 – Battery 2 Input V V

CCO CCI

– Switched Supply Output

– +5 VDC Input NOTE: Both pins 5 and 8 must be grounded.

ORDERING INFORMATION

DS1215 16–pin DIP DS1215S 16–pin SOIC DS1215N 16–pin DIP (IND) DS1215SN 16–pin SOIC (IND)

Copyright 1997 by Dallas Semiconductor Corporation. All Rights Reserved. For important information regarding patents and other intellectual property rights, please refer to Dallas Semiconductor data books.

032697 1/15

DS1215

OPERATION

The block diagram of Figure 1 illustrates the main elements of the Time Chip. Communication with the Time Chip is established by pattern recognition of a serial bit stream of 64 bits which must be matched by executing 64 consecutive write cycles containing the proper data on data in (D). All accesses which occur prior to recognition of the 64-bit pattern are directed to memory via the chip enable output pin (CEO

After recognition is established, the next 64 read or write cycles either extract or update data in the Time Chip and

TIMING BLOCK DIAGRAM Figure 1

32.768 kHz

ROM/RAM

CEO

CEI

RST

CONTROL

LOGIC

POWER-FAIL

READ

WRITE

CEO

remains high during this time, disabling the con-

nected memory.

Data transfer to and from the timekeeping function is accomplished with a serial bit stream under control of chip enable input (CEI

), output enable (OE), and write enable (WE). Initially , a read cycle using the CEI and OE control of the Time Chip starts the pattern recognition sequence by moving a pointer to the first bit of the 64 bit comparison register. Next, 64 consecutive write cycles are executed using the CEI and WE control of the Time Chip. These 64 write cycles are used only to gain access to the Time Chip.

CLOCK/CALENDAR LOGIC

UPDATE

TIMEKEEPING REGISTER

032697 2/15

ACCESS

ENABLE SEQUENCE DETECTOR

I/O BUFFERS

CCI

DATA

POWER–FAIL

DETECT

LOGIC

BAT

INTERNAL V

BAT

COMPARISON REGISTER

CCO

DS1215

When the first write cycle is executed, it is compared to bit 1 of the 64–bit comparison register. If a match is found, the pointer increments to the next location of the comparison register and awaits the next write cycle. If a match is not found, the pointer does not advance and all subsequent write cycles are ignored. If a read cycle oc-

64 cycles will cause the Time Chip to either receive data on D, or transmit data on Q, depending on the level of OE pin or the WE pin. Cycles to other locations outside the memory block can be interleaved with CEI without interrupting the pattern recognition sequence or

data transfer sequence to the Time Chip. curs at any time during pattern recognition, the present sequence is aborted and the comparison register pointer is reset. Pattern recognition continues for a total of 64 write cycles as described above until all the bits in the comparison register have been matched. (This bit pattern is shown in Figure 2.) With a correct match for 64 bits, the Time Chip is enabled and data transfer to or from the timekeeping registers may proceed. The next

A 32,768 Hz quartz crystal can be directly connected to

the DS1215 via pins 1 and 2 (X1, X2). The crystal se-

lected for use should have a specified load capacitance

) of 6 pF. For more information on crystal selection

and crystal layout considerations, please consult

Application Note 58, “Crystal Considerations with Dal-

las Real Time Clocks”.

TIME CHIP COMPARISON REGISTER DEFINITION Figure 2

76543210

BYTE 0

BYTE 1

BYTE 2

11000101

00111010

10100011

HEX

VALUE

cycles

BYTE 3

BYTE 4

BYTE 5

BYTE 6

BYTE 7

01011100

11000101

00111010

10100011

01011100

NOTE:

The pattern recognition in Hex is C5, 3A, A3, 5C, C5, 3A, A3, 5C. The odds of this pattern being accidentally duplicated and causing inadvertent entry to the Time Chip are less than 1 in 10

032697 3/15

DS1215

NONVOLATILE CONTROLLER OPERATION

The operation of the nonvolatile controller circuits within the Time Chip is determined by the level of the ROM/RAM select pin. When ROM/RAM is connected to ground, the controller is set in the RAM mode and performs the circuit functions required to make static CMOS RAM and the timekeeping function nonvolatile. A switch is provided to direct power from the battery inputs or V

CCI

to V

0.3 volts. The V rupted power to CMOS SRAM. The DS1215 also performs redundant battery control for high reliability. On power–fail, the battery with the highest voltage is automatically switched to V the system, the unused battery input should be connected to ground.

The DS1215 safeguards the Time Chip and RAM data by power–fail detection and write protection. Power–fail detection occurs when V equal to 1.26 x V

supply pin. When V

the V

CCI

parator outputs a power–fail signal to the control logic. The power–fail signal forces the chip enable output (CEO) to V

CCI

protection. During nominal supply conditions, CEO will track CEI

with a maximum propagation delay of 20 ns. Internally , the DS1215 aborts any data transfer in progress without changing any of the Time Chip registers and prevents future access until V typical RAM/Time Chip interface is illustrated in Figure 3.

When the ROM/RAM troller is set in the ROM mode. Since ROM is a read– only device that retains data in the absence of power, battery backup and write protection is not required. As a result, the chip enable logic will force CEO power fails. However, the Time Chip does retain the same internal nonvolatility and write protection as described in the RAM mode. In addition, the chip enable output is set at a low level on power–fail as V low the level of V is illustrated in Figure 4.

with a maximum voltage drop of

CCO

output pin is used to supply uninter-

CCO

. If only one battery is used in

CCO

falls below VTP, which is

CCI

. The DS1215 constantly monitors

BAT

or V

BAT

pin is connected to V

. A typical ROM/Time Chip interface

BAT

is less than VTP , a com-

CCI

–0.2 volts for external RAM write

exceeds VTP. A

CCI

CCO

, the con-

low when

falls be-

CCI

TIME CHIP REGISTER INFORMATION

Time Chip information is contained in 8 registers of 8 bits, each of which is sequentially accessed one bit at a time after the 64–bit pattern recognition sequence has been completed. When updating the Time Chip registers, each must be handled in groups of 8 bits. Writing and reading individual bits within a register could produce erroneous results. These read/write registers are defined in Figure 5.

Data contained in the Time Chip registers is in binary coded decimal format (BCD). Reading and writing the registers is always accomplished by stepping though all 8 registers, starting with bit 0 of register 0 and ending with bit 7 of register 7.

AM–PM/12/24 MODE

Bit 7 of the hours register is defined as the 12– or 24–hour mode select bit. When high, the 12–hour mode is selected. In the 12–hour mode, bit 5 is the AM/PM bit with logic high being PM. In the 24–hour mode, bit 5 is the second 10–hour bit (20 –23 hours).

OSCILLATOR AND RESET BITS

Bits 4 and 5 of the day register are used to control the reset and oscillator functions. Bit 4 controls the reset pin (Pin 13). When the reset bit is set to logic 1, the reset input pin is ignored. When the reset bit is set to logic 0, a low input on the reset pin will cause the Time Chip to abort data transfer without changing data in the timekeeping registers. Reset operates independently of all other inputs. Bit 5 controls the oscillator. When set to logic 0, the oscillator turns on and the watch becomes operational.

ZERO BITS

Registers 1, 2, 3, 4, 5, and 6 contain one or more bits that will always read logic 0. When writing these locations, either a logic 1 or 0 is acceptable.

032697 4/15

RAM/TIME CHIP INTERFACE Figure 3

A0 – AN

10 12

RST

BAT

414

CMOS STATIC RAM

ADD

DATA I/O

DS1215

CEO

CCO

OE WE

CEI RST

BAT

CCI

ROM/

RAM

BAT

32.768 KHz

DS1215

D0 – D7

15 6 7

+5 VDC

OR TIE TO GND FOR ONE–BATTERY

BAT

OPERATION

ROM/TIME CHIP INTERFACE Figure 4

A0 – AN

RST

BAT

11 13

414

ROM

ADD

DATA I/O

DS1215

CEO OE WE

CEI RST

BAT

CCI

CCO

ROM/

RAM

BAT

32.768 KHz

D0 – D7

10 7 16

+5 VDC 15 9

OR TIE TO GND FOR ONE–BATTERY

BAT

OPERATION

032697 5/15

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