DS1215
DS1215
Phantom Time Chip
FEATURES
• Keeps track of hundredths of seconds, seconds, min-
utes, hours, days, date of the month, months, and
years
• Adjusts for months with fewer than 31 days
• Leap year automatically corrected up to 2100
• No address space required
• Provides nonvolatile controller functions for battery
backup of RAM
• Supports redundant batteries for high–reliability
applications
• Uses a 32.768 KHz watch crystal
• Full ±10% operating range
• Operating temperature range 0°C to 70°C
• Space-saving, 16–pin DIP package and SOIC
• Optional industrial temperature range –40°C to +85°C
(IND)
DESCRIPTION
The DS1215 Phantom Time Chip is a combination of a
CMOS timekeeper and a nonvolatile memory controller.
In the absence of power, an external battery maintains
the timekeeping operation and provides power for a
CMOS static RAM. The watch keeps track of hundredths of seconds, seconds, minutes, hours, day, date,
month, and year information. The last day of the month
is automatically adjusted for months with less than 31
days, including correction for leap year every four years.
The watch operates in one of two formats: a 12–hour
mode with an AM/PM indicator or a 24–hour mode. The
nonvolatile controller supplies all the necessary support
circuitry to convert a CMOS RAM to a nonvolatile
memory. The DS1215 can be interfaced with either
RAM or ROM without leaving gaps in memory.
PIN ASSIGNMENT
1
X1
X2
WE
BAT1
GND
D
Q
GND
16–PIN DIP (300 MIL)
X1
1
X2
2
WE
3
BAT1
GND
GND
4
5
6
D
7
Q
8
16–PIN SOIC (300 MIL)
16
V
2
3
4
5
6
7
8
CCI
15
V
CCO
14
BAT2
13
RST
12
OE
CEI
11
10
CEO
9
ROM/RAM
16
V
15
14
13
12
11
10
CCI
V
CCO
BAT2
RST
OE
CEI
CEO
9
ROM/RAM
PIN DESCRIPTION
X1, X2 – 32.768 KHz Crystal Connections
WE – Write Enable
BAT1 – Battery 1 Input
GND – Ground
D – Data In
Q – Data Out
ROM/RAM
CEO
– ROM/RAM Select
– Chip Enable Out
CEI – Chip Enable Input
OE – Output Enable
RST – Reset
BAT2 – Battery 2 Input
V
V
CCO
CCI
– Switched Supply Output
– +5 VDC Input
NOTE: Both pins 5 and 8 must be grounded.
ORDERING INFORMATION
DS1215 16–pin DIP
DS1215S 16–pin SOIC
DS1215N 16–pin DIP (IND)
DS1215SN 16–pin SOIC (IND)
Copyright 1997 by Dallas Semiconductor Corporation.
All Rights Reserved. For important information regarding
patents and other intellectual property rights, please refer to
Dallas Semiconductor data books.
032697 1/15
DS1215
OPERATION
The block diagram of Figure 1 illustrates the main elements of the Time Chip. Communication with the Time
Chip is established by pattern recognition of a serial bit
stream of 64 bits which must be matched by executing
64 consecutive write cycles containing the proper data
on data in (D). All accesses which occur prior to recognition of the 64-bit pattern are directed to memory via the
chip enable output pin (CEO
).
After recognition is established, the next 64 read or write
cycles either extract or update data in the Time Chip and
TIMING BLOCK DIAGRAM Figure 1
X
1
32.768 kHz
ROM/RAM
CEO
CEI
OE
WE
RST
CONTROL
LOGIC
POWER-FAIL
READ
WRITE
X
2
CEO
remains high during this time, disabling the con-
nected memory.
Data transfer to and from the timekeeping function is accomplished with a serial bit stream under control of chip
enable input (CEI
), output enable (OE), and write enable (WE). Initially , a read cycle using the CEI and OE
control of the Time Chip starts the pattern recognition
sequence by moving a pointer to the first bit of the 64 bit
comparison register. Next, 64 consecutive write cycles
are executed using the CEI and WE control of the Time
Chip. These 64 write cycles are used only to gain access to the Time Chip.
CLOCK/CALENDAR LOGIC
UPDATE
TIMEKEEPING REGISTER
032697 2/15
ACCESS
ENABLE
SEQUENCE
DETECTOR
D
Q
I/O BUFFERS
V
CCI
DATA
POWER–FAIL
DETECT
LOGIC
BAT
1
INTERNAL V
BAT
2
CC
COMPARISON REGISTER
V
CCO
DS1215
When the first write cycle is executed, it is compared to
bit 1 of the 64–bit comparison register. If a match is
found, the pointer increments to the next location of the
comparison register and awaits the next write cycle. If a
match is not found, the pointer does not advance and all
subsequent write cycles are ignored. If a read cycle oc-
64 cycles will cause the Time Chip to either receive data
on D, or transmit data on Q, depending on the level of
OE pin or the WE pin. Cycles to other locations outside
the memory block can be interleaved with CEI
without interrupting the pattern recognition sequence or
data transfer sequence to the Time Chip.
curs at any time during pattern recognition, the present
sequence is aborted and the comparison register pointer is reset. Pattern recognition continues for a total of 64
write cycles as described above until all the bits in the
comparison register have been matched. (This bit pattern is shown in Figure 2.) With a correct match for 64
bits, the Time Chip is enabled and data transfer to or
from the timekeeping registers may proceed. The next
A 32,768 Hz quartz crystal can be directly connected to
the DS1215 via pins 1 and 2 (X1, X2). The crystal se-
lected for use should have a specified load capacitance
(C
) of 6 pF. For more information on crystal selection
L
and crystal layout considerations, please consult
Application Note 58, “Crystal Considerations with Dal-
las Real Time Clocks”.
TIME CHIP COMPARISON REGISTER DEFINITION Figure 2
76543210
BYTE 0
BYTE 1
BYTE 2
11000101
00111010
10100011
HEX
VALUE
C5
3A
A3
cycles
BYTE 3
BYTE 4
BYTE 5
BYTE 6
BYTE 7
01011100
11000101
00111010
10100011
01011100
5C
C5
3A
A3
5C
NOTE:
The pattern recognition in Hex is C5, 3A, A3, 5C, C5, 3A, A3, 5C. The odds of this pattern being accidentally duplicated
and causing inadvertent entry to the Time Chip are less than 1 in 10
19
.
032697 3/15
DS1215
NONVOLATILE CONTROLLER OPERATION
The operation of the nonvolatile controller circuits within
the Time Chip is determined by the level of the
ROM/RAM select pin. When ROM/RAM is connected to
ground, the controller is set in the RAM mode and performs the circuit functions required to make static
CMOS RAM and the timekeeping function nonvolatile.
A switch is provided to direct power from the battery inputs or V
CCI
to V
0.3 volts. The V
rupted power to CMOS SRAM. The DS1215 also performs redundant battery control for high reliability. On
power–fail, the battery with the highest voltage is automatically switched to V
the system, the unused battery input should be connected to ground.
The DS1215 safeguards the Time Chip and RAM data
by power–fail detection and write protection. Power–fail
detection occurs when V
equal to 1.26 x V
supply pin. When V
the V
CCI
parator outputs a power–fail signal to the control logic.
The power–fail signal forces the chip enable output
(CEO) to V
CCI
protection. During nominal supply conditions, CEO will
track CEI
with a maximum propagation delay of 20 ns.
Internally , the DS1215 aborts any data transfer in progress without changing any of the Time Chip registers
and prevents future access until V
typical RAM/Time Chip interface is illustrated in
Figure 3.
When the ROM/RAM
troller is set in the ROM mode. Since ROM is a read–
only device that retains data in the absence of power,
battery backup and write protection is not required. As a
result, the chip enable logic will force CEO
power fails. However, the Time Chip does retain the
same internal nonvolatility and write protection as described in the RAM mode. In addition, the chip enable
output is set at a low level on power–fail as V
low the level of V
is illustrated in Figure 4.
with a maximum voltage drop of
CCO
output pin is used to supply uninter-
CCO
. If only one battery is used in
CCO
falls below VTP, which is
CCI
. The DS1215 constantly monitors
BAT
or V
BAT
pin is connected to V
. A typical ROM/Time Chip interface
BAT
is less than VTP , a com-
CCI
–0.2 volts for external RAM write
exceeds VTP. A
CCI
CCO
, the con-
low when
falls be-
CCI
TIME CHIP REGISTER INFORMATION
Time Chip information is contained in 8 registers of
8 bits, each of which is sequentially accessed one bit at
a time after the 64–bit pattern recognition sequence has
been completed. When updating the Time Chip registers, each must be handled in groups of 8 bits. Writing
and reading individual bits within a register could produce erroneous results. These read/write registers are
defined in Figure 5.
Data contained in the Time Chip registers is in binary
coded decimal format (BCD). Reading and writing the
registers is always accomplished by stepping though all
8 registers, starting with bit 0 of register 0 and ending
with bit 7 of register 7.
AM–PM/12/24 MODE
Bit 7 of the hours register is defined as the 12– or
24–hour mode select bit. When high, the 12–hour mode
is selected. In the 12–hour mode, bit 5 is the AM/PM bit
with logic high being PM. In the 24–hour mode, bit 5 is
the second 10–hour bit (20 –23 hours).
OSCILLATOR AND RESET BITS
Bits 4 and 5 of the day register are used to control the
reset and oscillator functions. Bit 4 controls the reset pin
(Pin 13). When the reset bit is set to logic 1, the reset input pin is ignored. When the reset bit is set to logic 0, a
low input on the reset pin will cause the Time Chip to
abort data transfer without changing data in the timekeeping registers. Reset operates independently of all
other inputs. Bit 5 controls the oscillator. When set to
logic 0, the oscillator turns on and the watch becomes
operational.
ZERO BITS
Registers 1, 2, 3, 4, 5, and 6 contain one or more bits that
will always read logic 0. When writing these locations,
either a logic 1 or 0 is acceptable.
032697 4/15
RAM/TIME CHIP INTERFACE Figure 3
A0 – AN
10
12
3
CE
RST
BAT
11
13
414
1
CMOS STATIC RAM
ADD
DATA I/O
WE
OE
CE
V
CC
DS1215
CEO
V
CCO
OE
WE
CEI
RST
BAT
X
D
Q
V
CCI
ROM/
RAM
BAT
1
2
X
1
2
12
32.768 KHz
DS1215
D0 – D7
15
6
7
+5 VDC
9
OR TIE TO GND FOR
ONE–BATTERY
BAT
OPERATION
2
++
ROM/TIME CHIP INTERFACE Figure 4
A0 – AN
OE
6
12
3
CE
RST
BAT
11
13
414
1
ROM
ADD
V
CC
DATA I/O
A2
OE
A0
CE
DS1215
D
CEO
OE
WE
CEI
RST
BAT
X
Q
V
CCI
V
CCO
ROM/
RAM
BAT
1
2
X
1
2
12
32.768 KHz
D0 – D7
10
7
16
+5 VDC
15
9
OR TIE TO GND FOR
ONE–BATTERY
BAT
OPERATION
2
++
032697 5/15
DS1215
TIME CHIP REGISTER DEFINITION Figure 5
REGISTER
7654 3210
0
0.1 SEC
0.01 SEC
RANGE
(BCD)
00–99
1
2
3
4
5
6
7
0
0
12/24 0
00 0
00
0 0 0 10 MONTH
10 SEC SECONDS
10 MIN MINUTES
10
OSC RST
10 YEAR YEAR
HR
A/P
10 DATE DATE
MONTH
HOUR
DAY
00–59
00–59
01–12
00–23
01–07
01–31
01–12
00–99
032697 6/15
DS1215
ABSOLUTE MAXIMUM RATINGS*
Voltage on any Pin Relative to Ground –0.3V to +7.0V
Operating Temperature 0°C to 70°C
Storage Temperature –55°C to +125°C
Soldering Temperature 260°C for 10 seconds
* This is a stress rating only and functional operation of the device at these or any other conditions above those
indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods of time may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS (0°C to 70°C)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Supply Voltage V
Logic 1 V
Logic 0 V
V
BAT1
or V
Battery Voltage V
BAT2
CC
IH
IL
BAT
4.5 5.0 5.5 V 1
2.2 VCC+0.3 1
–0.3 +0.8 V 1
2.5 3.7 V 7
DC ELECTRICAL CHARACTERISTICS (0°C to 70°C; VCC = 4.5 to 5.5V)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Supply Current I
Supply Current V
CCO
= V
–0.3 I
CCI
Input Leakage I
Output Leakage I
Output @ 2.4V I
Output @ 0.4V I
CCI
CCO1
IL
LO
OH
OL
–1.0 +1.0 µA 11
–1.0 +1.0 µA
–1.0 mA 2
5 mA 6
80 mA 8
4.0 mA 2
DC ELECTRICAL CHARACTERISTICS (0°C to 70°C; VCC < 4.5V)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
CEO Output V
V
BAT1
or V
Battery Current I
BAT2
Battery Backup Current
= V
@ V
CCO
BAT
–0.2V
OH1
BAT
I
CCO2
V
or
CCI
–0.2
V
BAT
V 9
1 µA 6
10 µA 10
032697 7/15
DS1215
AC ELECTRICAL CHARACTERISTICS ROM/RAM = GND (0°C to 70°C; VCC = 4.5 to 5.5V)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Read Cycle Time t
CEI Access Time t
OE Access Time t
CEI to Output Low Z t
OE to Output Low Z t
CEI to Output High Z t
OE to Output High Z t
Read Recovery t
Write Cycle t
Write Pulse Width t
Write Recovery t
Data Setup t
Data Hold Time t
CEI Pulse Width t
RST Pulse Width t
CEI Propagation Delay t
CEI High to Power–Fail t
RC
CO
OE
COE
OEE
OD
ODO
RR
WC
WP
WR
DS
DH
CW
RST
PD
PF
120 ns
100 ns
100 ns
10 ns
10 ns
40 ns
40 ns
20 ns
120 ns
100 ns
20 ns 4
40 ns 5
10 ns 5
100 ns
200 ns
5 10 20 ns 2, 3
0 ns
AC ELECTRICAL CHARACTERISTICS ROM/RAM = GND (0°C to 70°C; VCC > 4.5V)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Recovery at Power–Up t
V
Slew Rate 4.5 – 3.0V t
CC
REC
F
0 ms
2 ms
CAPACITANCE (tA = 25°C)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Input Capacitance C
Output Capacitance C
032697 8/15
IN
OUT
5 10 pF
5 10 pF
DS1215
AC ELECTRICAL CHARACTERISTICS ROM/RAM = V
(0°C to 70°C; VCC = 5V ± 10%)
CCO
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Read Cycle Time t
CEI Access Time t
OE Access Time t
CEI to Output in Low Z t
OE to Output in Low Z t
CEI to Output in High Z t
OE to Output in High Z t
Address Setup Time t
Address Hold Time t
Read Recovery t
Write Cycle Time t
CEI Pulse Width t
OE Pulse Width t
Write Recovery t
Data Setup Time t
Data Hold Time t
RST Pulse Width t
CEI Propagation Delay t
CEI High to Power Fail t
RC
CO
OE
COE
OEE
OD
ODO
AS
AH
RR
WC
CW
OW
WR
DS
DH
RST
PD
PF
120 ns
100 ns
100 ns
10 ns
10 ns
40 ns
40 ns
20 ns
10 ns
20 ns
120 ns
100 ns
100 ns
20 ns 4
40 ns 5
10 ns 5
200 ns
5 10 20 ns 2, 3
0 ns
AC ELECTRICAL CHARACTERISTICS ROM/RAM = V
(0°C to 70°C; VCC < 4.5V)
CCO
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Recovery at Power–Up t
VCC Slew Rate 4.5 – 3.0V t
REC
F
2 ms
0 ms
032697 9/15
DS1215
TIMING DIAGRAM: READ CYCLE TO TIME CHIP ROM/RAM = GND
WE
= V
IH
t
CEI
OE
RC
t
CO
t
OE
t
OEE
t
COE
t
t
t
ODO
RR
OD
Q
OUTPUT DATA VALID
TIMING DIAGRAM: WRITE CYCLE TO TIME CHIP ROM/RAM = GND
OE
= V
IH
t
WE
WC
t
t
WP
WR
032697 10/15
CEI
D
t
CW
t
DS
DATA IN STABLE
t
WR
t
DH
t
DH
DS1215
TIMING DIAGRAM: READ CYCLE ROM/RAM = V
t
CO
CEI
t
COE
OE
t
OEE
OE
WE
t
t
AS
AS
t
Q
TIMING DIAGRAM: WRITE CYCLE ROM/RAM = V
t
CW
CEI
CCO
t
RC
t
RC
OUTPUT DATA VALID
CCO
t
WC
t
RR
t
OD
t
RR
t
ODO
t
AH
t
AH
t
WR
OE
WE
t
t
WC
t
OW
t
AS
t
AS
t
DS
t
DS
D
DATA IN STABLE
t
t
WR
t
AH
AH
t
DH
DH
032697 11/15
DS1215
TIMING DIAGRAM: POWER DOWN
ROM/RAM = GND
CEI
CEO
V
IH
V
IL
t
CE
t
PD
t
CE
V
V
IL
IH
t
PF
V
- 0.2V
BAT
ROM/RAM
= V
CCO
CEO
V
CCI
TIMING DIAGRAM: POWER UP
CEI
BAT - 0.2V
CCO
CEO
CEO
V
CCI
ROM/RAM = GND
= V
ROM/RAM
4.5V
4.5V
V
IH
V
IL
t
REC
t
F
3V
V
IL
t
PD
TIMING DIAGRAM: RESET FOR TIME CHIP
RST
032697 12/15
t
RST
NOTES:
1. All voltages are referenced to ground.
2. Measured with load shown in Figure 6.
3. Input pulse rise and fall times equal 10 ns.
is a function of the latter occurring edge of WE or CE in RAM mode, or OE or CE in ROM mode.
4. t
WR
5. t
DH
and t
are functions of the first occurring edge of WE or CE in RAM mode, or OE or CE in ROM mode.
DS
6. Measured without RAM connected.
7. Trip point voltage for power–fail detect. V
for 5% operation V
8. I
is the maximum average load current the DS1215 can supply to memory.
CC01
9. Applies to CEO
to a low level as V
10.I
is the maximum average load current that the DS1215 can supply to memory in the battery backup mode.
CC02
11.Applies to all input pins except RST
= 3.7V max.
BAT
with the ROM/RAM pin grounded. When the ROM/RAM pin is connected to V
falls below V
CCI
BAT
.
. RST is pulled internally to V
= 1.26 x V
TP
. For 10% VCC= 5V + 10% operation V
BAT
.
CCI
OUTPUT LOAD Figure 6
+5V
= 3.5V max.;
BAT
, CEO will go
CCO
DS1215
680Ω
1.1KΩ
50 pF
032697 13/15
DS1215
DS1215 TIME CHIP
B D
1
A
C
F
K
E
G
J
H
16–PINPKG
DIM MIN MAX
A IN. 0.740 0.780
MM
B IN. 0.240 0.260
MM
C IN. 0.120 0.140
MM
D IN. 0.300 0.325
MM
E IN. 0.015 0.040
MM
F IN. 0.110 0.140
MM
G IN. 0.090 0.110
MM
H IN. 0.300 0.370
MM
J IN. 0.008 0.012
MM
K IN. 0.015 0.021
MM
032697 14/15
DS1215S SERIAL TIMEKEEPER 16–PIN SOIC
GK
HB
1
A
C
DS1215
F
E
PKG
DIM MIN MAX
A IN.MM0.402
B IN.MM0.290
C IN.MM0.089
E IN.MM0.004
F IN.MM0.094
G IN.
MM
H INMM0.398
J INMM0.009
K IN.MM0.013
L INMM0.016
PHI 0° 8°
16–PIN
10.21
7.37
2.26
0.102
2.38
0.050 BSC
1.27 BSC
10.11
0.229
0.33
0.40
0.412
10.46
0.300
7.65
0.095
2.41
0.012
0.30
0.105
2.68
0.416
10.57
0.013
0.33
0.019
0.48
0.040
1.02
phi
J
L
032697 15/15
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