Rainbow Electronics DOC0395 User Manual

Features

•

Single 3.3V ± 10% Supply

•

Fast Read Access Time - 200 ns

•

Automatic Page Write Operation

– Internal Address and Data Latches for 128 Bytes
– Internal Control Timer

•

Fast Write Cycle Time

– Page Write Cycle Time - 10 ms Maximum
– 1 to 128-Byte Page Write Operation

•

Low Power Dissipation

– 15 mA Active Current
–20 µA CMOS Standby Current

•

Hardware and Software Data Protection

•

DAT A Polling for End of Write Detection

•

High Reliability CMOS Technology

– Endurance: 100,000K Cycles
– Data Retention: 10 Years

•

JEDEC Approved Byte-Wide Pinout

•

Commercial and Industrial Temperature Ranges

Description

The AT28LV010 is a high- pe r formance 3-volt only El ectr ic al ly Eras abl e an d Pr og ra m­mable Read Only Memory. Its 1 megabit of memory is organized as 131,072 words by
8 bits. Manufactured with Atmel’s advanced nonvolatile CMOS technology, the device
offers access time s to 200 ns with power dissi pation of j ust 54 mW. When the de vic e
is deselected, the CMOS standby current is less than 20 µA.

(continued)

1-Megabit
(128K x 8)
Low Voltage
Paged Parallel
EEPROMs

AT28LV010

Pin Configurations

Pin Name Function

A0 - A16 Addresses
CE
OE
WE Write Enable
I/O0 - I/O7 Data Inputs/Outputs
NC No Connect
DC Don’t Connect

NC
A16
A15
A12

A7
A6
A5
A4
A3
A2
A1

A0
I/O0
I/O1
I/O2

GND

PDIP

Top View

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

Chip Enable
Output En able

32

VCC

31

WE

30

NC

29

A14

28

A13

27

A8

26

A9

25

A11

24

OE

23

A10

22

CE

21

I/O7

20

I/O6

19

I/O5

18

I/O4

17

I/O3

A11

A13
A14

NC

WE

VCC

NC
A16
A15
A12

PLCC

Top View

A12

A15

A16DCVCCWENC

432

1

I/O2

GND

I/O3

323130

I/O4

I/O5

29
28
27
26
25
24
23
22
21

I/O6

A14
A13
A8
A9
A11
OE
A10
CE
I/O7

A7
A6
A5
A4
A3
A2
A1
A0

I/O0

5
6
7
8
9
10
11
12
13

14151617181920

I/O1

TSOP

Top View

1
2

A9

3

A8

4
5
6
7
8
9
10
11
12
13

A7

14

A6

15

A5

16

A4

OE

32

A10

31

CE

30

I/O7

29

I/O6

28

I/O5

27

I/O4

26

I/O3

25

GND

24

I/O2

23

I/O1

22

I/O0

21

A0

20

A1

19

A2

18

A3

17

Rev. 0395B–10/98

1

The AT28LV010 is accessed like a Static RAM for the read
or write cycle without the need for external components.
The device contai ns a 128- byte pa ge r egist er to a llow writ­ing of up to 128 bytes si mul tan eou sl y. Dur ing a wri te c ycle ,
the address and 1 to 128 bytes of data are internally
latched, freeing the address and data bus for other opera­tions. Following the initiation of a write cycle, the device will
automatically write the latched data using an internal con­trol timer. The end of a write cycle can be detected by

Block Diagram

polling of I/O7. On ce the end of a write c ycle has

DATA
been detected a new access for a read or write can begin.

Atmel’s 28LV010 has additional features to ensure high
quality and manufacturability. The device utilizes internal
error correction for extended endurance and improved data
retention character istics . Softwa re data protec tion is impl e­mented to guard against inadvertent writes. The device
also includes an extra 128 bytes of EEPRO M for device
identification or tracking.

Absolute Maximum Ratings*

Temperature Under Bias................................ -55°C to +125°C

Storage Temperature..................................... -65°C to +150°C

All Input Voltages (including NC Pins)

with Respect to Ground...................................-0.6V to +6.25V

All Output Voltages

with Respect to Ground.............................-0.6V to V

Voltage on OE

with Respect to Ground...................................-0.6V to +13.5V

and A9

+ 0.6V

CC

*NOTICE: Stresses beyond those listed under “Absolute

Maximum Ratings” may cause permanent dam­age to the de vic e. T his is a stres s r ating o nly an d
functional opera tion of the device at these or an y
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect
device reli abi li ty

2

AT28LV010

Device Operation

READ:

When CE
at the memory location determined by the address pins is
asserted on the outputs. The outputs are put in the high
impedance state when either CE
line control gives designers flexibility in preventing bus con­tention in their system.

WRITE:

128 bytes of data to be written into the device duri ng a sin­gle internal programming period. Each write operation must
be preceded by the software data protection (SDP) com­mand sequence. This s equence i s a s eries o f three uni que
write command operations that enable the internal write cir­cuitry. The command sequence and the data to be written
must conform to the software protected write cycle timing.
Addresses are latched o n the fall ing edge of WE
whichever occurs la st and data i s latched on th e rising
edge of WE
byte must be written within 150 µs (t
byte. If the t
accepting data and commence the internal programming
operation. If more than one data byte is to be written during
a single programming operation, they must reside on the
same page as defined by the state of the A7 - A16 inputs.
For each WE
operation, A7 - A16 must be the same.

The A0 to A6 inputs are used to specify which bytes wi thin
the page are to be written. The bytes may be lo ade d in any
order and may be altered within the same load period. Only
bytes which are specified for writing will be written; unnec­essary cycling of other bytes within the page does not
occur.

DATA

to indicate the end of a write cycle. During a byte or page
write cycle an attempted read of the last byte written will
result in the complement of the written data to be presented
on I/O7. Once the write cycle has been completed, true

The AT28LV010 is accessed like a Static RAM.

and OE are low and WE is high, the data stored

or OE is high. This dual-

The write operation of the AT28LV010 allows 1 to

or CE,

or CE, whichever occurs first. Each successive

) of the previous

limit is exceeded the AT28LV010 will ce ase

BLC

high to low transition during the page write

POLLING:

The AT28LV010 features DATA

BLC

Polling

AT28LV010

data is valid on all outputs, and the next write cycle may
begin. DATA
cycle.

TOGGLE BIT:

provides another m ethod for determining th e end of a write
cycle. During the write operation, successive attempts to
read data from the d evice will result i n I/O6 toggling
between one and zero. Once the write has completed, I/O6
will stop togglin g and v alid data will be read. R eading th e
toggle bit may begin at any time during the write cycle.

DATA PROTECTION:

vertent writes may oc cur during transiti ons of the ho st sys­tem power supply. Atmel has incorp orated both har dware
and software features that will protect the memory against
inadvertent writes.

HARDWARE PROTECTION:

against inadvertent writes to the AT28LV010 in the follow­ing ways: (a) V

2.0V (typical) the device will automatically time out 5 ms
(typical) before allowing a write; (b) write inhibit—holding
any one of OE
cycles; and (c) nois e filter—pu lses of le ss than 15 ns (typi­cal) on the WE

SOFTWARE DATA PROTECTION:

incorporates the industry standard software data prot ection
(SDP) function. Unlike standard 5-volt only EEPROM’s, the
AT28LV010 has SDP enabled at all times. Therefore, all
write operations must be preceded by the SDP command
sequence.

The data in the 3-byte co mma nd s equ enc e i s not wr i tten to
the device; the addresses in the co mmand sequen ce can
be utilized just lik e any other location in th e device. Any
attempt to write to the device without the 3-byte sequence
will start the internal timers. No data will be written to the
device. However, for the duration of t
will effectively be polling operations.

Polling may be gin a t any time during the write

In addition to DATA

If precautions are not taken, inad-

power-on delay—once VCC has reached

CC

low, CE high or WE high inhibits write

or CE inputs will not initiate a write cycle.

Polling the A T28L V010

Hardware features protect

The AT28LV010

, read operations

WC

3

DC and AC Operating Range

AT28LV010-20 AT28LV010-25

Operating
Temperature (Case)

V

Power Supply 3.3V ± 5% 3.3V ± 10%

CC

Com. 0°C - 70°C 0°C - 70°C
Ind. -40°C - 85°C -40°C - 85°C

Operating Modes

Mode CE OE WE I/O

Read V

(2)

Write
Standby/Write Inhibit V

IL

V

IL

IH

Write Inhibit X X V
Write Inhibit X V
Output Disable X V

X

V

IL

V

IH

(1)

IL

IH

V

IH

V

IL

D

OUT

D

IN

XHigh Z

IH

X
XHigh Z

Notes: 1. X can be VIL or VIH.

2. Refer to AC Programming Waveforms.

DC Characteristics

Symbol Parameter Condition Min Max Units

I

LI

I

LO

I

SB

I

CC

V

IL

V

IH

V

OL

V

OH

Input Load Current VIN = 0V to V
Output Leakage Current V

= 0V to V

I/O

CC

CC

1 µA
1 µA

Com. 20 µA

VCC Standby Current CMOS CE = V

V

Active Current f = 5 MHz; I

CC

- 0.3V to VCC + 1V

CC

= 0 mA; VCC = 3.6V 15 mA

OUT

Ind. 50 µA

Input Low Voltage 0.8 V
Input High Voltage 2.0 V
Output Low Voltage IOL = 1.6 mA; V
Output High Voltage IOH = -100 µA; V

= 3.0V 0.45 V

CC

= 3.0V 2.4 V

CC

4

AT28LV010