Rainbow Electronics DDS1693 User Manual

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DS1689/DS1693

3-Volt/5-Volt Serialized Real-Time Clock

with NV RAM Control

FEATURES

Incorporates industry standard DS1287 PC clock plus enhanced features:

§ +3- or +5V operation

§ 64-bit silicon serial number

§ 64-bit customer specific ROM or additional

serial number available

§ Power control circuitry supports system

power-on from date/time alarm or key closure

§ Automatic battery backup and write

protection to external SRAM

§ Crystal select bit allows RTC to operate with

6 pF or 12.5 pF crystal

§ 114 bytes user NV RAM

§ Auxiliary battery input

§ RAM clear input

§ Century register

§ 32 kHz output for power management

§ 32-bit VCC powered elapsed time counter

§ 32-bit V

powered elapsed time counter

BAT

§ 16-bit power cycle counter

§ Compatible with existing BIOS for original

DS1287 functions

§ Available as IC (DS1689) or standalone

module with embedded battery and crystal (DS1693)

§ IC is available in industrial temperature

version

§ Timekeeping algorithm includes leap year

compensation valid up to 2100

ORDERING INFORMATION

PART # DESCRIPTION

DS1689S RTC IC, 28-pin SOIC DS1689SN RTC IC, 28-pin SOIC IND DS1693 RTC Module; 28-pin DIP

PIN ASSIGNMENT

BAU

NC NC

RCLR

AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7

PWR

GND

DS1693 28-Pin Encapsulated Package

(740-mil)

CEI CEO

CCI

CCO

SQW NC

IRQ PSEL RD NC WR

CS KS

BAU

RCLR

AD0 AD1 AD2

AD3 AD4 AD5 AD6 AD7

PWR

GND

X1 X2

1 2

3 4

5 6

7 8

9 10

11 12

13 14

DS1689S 28-Pin SOIC

(330-mil)

PIN DESCRIPTION

X1 - Crystal Input X2 - Crystal Output

RCLR - RAM Clear Input

AD0-AD7 - Mux’ed Address/Data Bus

PWR - Power-on Interrupt Output

(Open drain)

KS - Kickstart Input

CS - RTC Chip Select Input

ALE - RTC Address Strobe

WR - RTC Write Data Strobe

RD - RTC Read Data Strobe

- RAM Power Supply Output

CCO

IRQ - Interrupt Request Output

(Open drain) SQW - Square Wave Output V

CCI

GND - Ground V

- Battery + Supply

BAT

- Auxiliary Battery Supply

BAUX

PSEL - +3- or +5V Power Select

CEI - RAM Chip Enable In

- +3- or +5V Main Supply

28 27

26 25

24 23

22 21

20 19

18 17

16 15

CEI CEO

CCI

CCO

SQW V

BAT

IRQ PSEL RD GND WR

LE CS

CEO - RAM Chip Enable Out

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DS1689/DS1693

DESCRIPTION

The DS1689/DS1693 is a real time clock (RTC) designed as a successor to the industry standard DS1285, DS1385, DS1485, and DS1585 PC real time clocks. This device provides the industry standard DS1285 clock function with the new feature of either +3.0- or +5.0 volt operation and automatic backup and write protection to an external SRAM. The DS1689 also incorporates a number of enhanced features including a silicon serial number, power-on/off control circuitry, and 114 bytes of user NVSRAM, power-on elapsed timer, and power cycle counter.

Each DS1689/DS1693 is individually manufactured with a unique 64-bit serial number as well as an additional 64-bit customer specific ROM or serial number. The serial number is programmed and tested at Dallas to insure that no two devices are alike. The serial number can be used to electronically identify a system for purposes such as establishment of a network node address or for maintenance tracking. Blocks of available numbers from Dallas Semiconductor can be reserved by the customer.

The serialized RTCs also incorporate power control circuitry, which allows the system to be powered on

via an external stimulus, such as a keyboard or by a time and date (wake-up) alarm. The PWR output pin can be triggered by one or either of these events, and can be used to turn on an external power supply.

The PWR pin is under software control, so that when a task is complete, the system power can then be shut down.

The DS1689/DS1693 incorporates a power-on elapsed time counter, a power-on cycle counter, and a battery powered continuous counter. These three counters provide valuable information for maintenance and warranty requirements.

Automatic backup and write protection for an external SRAM is provided through the V

CCO

and

CEO

pins. The lithium energy source used to permanently power the real time clock is also used to retain RAM data in the absence of VCC power through the V

pin. The chip enable output to RAM (

CCO

CEO

) is

controlled during power transients to prevent data corruption.

The DS1689 is a clock/calendar chip with the features described above. An external crystal and battery are the only components required to maintain time-of-day and memory status in the absence of power. The DS1693 incorporates the DS1689 chip, a 32.768 kHz crystal, and a lithium battery in a complete, self-contained timekeeping module. The entire unit is fully tested at Dallas Semiconductor such that a minimum of 10 years of timekeeping and data retention in the absence of V

is guaranteed.

OPERATION

The block diagram in Figure 1 shows the pin connections with the major internal functions of the DS1689/DS1693. The following paragraphs describe the function of each pin.

SIGNAL DESCRIPTIONS

GND, V

Five-volt operation is selected when the PSEL pin is at a logic 1. If PSEL is floated or at a logic 0, the device will be in auto-sense mode and will determine the correct operating voltage based on the V voltage level.

- DC power is provided to the device on these pins. V

CCI

is the +3-volt or +5-volt input.

CCI

PSEL (Power Select Input) - This pin selects whether 3-volt operation or 5-volt operation will be used. When PSEL is a logic 1, 5-volt operation is selected. When PSEL is a logic 0 or is floated, the device will be in auto-sense mode and will determine the correct mode of operation based on the voltage on V

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CCI

(External SRAM Power Supply Output) - This pin will be internally connected to V

CCO

is within nominal limits. However, during power fail, V

CCI

or V when V backup supply occurs at VPF if VPF is less than V the switch from V

(whichever is larger). For 5-volt operation, switch over from V

BAUX

drops below the larger of V

CCI

to the backup supply occurs when V

CCI

BAT

and V

BAUX

BAT

. For 3-volt operation, switch over from V

and V

CCI

will be internally connected to the V

CCO

to the backup supply occurs

CCI

. If VPF is greater than V

BAUX

drops below the larger of V

DS1689/DS1693 BLOCK DIAGRAM Figure 1

DS1689/DS1693

CCI

and V

BAT

and V

BAT

when

to the

BAUX

BAT

SQW (Square Wave Output) - The SQW pin can output a signal from one of 13 taps provided by the 15 internal divider stages of the real time clock. The frequency of the SQW pin can be changed by programming Register A as shown in Table 2. The SQW signal can be turned on and off using the SQWE bit in Register B. A 32 kHz SQW signal is output when SQWE=1, the Enable 32 kHz (E32K) bit in extended register 04BH is a logic 1, and VCC is above VPF. A 32 kHz square wave is also available when

is less than VPF if E32K=1, ABE=1, and voltage is applied to V

3 of 32

BAUX

DS1689/DS1693

AD0-AD7 (Multiplexed Bi-directional Address/Data Bus) - Multiplexed buses save pins because address information and data information time-share the same signal paths. The addresses are present during the first portion of the bus cycle and the same pins and signal paths are used for data in the second portion of the cycle. Address/data multiplexing does not slow the access time of the DS1689 since the bus change from address to data occurs during the internal RAM access time. Addresses must be valid prior to the latter portion of ALE, at which time the DS1689/DS1693 latches the address. Valid write data must

be present and held stable during the latter portion of the

outputs 8 bits of data during the latter portion of the

WR pulse. In a read cycle the DS1689/DS1693

RD pulse. The read cycle is terminated and the bus

returns to a high impedance state as RD transitions high. The address/data bus also serves as a bidirectional data path for the external extended RAM.

ALE (RTC Address Strobe Input; active high) - A pulse on the address strobe pin serves to demultiplex the bus. The falling edge of ALE causes the RTC address to be latched within the DS1689/DS1693.

RD (RTC Read Input; active low) - RD identifies the time period when the DS1689/DS1693 drives the

bus with RTC read data. The RD signal is an enable signal for the output buffers of the clock.

WR (RTC Write Input; active low) - The WR signal is an active low signal. The WR signal defines

the time period during which data is written to the addressed register.

CS (RTC Chip Select Input; active low) - The Chip Select signal must be asserted low during a bus

cycle for the RTC portion of the DS1689/DS1693 to be accessed. CS must be kept in the active state

during RD and WR timing. Bus cycles, which take place with ALE asserted but without asserting, CS will latch addresses. However, no data transfer will occur.

IRQ (Interrupt Request Output; open drain, active low) - The IRQ pin is an active low output of the

DS1689/DS1693 that can be tied to the interrupt input of a processor. The IRQ output remains low as long as the status bit causing the interrupt is present and the corresponding interrupt-enable bit is set. To

clear the

IRQ pin, the application software must clear all enabled flag bits contributing to IRQ ’s active

state.

When no interrupt conditions are present, the IRQ level is in the high impedance state. Multiple

interrupting devices can be connected to an

IRQ bus. The IRQ pin is an open drain output and requires an

external pull-up resistor.

CEI (RAM Chip Enable Input; active low) - CEI should be driven low to enable the external RAM.

CEO (RAM Chip Enable Output; active low) - When power is valid, CEO will equal CEI . When

power is not valid,

PWR (Power-on Output; open drain, active low) - The PWR pin is intended for use as an on/off

CEO will be driven high regardless of CEI .

control for the system power. With VCC voltage removed from the DS1689/DS1693, PWR may be

automatically activated from a Kickstart input via the

system is powered on, the state of

PWR can be controlled via bits in the Dallas registers.

KS pin or from a Wake-up interrupt. Once the

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DS1689/DS1693

KS (Kickstart Input; active low) - When V

is removed from the DS1689/DS1693, the system can be

powered on in response to an active low transition on the KS pin, as might be generated from a key closure. V

function is used, and the KS pin must be pulled up to the V

must be present and Auxiliary Battery Enable bit (ABE) must be set to 1 if the kickstart

BAUX

supply. While VCC is applied, the KS pin

BAUX

can be used as an interrupt input.

RCLR (RAM Clear Input; active low) - If enabled by software, taking RCLR low will result in the

clearing of the 114 bytes of user RAM. When enabled,

RCLR can be activated whether or not V

present.

clock/calendar and External NVRAM if V

- Auxiliary battery input required for kickstart and wake-up features. This input also supports

BAUX

is at lower voltage or is not present. A standard +3-volt

BAT

lithium cell or other energy source can be used. Battery voltage must be held between +2.5 and +3.7 volts for proper operation. If V

is not going to be used it should be grounded and auxiliary battery enable

BAUX

bit bank 1, register 4BH, should=0.

DS1689 ONLY

X1, X2 - Connections for a standard 32.768 kHz quartz crystal. For greatest accuracy, the DS1689 must be used with a crystal that has a specified load capacitance of either 6 pF or 12.5 pF. The Crystal Select (CS) bit in Extended Control Register 4B is used to select operation with a 6 pF or 12.5 pF crystal. The crystal is attached directly to the X1 and X2 pins. There is no need for external capacitors or resistors. Note: X1 and X2 are very high impedance nodes. It is recommended that they and the crystal by guardringed with ground and that high frequency signals be kept away from the crystal area.

For more information on crystal selection and crystal layout considerations, please consult Application Note 58, “Crystal Considerations with Dallas Real Time Clocks.” The DS1689 can also be driven by an external 32.768 kHz oscillator. In this configuration, the X1 pin is connected to the external oscillator signal and the X2 pin is floated.

- Battery input for any standard 3-Volt lithium cell or other energy source. Battery voltage must be

BAT

held between 2.5 and 3.7 volts for proper operation.

POWER-DOWN/POWER-UP CONSIDERATIONS

The real-time clock function will continue to operate and all of the RAM, time, calendar, and alarm memory locations remain nonvolatile regardless of the level of the V the DS1689/DS1693 and reaches a level of greater than VPF (power fail trip point), the device becomes accessible after t

, provided that the oscillator is running and the oscillator countdown chain is not in

REC

reset (see Register A). This time period allows the system to stabilize after power is applied.

When PSEL is floating or logic 0, the DS1689 is in autosense mode and 3-volt or 5-volt operation is determined based on the voltage on V V

rises above 4.5 volts for a minimum of t

CCI

does not rise above the level of 4.25 volts. Selection of the power supply input levels requires

CCI

. Selection of 5-volt operation is automatically invoked when

CCI

. However, 3-volt operation is automatically selected if

REC

150 ms of input stability before operation can commence.

input. When V

CCI

is applied to

CCI

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DS1689/DS1693

When 5-volt operation is selected, the device is fully accessible and data can be written and read only when V

is greater than 4.5 volts. When V

CCI

is below 4.5 volts, read and writes are inhibited. However,

CCI

the timekeeping function continues unaffected by the lower input voltage. As VCC falls below the greater of V the V

BAT

and V

pin or V

, the RAM and timekeeper are switched over to a lithium battery connected either to

BAUX

pin.

BAUX

When 3-volt operation is selected and applied within normal limits, the device is fully accessible and data can be written or read. When V V

and V

BAT

BAUX

from V

) when V

to the backup supply when V

CCI

, the power supply is switched from V

BAUX

drops below VPF. If VPF is greater than V

CCI

falls below VPF, access to the device is inhibited. If VPF is less than

CCI

to the backup supply (the greater of V

CCI

BAT

drops below the larger of V

CCI

and V

, the power supply is switched

BAUX

BAT

and V

BAUX

BAT

and

When VCC falls below VPF, the chip is write-protected. With the possible exception of the KS , PWR , and SQW pins, all inputs are ignored and all outputs are in a high impedance state.

RTC ADDRESS MAP

The address map for the RTC registers of the DS1689/DS1693 is shown in Figure 2. The address map consists of the 14-clock/calendar registers. Ten registers contain the time, calendar, and alarm data, and four bytes are used for control and status. All registers can be directly written or read except for the following:

1. Registers C and D are read-only.

2. Bit 7 of Register A is read-only.

3. The high order bit of the seconds byte is read-only.

DS1689 REAL TIME CLOCK ADDRESS MAP Figure 2

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DS1689/DS1693

TIME, CALENDAR AND ALARM LOCATIONS

The time and calendar information is obtained by reading the appropriate register bytes shown in Table 1. The time, calendar, and alarm are set or initialized by writing the appropriate register bytes. The contents of the time, calendar, and alarm registers can be either Binary or Binary-Coded Decimal (BCD) format. Table 1 shows the binary and BCD formats of the twelve time, calendar, and alarm locations that reside in both bank 0 and in bank 1, plus the two extended registers that reside in bank 1 only (bank 0 and bank 1 switching will be explained later in this text).

Before writing the internal time, calendar, and alarm registers, the SET bit in Register B should be written to a logic 1 to prevent updates from occurring while access is being attempted. Also at this time, the data format (binary or BCD) should be set via the data mode bit (DM) of Register B. All time, calendar, and alarm registers must use the same data mode. The set bit in Register B should be cleared after the data mode bit has been written to allow the real-time clock to update the time and calendar bytes.

Once initialized, the real-time clock makes all updates in the selected mode. The data mode cannot be changed without reinitializing the 10 data bytes. The 24/12 bit cannot be changed without reinitializing the hour locations. When the 12-hour format is selected, the high order bit of the hours byte represents PM when it is a logic 1. The time, calendar, and alarm bytes are always accessible because they are double-buffered. Once per second the 10 bytes are advanced by one second and checked for an alarm condition. If a read of the time and calendar data occurs during an update, a problem exists where seconds, minutes, hours, etc. may not correlate. The probability of reading incorrect time and calendar data is low. Several methods of avoiding any possible incorrect time and calendar reads are covered later in this text.

The 4 alarm bytes can be used in two ways. First, when the alarm time is written in the appropriate hours, minutes, and seconds alarm locations, the alarm interrupt is initiated at the specified time each day if the alarm enable bit is high. The second use condition is to insert a “don’t care” state in one or more of the 4 alarm bytes. The “don’t care” code is any hexadecimal value from C0 to FF. The 2 most significant bits of each byte set the “don’t care” condition when at logic 1. An alarm will be generated each hour when the “don’t care” bits are set in the hours byte. Similarly, an alarm is generated every minute with “don’t care” codes in the hours and minute alarm bytes. The “don’t care” codes in all 3-alarm bytes create an interrupt every second. The 3 alarm bytes may be used in conjunction with the date alarm as described in the Wakeup/Kickstart section. The century counter will be discussed later in this text.

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DS1689/DS1693

TIME, CALENDAR AND ALARM DATA MODES Table 1

ADDRESS

LOCATION

00H Seconds 0-59 00-3B 00-59 01H Seconds Alarm 0-59 00-3B 00-59 02H Minutes 0-59 00-3B 00-59 03H Minutes Alarm 0-59 00-3B 00-59

06H Day of Week

07H Date of Month 1-31 01-1F 01-31 08H Month 1-12 01-0C 01-12 09H Year 0-99 00-63 00-99

BANK1, 48H Century 0-99 00-63 00-99

BANK 1, 49H Date Alarm 1-31 01-1F 01-31

FUNCTION

Hours 12-hr Mode 1-12 01-0C AM, 81-8C PM 01-12 AM, 81-92 PM04H Hours 24-hr Mode 0-23 00-17 00-23 Hours Alarm 12-hr Mode Hours Alarm 24-hr Mode

Sunday=1

DECIMAL

RANGE

1-12 01-0C AM, 81-8C PM 01-12 AM, 81-92 PM05H

0-23 00-17 00-23

1-7 01-07 01-07

BINARY DATA

MODE

RANGE

BCD DATA

MODE

CONTROL REGISTERS

The four control registers; A, B, C, and D reside in both bank 0 and bank 1. These registers are accessible at all times, even during the update cycle.

NONVOLATILE RAM - RTC

The 114 general-purpose nonvolatile RAM bytes are not dedicated to any special function within the DS1689/DS1693. They can be used by the application program as nonvolatile memory and are fully available during the update cycle. This memory is directly accessible when bank 0 is selected.

INTERRUPT CONTROL

The DS1689/DS1693 includes six separate, fully automatic sources of interrupt for a processor:

1. Alarm interrupt

2. Periodic interrupt

3. Update-ended interrupt

4. Wake-up interrupt

5. Kickstart interrupt

6. RAM clear interrupt

The conditions, which generate each of these independent interrupt conditions, are described in greater detail elsewhere in this data sheet. This section describes the overall control of the interrupts.

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DS1689/DS1693

The application software can select which interrupts, if any are to be used. There are a total of 6 bits including 3 bits in Register B and 3 bits in Extended Register B which enable the interrupts. The extended register locations are described later. Writing a logic 1 to an interrupt enable bit permits that interrupt to

be initiated when the event occurs. A logic 0 in the interrupt enable bit prohibits the IRQ . pin from being

asserted from that interrupt condition. If an interrupt flag is already set when an interrupt is enabled, IRQ will immediately be set at an active level, even though the event initiating the interrupt condition may have occurred much earlier. As a result, there are cases where the software should clear these earlier generated interrupts before first enabling new interrupts.

When an interrupt event occurs, the relating flag bit is set to a logic 1 in Register C or in Extended Register A. These flag bits are set regardless of the setting of the corresponding enable bit located either in Register B or in Extended Register B. The flag bits can be used in a polling mode without enabling the corresponding enable bits.

However, care should be taken when using the flag bits of Register C as they are automatically cleared to 0 immediately after they are read. Double latching is implemented on these bits so that bits which are set remain stable throughout the read cycle. All bits which were set are cleared when read and new interrupts which are pending during the read cycle are held until after the cycle is completed. One, 2, or 3 bits can be set when reading Register C. Each utilized flag bit should be examined when read to ensure that no interrupts are lost.

The flag bits in Extended Register A are not automatically cleared following a read. Instead, each flag bit can be cleared to 0 only by writing 0 to that bit.

When using the flag bits with fully enabled interrupts, the IRQ line will be driven low when an interrupt

flag bit is set and its corresponding enable bit is also set. IRQ will be held low as long as at least one of the six possible interrupt sources has it s flag and enable bits both set. The IRQF bit in Register C is a 1

whenever the IRQ pin is being driven low as a result of one of the six possible active sources. Therefore, determination that the DS1689/DS1693 initiated an interrupt is accomplished by reading Register C and finding IRQF=1. IRQF will remain set until all enabled interrupt flag bits are cleared to 0.

SQUARE WAVE OUTPUT SELECTION

The SQW pin can be programmed to output a variety of frequencies divided down from the 32.768 kHz crystal tied to X1 and X2. The square wave output is enabled and disabled via the SQWE bit in Register B. If the square wave is enabled (SQWE=1), then the output frequency will be determined by the settings of the E32K bit in Extended Register B and by the RS3-0 bits in Register A. If the E32K = 1, then a

32.768 kHz square wave will be output on the SQW pin regardless of the settings of RS3-0.

If E32K = 0, then the square wave output frequency is determined by the RS3-0 bits. These bits control a 1-of-15 decoder, which selects one of 13 taps that divide the 32.768 kHz frequency. The RS3-0 bits establish the SQW output frequency as shown in Table 2. In addition, RS3-0 bits control the periodic interrupt selection as described below.

If SQWE1, E32K=1, and the Auxiliary Battery Enable bit (ABE, bank 1; register 04BH) is enabled, and voltage is applied to V the absence of V

. This facility is provided to clock external power management circuitry. If any of the

then the 32 kHz square wave output signal will be output on the SQW pin in

BAUX

above requirements are not met, no square wave output signal will be generated on the SQW pin in the absence of V

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DS1689/DS1693

A pattern of 01X in the DV2, DV1, and DV0, bits respectively, will turn the oscillator on and enable the countdown chain. Note that this is different than the DS1287, which required a pattern of 010 in these bits. DV0 is now a “don’t care” because it is used for selection between register banks 0 and 1. A pattern of 11X will turn the oscillator on, but the oscillator’s countdown chain will be held in reset, as it was in the DS1287. Any other bit combination for DV2 and DV1 will keep the oscillator off.

PERIODIC INTERRUPT SELECTION

The periodic interrupt will cause the IRQ pin to go to an active state from once every 500 ms to once every 122 ms. This function is separate from the alarm interrupt which can be output from once per

second to once per day. The periodic interrupt rate is selected using the same RS3-0 bits in Register A which select the square wave frequency (see Table 2). Changing the bits affects both the square wave frequency and the periodic interrupt output. However, each function has a separate enable bit in Register B. The SQWE bit controls the square wave output. Similarly, the periodic interrupt is enabled by the PIE bit in Register B. The periodic interrupt can be used with software counters to measure inputs, create output intervals, or await the next needed software function.

UPDATE CYCLE

The Serialized RTC executes an update cycle once per second regardless of the SET bit in Register B. When the SET bit in Register B is set to 1, the user copy of the double-buffered time, calendar, alarm and elapsed time byte is frozen and will not update as the time increments. However, the time countdown chain continues to update the internal copy of the buffer. This feature allows the time to maintain accuracy independent of reading or writing the time, calendar, and alarm buffers and also guarantees that time and calendar information is consistent. The update cycle also compares each alarm byte with the corresponding time byte and issues an alarm if a match or if a “don’t care” code is present in all three positions.

There are three methods that can handle access of the real-time clock that avoid any possibility of accessing inconsistent time and calendar data. The first method uses the update-ended interrupt. If enabled, an interrupt occurs after every up date cycle that indicates that over 999 ms are available to read valid time and date information. If this interrupt is used, the IRQF bit in Register C should be cleared before leaving the interrupt routine.

A second method uses the update-in-progress bit (UIP) in Register A to determine if the update cycle is in progress. The UIP bit will pulse once per second. After the UIP bit goes high, the update transfer occurs 244 ms later. If a low is read on the UIP bit, the user has at least 244 ms before the time/calendar data will be changed. Therefore, the user should avoid interrupt service routines that would cause the time needed to read valid time/calendar data to exceed 244 ms.

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