Rainbow Electronics DAB-IMU-C01 User Manual

A

Programmable Low Power Gyroscope

FEATURES

Yaw rate gyroscope with digital range scaling

±80°/sec, ±160°/sec, and ±320°/sec settings
14-bit digital gyroscope sensor outputs
12-bit digital temperature sensor output
Calibrated sensitivity and bias

ADIS16250: +25°C

ADIS16255: −40°C to +85°C
In-system, auto-zero for bias drift calibration
Digitally controlled sample rate
Digitally controlled frequency response
Dual alarm settings with configurable operation
Embedded integration for short-term angle estimates
Digitally activated self-test
Digitally activated low power mode

Interrupt-driven wake-up
SPI®-compatible serial interface
50 Hz sensor bandwidth
Auxiliary 12-bit ADC input and 12-bit DAC output
Auxiliary digital input/output
Single-supply operation: 4.75 V to 5.25 V
2000 g powered shock survivability

ADIS16250/ADIS16255

APPLICATIONS

Instrumentation control
Platform control and stabilization
Motion control and analysis
Avionics instrumentation
Navigation
Image stabilization
Robotics

FUNCTIONAL BLOCK DIAGRAM

UX

AUX

RATE

FILT

VCC

COM

TEMPERAT URE

SENSOR

GYROSCOPE

SENSOR

SELF-TEST

ADC

POWER

MANAGEMENT

VREF

DAC

SIGNAL

CONDITI ONING

AND

CONVERSION

CONTROL

ALARM

RST DIO0 DIO1

Figure 1.

CALIBRATI ON

PROCESSING

DIGITAL

AND

DIGITAL

AUXILIARY

I/O

ADIS16250/

ADIS16255

SPI

PORT

CS

SCLK

DIN

DOUT

06070-001

GENERAL DESCRIPTION

The ADIS16250/ADIS16255 are complete angular rate meas­urement systems available in a single compact package enabled
by Analog Devices, Inc. iSensor™ integration. By enhancing
Analog Devices iMEMS® sensor technology with an embedded
signal processing solution, the ADIS16250/ADIS16255 provide
factory-calibrated and tunable digital sensor data in a convenient
format that can be accessed using a simple SPI serial interface.
The ADIS16255 additionally provides an extended temperature
calibration. The SPI interface provides access to measurements
for the gyroscope, temperature, power supply, and one auxiliary
analog input. Easy access to calibrated digital sensor data
provides developers with a system-ready device, reducing
development time, cost, and program risk.

The device range can be digitally selected from three different
settings: ±80°/sec, ±160°/sec, and ±320°/sec. Unique charac­teristics of the end system are accommodated easily through

Rev. B

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

several built-in features, including a single-command auto-zero
recalibration function, as well as configurable sample rate and
frequency response. Additional features can be used to further
reduce system complexity, including:

• Configurable alarm function

• Auxiliary 12-bit ADC and DAC

• Two configurable digital I/O ports

• Digital self-test function

System power dissipation can be optimized via the ADIS16250/
ADIS16255 power management features, including an interrupt­driven wake-up. The ADIS16250/ADIS16255 are available in an
11 mm × 11 mm × 5.5 mm, laminate-based land grid array
(LGA) package with a temperature range of −40°C to +85°C.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2006–2007 Analog Devices, Inc. All rights reserved.

ADIS16250/ADIS16255

TABLE OF CONTENTS

Features.............................................................................................. 1

Applications....................................................................................... 1

Functional Block Diagram .............................................................. 1

General Description ......................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Timing Specifications .................................................................. 5

Absolute Maximum Ratings............................................................ 6

ESD Caution.................................................................................. 6

Pin Configuration and Function Descriptions............................. 7

Recommended Layout................................................................. 7

Typical Performance Characteristics ............................................. 8

Theory of Operation ...................................................................... 10

Overview...................................................................................... 10

Relative Angle Estimate............................................................. 10

Factory Calibration .................................................................... 10

Auxiliary ADC Function........................................................... 10

Basic Operation .............................................................................. 11

Serial Peripheral Interface (SPI)............................................... 11

Data Output Register Access .................................................... 12

Programming and Control............................................................ 13

Control Register Overview ....................................................... 13

Control Register Structure........................................................ 13

Calibration................................................................................... 14

Global Commands ..................................................................... 14

Operational Control................................................................... 14

Status and Diagnostics............................................................... 16

Outline Dimensions....................................................................... 20

Ordering Guide .......................................................................... 20

REVISION HISTORY

3/07—Rev. A to Rev. B

Changes to Table 2 and Figure 2..................................................... 5

Changes to Table 8.......................................................................... 13

Changes to Table 9 and Table 11................................................... 14

Changes to Table 24........................................................................ 16

Changes to Data-Ready I/O Indicator Section........................... 17

Changes to Self-Test Section ......................................................... 17

2/07—Rev. 0 to Rev. A

Added ADIS16255..............................................................Universal

Changes to Table 1............................................................................ 3

Changes to Table 2............................................................................ 5

Changes to Figure 2.......................................................................... 5

Changes to Typical Performance Characteristics......................... 8

Deleted Temperature Sensor Section ........................................... 11

Added Factory Calibration Section.............................................. 11

Changes to Table 7.......................................................................... 12

Changes to Table 8.......................................................................... 13

Changes to Table 11........................................................................ 14

Changes to Table 19........................................................................ 16

Changes to Flash Memory Endurance Section........................... 18

Changes to Ordering Guide.......................................................... 20

10/06—Revision 0: Initial Version

Rev. B | Page 2 of 20

ADIS16250/ADIS16255

SPECIFICATIONS

TA = −40°C to +85°C, VCC = 5.0 V, angular rate = 0°/sec, ±1 g, ±320°/sec range setting, unless otherwise noted.

Table 1.

Parameter Conditions Min Typ Max Unit

SENSITIVITY

25°C, dynamic range = ±320°/sec
25°C, dynamic range = ±160°/sec 0.03663 °/sec/LSB
25°C, dynamic range = ±80°/sec 0.01832 °/sec/LSB
Initial Tolerance 25°C, dynamic range = ±320°/sec ±0.2 ±1 %
Temperature Coefficient ADIS16250 (see Figure 8) 225 ppm/°C
ADIS16255 (see Figure 11) 25 ppm/°C
Nonlinearity Best fit straight line 0.1 % of FS

BIAS

In Run Bias Stability 25°C, 1σ 0.016 °/sec
Turn-On-to-Turn-On Bias Stability 25°C, 1σ 0.05 °/sec
Angular Random Walk 25°C, 1σ 3.6 °/√hour
Temperature Coefficient ADIS16250 (see Figure 7) 0.03 °/sec/°C
ADIS16255 (see Figure 10) 0.005 °/sec/°C
Linear Acceleration Effect Any axis 0.2 °/sec/g
Voltage Sensitivity VCC = 4.75 V to 5.25 V 1.0 °/sec/V

NOISE PERFORMANCE

Output Noise At 25°C, ±320°/sec range, no filtering 0.48 °/sec rms
At 25°C, ±160°/sec range, 4-tap filter setting 0.28 °/sec rms
At 25°C, ±80°/sec range, 16-tap filter setting 0.14 °/sec rms
Rate Noise Density

FREQUENCY RESPONSE

3 dB Bandwidth

Sensor Resonant Frequency 14 kHz

SELF-TEST STATE

Change for Positive Stimulus 320°/sec dynamic range setting 439 721 1092 LSB
Change for Negative Stimulus 320°/sec dynamic range setting −439 −721 −1092 LSB
Internal Self-Test Cycle Time 20 ms

TEMPERATURE SENSOR

Output at 25°C 0 LSB
Scale Factor 6.88 LSB/°C

ADC INPUT

Resolution 12 Bits
Integral Nonlinearity ±2 LSB
Differential Nonlinearity ±1 LSB
Offset Error ±4 LSB
Gain Error ±2 LSB
Input Range 0 2.5 V
Input Capacitance During acquisition 20 pF

ON-CHIP VOLTAGE REFERENCE 2.5 V

Accuracy At 25°C −10 +10 mV
Temperature Coefficient ±40 ppm/°C
Output Impedance 70 Ω

1

Clockwise rotation is positive output

At 25°C, f = 25 Hz, ±320°/sec range,
no filtering

Analog Bandwidth section for

See the
adjustment

2

0.07326 °/sec/LSB

0.056 °/sec/√Hz rms

50 Hz

Rev. B | Page 3 of 20

ADIS16250/ADIS16255

Parameter Conditions Min Typ Max Unit

DAC OUTPUT 5 kΩ/100 pF to GND

Resolution 12 Bits

Relative Accuracy For Code 101 to Code 4095 4 LSB

Differential Nonlinearity 1 LSB

Offset Error ±5 mV

Gain Error ±0.5 %

Output Range 0 to 2.5 V

Output Impedance 2 Ω

Output Settling Time 10 µs
LOGIC INPUTS

Input High Voltage, V

Input Low Voltage, V

Logic 1 Input Current, I

Logic 0 Input Current, I

All except RST

3

RST

Input Capacitance, CIN 10 pF
DIGITAL OUTPUTS

Output High Voltage, VOH I

Output Low Voltage, VOL I
SLEEP TIMER

Timeout Period
START-UP TIME

Initial 160 ms

Sleep Mode Recovery 2.5 ms
FLASH MEMORY

Endurance

Data Retention

5

6

CONVERSION RATE

Minimum Conversion Time 3.906 ms

Maximum Conversion Time 7.75 sec

Maximum Throughput Rate 256 SPS

Minimum Throughput Rate 0.129 SPS
POWER SUPPLY

Operating Voltage Range, VCC 4.75 5.0 5.25 V

Power Supply Current Normal mode at 25°C 18 mA

Fast mode at 25°C 44 mA
Sleep mode at 25°C 425 A

1

ADIS16255 characterization data represents ±4σ to fall within the ±1% limit.

2

The sensor is capable of ±600°/sec, but the specifications herein are for ±320°/sec only.

3

RST

The

pin has an internal pull-up.

4

Guaranteed by design.

5

Endurance is qualified as per JEDEC Standard 22 Method A117 and measured at −40°C, +25°C, +85°C, and +125°C.

6

Retention lifetime equivalent at junction temperature (TJ) 55°C, as per JEDEC Standard 22 Method A117. Retention lifetime decreases with junction temperature.

2.0 V

INH

0.8 V

INL

CS signal when used to wake up from

For

0.55 V

sleep mode

V

INH

V

INL

= 3.3 V ±0.2 ±10 µA

IH

= 0 V

IL

−40 −60 A

−1 mA

= 1.6 mA 2.4 V

SOURCE

= 1.6 mA 0.4 V

SINK

4

0.5 128 sec

20,000 Cycles
TJ = 55°C 20 Years

Rev. B | Page 4 of 20

ADIS16250/ADIS16255

TIMING SPECIFICATIONS

TA = −40°C to +85°C, VCC = 5.0 V, unless otherwise noted.

Table 2.

Parameter Description Min

f

Fast mode, SMPL_PRD ≤ 0x07 (fS ≥ 64 Hz) 0.01 2.5 MHz

SCLK

1

Typ Max

1

Unit

Normal mode, SMPL_PRD ≥ 0x08 (fS ≤ 56.9 Hz) 0.01 1.0 MHz
t

Data rate period, fast mode, SMPL_PRD ≤ 0x07 (fS ≥ 64 Hz) 32 s

DATARATE

Data rate period, normal mode, SMPL_PRD ≥ 0x08 (fS ≤ 56.9 Hz) 42 s
t

Stall period, fast mode, SMPL_PRD ≤ 0x07 (fS ≥ 64 Hz) 9 s

STALL

Stall period, normal mode, SMPL_PRD ≥ 0x08 (fS ≤ 56.9 Hz) 12 s
tCS Chip select to clock edge 48.8 ns
t

Data output valid after SCLK falling edge2 100 ns

DAV

t

Data input setup time before SCLK rising edge 24.4 ns

DSU

t

Data input hold time after SCLK rising edge 48.8 ns

DHD

tDF Data output fall time 5 12.5 ns
tDR Data output rise time 5 12.5 ns
t

SFS

CS high after SCLK edge

3

5 ns

Flash update time (power supply must be within range) 50 ms

1

Guaranteed by design; not production tested.

2

The MSB presents an exception to this parameter. The MSB clocks out on the falling edge of CS. The rest of the DOUT bits are clocked after the falling edge of SCLK and

are governed by this specification.

3

This parameter may need to be expanded to allow for proper capture of the LSB. After CS goes high, the DOUT line goes into a high impedance state.

t

DATARATE

CS

SCLK

t

DATASTALL

06070-026

Figure 2. SPI Chip Select Timing

CS

SCLK

DOUT

DIN

t

CS

*

*NOT DEFINE D

1 2 3 4 5 6 15 16

t

DAV

MSB DB14

W/R A5 A4 A3 A2

DB13 DB12 DB10DB11 DB2 LSBDB1

t

DSU

t

DHD

D2

D1 LSB

t

SFS

06070-003

Figure 3. SPI Timing

(Utilizing SPI Settings Typically Identified as Phase = 1, Polarity = 1)

Rev. B | Page 5 of 20

ADIS16250/ADIS16255

ABSOLUTE MAXIMUM RATINGS

Table 3.

Parameter Rating

Acceleration (Any Axis, Unpowered, 0.5 ms) 2000 g
Acceleration (Any Axis, Powered, 0.5 ms) 2000 g
VCC to COM −0.3 V to +6.0 V
Digital Input/Output Voltage to COM −0.3 V to +5.5 V
Analog Inputs to COM −0.3 V to +3.5 V
Operating Temperature Range1 −40°C to +125°C
Storage Temperature Range1 −65°C to +150°C

1

Extended exposure to temperatures outside of the specified temperature

range of −40°C to +85°C can adversely affect the accuracy of the factory
calibration. For best accuracy, store the parts within the specified operating
range of −40°C to +85°C.

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

RATE

AXIS

LONGIT UDINAL

AXIS

10

6

LATERAL

AXIS

5

1

Figure 4. RATEOUT Level Increase with Clockwise Rotation Increase

RATEOUT

RATEIN

+8191 LSB

CLOCKWISE
ROTATIO N

–8192 LSB

ESD CAUTION

06070-011

Rev. B | Page 6 of 20

ADIS16250/ADIS16255

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

COM

COM

VREF

20

SCLK

DOUT

DIN

CS

DIO0

19 18 17

1

ADIS16250/

ADIS16255

2

(Not To Scale)

3

POSITIVE O UTPUT

4

ROTATIO NAL

5

DNC = DO NOT CONNECT

Figure 5. Pin Configuration

Table 4. Pin Function Descriptions

Pin No. Mnemonic Type1Description

1 SCLK I SPI, Serial Clock.
2 DOUT O SPI, Data Output.
3 DIN I SPI, Data Input.
4

CS

I SPI, Chip Select, Active Low.
5, 6 DIO0, DIO1 I/O Multifunction Digital Input/Output Pin.
7

RST

I Reset, Active Low. This resets the sensor signal conditioning circuit and initiates a start-up sequence.
8, 9, 10, 11 DNC – Do Not Connect.

12 AUX DAC O Auxiliary DAC Analog Output Voltage.
13 AUX ADC I Auxiliary ADC Analog Input Voltage.
14 RATE O Analog Rate Signal Output (Uncalibrated).
15 FILT I

Analog Amplifier Summing Junction. This is used for setting the analog bandwidth. See the
Bandwidth

section for more details.
16, 17 VCC S 5.0 V Power Supply.
18, 19 COM S Common. Reference point for all circuitry in the ADIS16250/ADIS16255.
20 VREF O Precision Reference Output.

1

S = supply; O = output; I = input.

TOP VIEW

DIRECTION

876

VCC VCC

16

109

DNC

DNCDNCDIO1 RST

15

FILT

14

RATE

AUX

13

ADC

AUX

12

DAC

DNC

11

06070-004

Analog

RECOMMENDED LAYOUT

5.0865

3.800
8×

10.1732×7.600

11mm × 11mm STACKED LGA P ACKAGE

4×

1.127

8×

20×

Figure 6. Recommended Pad Layout (Units in Millimeters)

Rev. B | Page 7 of 20

0.773
16×

0.500
20×

06070-010

ADIS16250/ADIS16255

TYPICAL PERFORMANCE CHARACTERISTICS

4

4

3

2

1

0

BIAS (°/s)

–1

–2

–3

–4

–50 –35 –20 –5 10 25 40 55 70 85 100

TEMPERATURE ( °C)

+1σ

–1σ

Figure 7. Bias vs. Temperature, ADIS16250

2.0

1.5

1.0

SENSITIVITY (%)

0.5

0

–0.5

–1.0

–1.5

+1σ

µ

–1σ

3

2

1

0

BIAS (°/s)

µ

06070-012

–1

–2

–3

–4

–50 –40 –30 –20 –10 0 10 20 30 40 50 60 70 80 90

+1σ

µ

–1σ

TEMPERATURE ( °C)

06070-024

Figure 10. Bias vs. Temperature, ADIS16255

2.0

1.5

1.0

0.5

0

–0.5

SENSITIVITY (%)

–1.0

–1.5

+1σ

µ

–1σ

–2.0

–50 100857055402510–5–20–35

TEMPERATURE ( °C)

Figure 8. Sensitivity vs. Temperature, ADIS16250

4

3

2

1

0

BIAS (°/s)

–1

–2

–3

–4

MINIMUM TYPICAL MAXIMUM

SUPPLY VO LTAGE (4.75V, 5.00V, 5.25V )

Figure 9. Bias vs. Supply Voltage

–2.0

–50–35–20–5102540557080

06070-016

TEMPERATURE ( °C)

06070-025

Figure 11. Sensitivity vs. Temperature, ADIS16255

2.0

1.5

1.0

0.5

0

–0.5

SENSITIVITY (%)

–1.0

–1.5

–2.0

06070-013

MINIMUM TYPICAL MAXIMUM

SUPPLY VO LTAGE ( 4.75V, 5.00V , 5.25V)

06070-017

Figure 12. Sensitivity vs. Supply Voltage

Rev. B | Page 8 of 20

ADIS16250/ADIS16255

–

1

13.75

13.70

13.65

13.60

0.1

ROOT ALL AN VARIANCE (°/ s)

0.01

0.1 1 10 100 1000

TAU (Seconds)

Figure 13. Root Allan Variance vs. TAU, ±320°/sec Range

44

42

40

38

36

34

32

30

28

CURRENT (mA)

26

24

22

20

18

16

–50 –35 –20 –5 10 25 40 55 70 85 100

FAST MODE

NORMAL MODE

TEMPERATURE (°C)

Figure 14. Current vs. Temperature

13.55

13.50

SENSITIVITY (°/s/LSB)

13.45

13.40

13.35
0 600500400300200100

06070-014

RATE (° /s)

06070-018

Figure 16. Sensitivity vs. Angular Rate, ±320°/sec Range

65

60

55

50

45

SELF-TEST (°/s)

40

35

30

–50 –35 –20 –5 10 25 40 55 70 85 100

06070-019

TEMPERATURE ( °C)

06070-020

Figure 17. Positive Self-Test vs. Temperature

0.5

0.4

0.3

0.2

0.1

BIAS (°/s)

–0.1

–0.2

–0.3

–0.4

–0.5

0

0 30002500200015001000500

TIME (Minutes)

Figure 15. Bias vs. Time

06070-015

30

–35

–40

–45

–50

–55

SELF-TEST (°/s)

–60

–65

–70

–50 –35 –20 –5 10 25 40 55 70 85 100

TEMPERATURE ( °C)

Figure 18. Negative Self-Test vs. Temperature

06070-022

Rev. B | Page 9 of 20

ADIS16250/ADIS16255

V

THEORY OF OPERATION

OVERVIEW

The core angular rate sensor integrated inside the ADIS16250/
ADIS16255 is based on the Analog Devices iMEMS technology.
This sensor operates on the principle of a resonator gyroscope.
Two polysilicon sensing structures each contain a dither frame
electrostatically driven to resonance. This provides the necessary
velocity element to produce a Coriolis force during rotation. At
two of the outer extremes of each frame, orthogonal to the
dither motion, are movable fingers placed between fixed fingers to
form a capacitive pickoff structure that senses Coriolis motion.
The resulting signal is fed to a series of gain and demodulation
stages that produce the electrical rate signal output.

The base sensor output signal is sampled using an ADC, and then
the digital data is fed into a proprietary digital calibration circuit.
This circuit contains calibration coefficients from the factory
calibration, along with user-defined calibration registers that can
be used to calibrate system-level errors.

The calibrated gyroscope data (GYRO_OUT) is made available
through output data registers along with temperature, power
supply, auxiliary ADC, and relative angle output calculations.

RELATIVE ANGLE ESTIMATE

The ANGL_OUT register offers the integration of the
GYRO_OUT data. In order for this information to be useful,
the reference angle must be known. This can be accomplished
by reading the register contents at the initial time, before
starting the monitoring, or by setting its contents to zero. This
number is reset to zero when the NULL command is used, after
a RESET command is used, and during power-up. This function
can be used to estimate change in angle over a period. The user
is cautioned to fully understand the stability requirements and
the time period over which to use this estimated relative angle
position.

FACTORY CALIBRATION

The ADIS16250/ADIS16255 provide a factory calibration that
includes correction for initial tolerance and power supply
variation. In addition, the ADIS16255 provides correction for
temperature variation. This calibration includes individual
sensor characterization and custom correction coefficient
calculation.

AUXILIARY ADC FUNCTION

The auxiliary ADC function integrates a standard 12-bit ADC
into the ADIS16250/ADIS16255 to digitize other system-level
analog signals. The output of the ADC can be monitored
through the AUX_ADC control register, as defined in
The ADC is a 12-bit successive approximation converter. The
output data is presented in straight binary format with the full­scale range extending from 0 V to 2.5 V. The 2.5 V upper limit
is derived from the on-chip precision internal reference.

Figure 19 shows the equivalent circuit of the analog input
structure of the ADC. The input capacitor (C1) is typically 4 pF
and can be attributed to parasitic package capacitance. The two
diodes provide ESD protection for the analog input. Care must
be taken to ensure that the analog input signals never exceed
the range of −0.3 V to +3.5 V. This causes the diodes to become
forward-biased and to start conducting. The diodes can handle
10 mA without causing irreversible damage. The resistor is a
lumped component that represents the on resistance of the
switches. The value of this resistance is typically 100 .
Capacitor C2 represents the ADC sampling capacitor and is
typically 16 pF.

DD

D

C1

Figure 19. Equivalent Analog Input Circuit

Conversion Phase: Switch Open

D

Track Phase: Switch Closed

C2

R1

06070-005

For ac applications, it is recommended to remove high frequency
components from the analog input signal by using a low-pass
filter on the analog input pin.

In applications where harmonic distortion and signal-to-noise
ratio are critical, the analog input must be driven from a low
impedance source. Large source impedances significantly affect
the ac performance of the ADC. This can necessitate the use of
an input buffer amplifier. When no input amplifier is used to drive
the analog input, the source impedance should be limited to
values lower than 1 k.

Tabl e 6.

Rev. B | Page 10 of 20

ADIS16250/ADIS16255

BASIC OPERATION

The ADIS16250/ADIS16255 are designed for simple integration
into industrial system designs, requiring only a 5.0 V power
supply and a 4-wire, industry standard serial peripheral interface
(SPI). All outputs and user-programmable functions are
handled by a simple register structure. Each register is 16 bits in
length and has its own unique bit map. The 16 bits in each
register consist of an upper (D8 to D15) byte and a lower (D0 to
D7) byte, each of which has its own 6-bit address.

SERIAL PERIPHERAL INTERFACE (SPI)

The ADIS16250/ADIS16255 serial peripheral interface (SPI)

CS

port includes four signals: chip select (
data input (DIN), and data output (DOUT). The
enables the ADIS16250/ADIS16255 SPI port and frames each

SPI event, which consists of single or multiple data frames.
When this signal is high, the DOUT lines are in a high
impedance state and the signals on DIN and SCLK have no
impact on operation. A complete data frame contains 16 clock
cycles. Because the SPI port operates in full duplex mode, it
supports simultaneous, 16-bit receive (DIN) and transmit
(DOUT) functions during the same data frame.

Refer to Table 2,

Figure 2, and Figure 3 for detailed timing and

operation of the SPI port.

CS

), serial clock (SCLK),

CS

line

DATA FRAME

Writing to Registers

Figure 20 displays a typical data frame for writing a command
to a control register. In this case, the first bit of the DIN se­quence is a 1, followed by a 0, the 6-bit address, and the 8-bit
data command. Because each write command covers a single
byte of data, two data frames are required when writing the entire
16-bit space of a register.

Reading from Registers

Reading the contents of a register requires a modification to the
sequence in

Figure 20. In this case, the first two bits in the DIN
sequence are 0, followed by the address of the register. Each register
has two addresses (upper, lower), but either one can be used to
access its entire 16 bits of data. The final eight bits of the DIN
sequence are irrelevant and can be counted as don’t cares during a
read command. During the next data frame, the DOUT sequence
contains the register’s 16-bit data, as shown in

Figure 21.
Although a single read command requires two separate data
frames, the full duplex mode minimizes this overhead, requiring
only one extra data frame when continuously sampling.

SCL

K

DIN

W/R A5 A4 A3 A2 A1 A0 DC7 DC6 DC5 DC4 DC3 DC2 DC1 DC0

WRITE = 1

READ = 0

REGISTER ADDRESS DATA FOR WRIT E COMMANDS

Figure 20. DIN Bit Sequence

DON’T CARE FO R READ COMMANDS

06070-006

CS

SCLK

DIN

W/R BIT

DOUT

DON’T

CARE

DATA FRAME

ADDRESS DO N’T CARE NEXT COMMAND

ZERO

BASED ON PREVIO US COMMAND

Figure 21. SPI Sequence for Read Commands

DATA FRAME

16-BIT REGI STER CONT ENTS

DON’T

CARE

06070-007

Rev. B | Page 11 of 20

ADIS16250/ADIS16255

W

DATA OUTPUT REGISTER ACCESS

The ADIS16250/ADIS16255 provide access to calibrated
rotation measurements, relative angle estimates, power supply
measurements, temperature measurements, and an auxiliary
12-bit ADC channel. This output data is continuously updating
internally, regardless of user read rates. The following bit map
describes the structure of all output data registers, except
ENDURANCE, in the ADIS16250/ADIS16255.

Table 5. Register Bit Map

MSB LSB

ND EA D13 D12 D11 D10 D9 D8
D7 D6 D5 D4 D3 D2 D1 D0

Table 6. Data Output Register Information

Name Function Address Resolution (Bits) Data Format Scale Factor (per LSB)

ENDURANCE Flash Memory Write Counter 0x01, 0x00 16 Binary 1 count
SUPPLY_OUT Power Supply Data 0x03, 0x02 12 Binary 1.8315 mV
GYRO_OUT Gyroscope Data 0x05, 0x04 14 Twos Complement 0.07326°/sec
AUX_ADC Auxiliary Analog Input Data 0x0B, 0x0A 12 Binary 0.6105 mV
TEMP_OUT Sensor Temperature Data 0x0D, 0x0C 12 Twos Complement 0.1453°C
ANGL_OUT Angle Output 0x0F, 0x0E 14 Binary 0.03663°

1

Assumes that the scaling is set to 320°/sec.

Table 7. Output Coding Example, GYRO_OUT

Rate of Rotation

±320°/sec Range ±160°/sec Range ±80°/sec Range Binary Output Hex Output Decimal

600°/sec 300°/sec 150°/sec 01 1111 1111 1111 0x1FFF 8191
320°/sec 160°/sec 80°/sec 01 0001 0001 0000 0x1110 4368
80°/sec 40°/sec 20°/sec 00 0100 0100 0100 0x0444 1092
40°/sec 20°/sec 10°/sec 00 0010 0010 0010 0x0222 546

0.07326°/sec 0.03663°/sec 0.018315°/sec 00 0000 0000 0001 0x0001 1
0°/sec 0°/sec 0°/sec 00 0000 0000 0000 0x0000 0

−0.07326°/sec −0.03663°/sec −0.018315°/sec 11 1111 1111 1111 0x3FFF −1

−40°/sec −20°/sec −10°/sec 11 1101 1101 1110 0x3DDE −546

−80°/sec −40°/sec −20°/sec 11 1011 1011 1100 0x3BBC −1092

−320°/sec −160°/sec −80°/sec 10 1110 1111 0000 0x2EF0 −4368

−600°/sec −300°/sec −150°/sec 10 0000 0000 0000 0x2000 −8192

1

Two MSBs have been masked off and are not considered in the coding.

2

Nominal sensitivity and zero offset null performance are assumed.

CS

1, 2

The MSB holds the new data (ND) indicator. When the output
registers are updated with new data, the ND bit goes to a 1 state.
After the output data is read, it returns to a 0 state. The EA bit is
used to indicate a system error or an alarm condition that can
result from a number of conditions, such as a power supply that
is out of the specified operating range. See the
Diagnostics

section for more details. The output data is either

Status and

12 bits or 14 bits in length. For all of the 12-bit output data,
Bit D13 and Bit D12 are assigned don’t care status.

The output data register map is located in

Tabl e 6 and provides
all of the necessary details for accessing each register’s data.
Tabl e 7 displays the output coding for the GYRO_OUT register.
Figure 22 provides an example SPI read cycle for this register.

1

SCLK

DIN

/R BIT = 0

ADDRESS = 000101

DOUT

DATA = 1011 1101 1101 1110
NEW DATA, NO ALARM, GYRO_OU T = –40°/S ECOND

Figure 22. Example Read Cycle, ±320°/sec Setting

Rev. B | Page 12 of 20

6070-008

ADIS16250/ADIS16255

PROGRAMMING AND CONTROL

CONTROL REGISTER OVERVIEW

The ADIS16250/ADIS16255 offer many programmable features
controlled by writing commands to the appropriate control
registers using the SPI.
control registers, which controls the operation of the following
parameters:

• Calibration

• Global commands

• Operational control

• Sample rate

• Power management

• Digital filtering

• Dynamic range

• DAC output

• Digital I/O

• Operational status and diagnostics

• Self-test

• Status conditions

• Alarms

Tabl e 8 provides a summary of these

CONTROL REGISTER STRUCTURE

The ADIS16250/ADIS16255 uses a temporary, RAM-based
memory structure to facilitate the control registers displayed in
Tabl e 8 . The start-up configuration is stored in a flash memory
structure that automatically loads into the control registers
during the start-up sequence. Each nonvolatile register has a
corresponding flash memory location, for storing the latest
configuration contents. Since flash memory has endurance
limitations, the contents of each nonvolatile register must be
manually stored to flash (note that the contents of the control
register contents are only nonvolatile when they are stored to
flash). The manual flash update command, made available
in the COMMAND register, provides this function. The
ENDURANCE register provides a counter that allows for
memory reliability management against the 20,000-write cycle
specification.

Table 8. Control Register Memory Map

Register Name Type Volatility Address Bytes Function Reference Table

GYRO_OFF R/W Nonvolatile 0x15, 0x14 2 Gyroscope bias offset factor Table 9, Table 10
GYRO_SCALE R/W Nonvolatile 0x17, 0x16 2 Gyroscope scale factor Table 11, Table 12
0x18 to 0x1F 8 Reserved
ALM_MAG1 R/W Nonvolatile 0x21, 0x20 2 Alarm 1 amplitude threshold and polarity Table 31, Table 32
ALM_MAG2 R/W Nonvolatile 0x23, 0x22 2 Alarm 2 amplitude threshold and polarity Table 35, Table 36
ALM_SMPL1 R/W Nonvolatile 0x25, 0x24 2 Alarm 1 sample period Table 33, Table 34
ALM_SMPL2 R/W Nonvolatile 0x27, 0x26 2 Alarm 2 sample period Table 37, Table 38
ALM_CTRL R/W Nonvolatile 0x29, 0x28 2 Alarm control register Table 39, Table 4 0
0x2A to 0x2F 6 Reserved
AUX_DAC R/W Volatile 0x31, 0x30 2 Auxiliary DAC data Table 21, Table 22
GPIO_CTRL R/W Volatile 0x33, 0x32 2 Auxiliary digital I/O control register Table 23, Table 24
MSC_CTRL R/W Nonvolatile10x35, 0x34 2 Miscellaneous control register Table 26 , Table 27
SMPL_PRD R/W Nonvolatile 0x37, 0x36 2 ADC sample period control Table 15, Table 16
SENS/AVG R/W Nonvolatile 0x39, 0x38 2

SLP_CNT R/W Volatile 0x3B, 0x3A 2

STATUS R Volatile 0x3D, 0x3C 2 System status register Table 28, Table 29
COMMAND W N/A 0x3F, 0x3E 2 System command register Tabl e 13, Table 14

1

The contents of the upper byte are nonvolatile; the contents of the lower byte are volatile.

Defines the dynamic range (sensitivity setting)
and the number of taps for the digital filter

Counter used to determine length of power­down mode

Table 19, Table 20

Table 17, Table 18

Rev. B | Page 13 of 20

ADIS16250/ADIS16255

CALIBRATION

The ADIS16250/ADIS16255 are factory-calibrated for
sensitivity and bias. It also provides several user calibration
functions for simplifying field-level corrections. The calibra­tion factors are stored in nonvolatile memory and are applied
using the following linear calibration equation:

y = mx + b

where:

y is the calibrated output data.
x is the precalibration data.
m is the sensitivity scale factor.
b is the offset scale factor.

There are three options for system-level calibrations of the
bias in the ADIS16250/ADIS16255: auto-null, factory
calibration restore, and manual calibration updates. The
auto-null and factory reset options are described in the
Global Commands section. Optional field-level calibrations
use the preceding equation and require two steps:

1. Characterize the behavior of the ADIS16250/ADIS16255

at predefined critical operating conditions.

2. Use this characterization data to calculate and load the

contents of GYRO_OFF (b) and GYRO_SCALE (m).

The GYRO_OFF provides a calibration range of ±37.5°/sec,
and its contents are nonvolatile. The GYRO_SCALE register
provides a calibration range of 0 to 1.9995, and its contents
are also nonvolatile.

Table 9. GYRO_OFF Register Definition

Address Scale1 Default Format Access

0x15,
0x14

1

Scale is the weight of each LSB.

0.018315°/sec 0x0000

Twos
complement

Table 10. GYRO_OFF Bit Descriptions

Bit Description

15:12 Not used
11:0 Data bits

Table 11. GYRO_SCALE Register Definition

Address Scale1 Default2 Format Access

0x17, 0x16 0.0487% 0x0800 Binary R/W

1

Scale is the weight of each LSB.

2

Equates to a scale factor of one.

Table 12. GYRO_SCALE Bit Descriptions

Bit Description

15:12 Not used
11:0 Data bits

R/W

GLOBAL COMMANDS

The ADIS16250/ADIS16255 provide global commands for
common operations such as auto-null, factory calibration restore,
manual flash update, auxiliary DAC latch, and software reset. Each
of these global commands has a unique control bit assigned to it in
the COMMAND register and is initiated by writing a 1 to its
assigned bit.

The auto-null function does two things: it resets the contents of the
ANGL_OUT register to zero, and it adjusts the GYRO_OUT
register to zero. This automated adjustment takes two steps:

1. Read GYRO_OUT.

2. Write the opposite of this value into the GRYO_OFF register.

Sensor noise influences the accuracy of this step.

For optimal calibration accuracy, set the number of filtering taps to
its maximum, wait for the appropriate number of samples to
process through the filter, and then exercise this option.

The factory calibration restore command sets the contents of
GYRO_OFF to 0x0000 and GYRO_SCALE to 0x0800, erasing any
field-level calibration contents. The manual flash update writes the
contents of each nonvolatile register into flash memory for storage.
This process takes approximately 50 ms and requires the power
supply voltage to be within specification for the duration of the
event. It is worth noting that this operation also automatically
follows the auto-null and factory reset commands.

The DAC latch command loads the contents of AUX_DAC into the
DAC latches. Since the AUX_DAC contents must be updated one
byte at a time, this command ensures a stable DAC output voltage
during updates. Finally, the software reset command sends the
ADIS16250/ADIS16255 digital processor into a restart sequence,
effectively doing the same thing as the

RST

line.

Table 13. COMMAND Register Definition

Address Default Format Access

0x3F, 0x3E N/A N/A Write only

Table 14. COMMAND Bit Descriptions

Bit Description

15:8 Not used
7 Software reset command
6:4 Not used
3 Manual flash update command
2 Auxiliary DAC data latch
1 Factory calibration restore command
0 Auto-null command

OPERATIONAL CONTROL

Internal Sample Rate

The internal sample rate defines how often data output variables
are updated, independent of the rate at which they are read out on
the SPI port. The SMPL_PRD register controls the ADIS16250/
ADIS16255 internal sample rate and has two parts: a selectable

Rev. B | Page 14 of 20

ADIS16250/ADIS16255

×

×

time base and a multiplier. The sample period can be
calculated using the following equation:

= TB × (NS + 1)

T

S

where:

is the sample period.

T

S

T

is the time base.

B

is the increment setting.

N

S

The default value is the maximum 256 samples per second,
and the contents of this register are nonvolatile.

Table 15. SMPL_PRD Register Definition

Address Default Format Access

0x37, 0x36 0x0001 N/A R/W

Table 16. SMPL_PRD Bit Descriptions

Bit Description

15:8 Not used
7 Time base, 0 = 1.953 ms, 1 = 60.54 ms
6:0 Multiplier

The following is an example calculation of the sample period
for the ADIS16250/ADIS16255:

If SMPL_PRD = 0x0007, B7…B0 = 00000111

B7 = 0  T

B6…B0 = 000000111  N

T

= TB × (NS + 1) = 1.953 ms × (7 + 1) = 15.624 ms

S

f

= 1TS = 64 SPS

S

= 1.953 ms

B

= 7

S

The sample rate setting has a direct impact on the SPI data
rate capability. For sample rates of 64 SPS and above, the SPI
SCLK can run at a rate up to 2.5 MHz. For sample rates
below 64 SPS, the SPI SCLK can run at a rate up to 1 MHz.

The sample rate setting also affects the power dissipation.
When the sample rate is set below 64 SPS, the power
dissipation reduces by a factor of 60%. The two different
modes of operation offer a system-level trade-off between
performance (sample rate, serial transfer rate) and power
dissipation.

Power Management

In addition to offering two different performance modes for
power optimization, the ADIS16250/ADIS16255 offer a
programmable shutdown period. Writing the appropriate
sleep time to the SLP_CNT register shuts the device down
for the specified time. The following example provides an
illustration of this relationship:

B7 … B0 = 00000110

Sleep period = 3 sec

After completing the sleep period, the ADIS16250/ADIS16255
return to normal operation. If measurements are required
before sleep period completion, the ADIS16250/ADIS16255
can be awakened by putting the

CS

line in a zero logic state.

Otherwise, the
sleep mode.

Table 17. SLP_CNT Register Definition

Address Scale1 Default Format Access

0x3B, 0x3A 0.5 sec 0x0000 Binary R/W

1

Scale is the weight of each LSB.

Table 18. SLP_CNT Bit Descriptions

Bit Description

15:8 Not used
7:0 Data bits

Analog Bandwidth

The analog bandwidth of the ADIS16250/ADIS16255 is 50 Hz.
This bandwidth can be reduced by placing an external capacitor
across the RATE and FILT pins. In this case, the analog bandwidth
can be calculated using the following equation:

f

where:

= 45.22 kΩ.

R

OUT

C

is the external capacitance.

OUT

Digital Filtering

The ADIS16250/ADIS16255 GYRO_OUT signal path has a nominal
analog bandwidth of 50 Hz. The ADIS16250 provides a Bartlett
Window FIR filter for additional noise reduction on all of the output
data registers. The SENS/AVG register stores the number of taps in
this filter in seven power-of-two step sizes (that is, 2
32, 64, and 128). Filter setup requires one simple step: write the
appropriate M factor to the assigned bits in the SENS/AVG register.
The bit assignments are listed in
offers a frequency response relationship for this filter:

Rev. B | Page 15 of 20

OUT

B

MAGNITUDE (d B)

CS

line must be kept high to maintain

= 1/(2 × π × R

OUT

× (C

+ 0.068 µF))

OUT

M

= 1, 2, 4, 16,

Tabl e 20 . The following equation

2

0

–20

–40

–60

–80

–100

–120

–140

–160

0.001 0.01 0. 1 1

Figure 23. Bartlett Window FIR Frequency Response

N = 128

)()()(

fHfHfH

=⇒=

AA

N = 16

FREQUENCY (f/ fs)

×π

N = 4

tfN

tfN

××π×

N = 2

)sin(

S

)sin(

S

06070-009

ADIS16250/ADIS16255

Dynamic Range

The ADIS16250/ADIS16255 provide three dynamic range
settings: ±80°/sec, ±160°/sec, and ±320°/sec. The lower
dynamic range settings (80, 160) limit the minimum filter
tap sizes in order to maintain the resolution as the maximum
rate measurements decrease. The recommended order for
programming the SENS/AVG register is (1) dynamic range
and then (2) filtering response. The contents of the
SENS/AVG register are nonvolatile.

Table 19. SENS/AVG Register Definition

Address Default Format Access

0x39, 0x38 0x0402 Binary R/W

Table 20. SENS/AVG Bit Descriptions

Bit Value Description

15:11 Not used
10:8 Sensitivity selection bits
100 320°/sec (default condition)
010 160°/sec, filter taps ≥ 4 (Bits[3:0] ≥ 0x02)
001 80°/sec, filter taps ≥16 (Bits[3:0] ≥ 0x04)
7:4 Not used
3:0 Filter tap setting, M = binary number

(number of taps, N = 2

M

)

Auxiliary DAC

The auxiliary DAC provides a 12-bit level adjustment
function. The AUX_DAC register controls the operation of
this feature. It offers a rail-to-rail buffered output that has a
range of 0 V to 2.5 V. The DAC can drive its output to within
5 mV of the ground reference when it is not sinking current.
As the output approaches ground, the linearity begins to
degrade (100 LSB beginning point). As the sink current
increases, the nonlinear range increases. The DAC output
latch function, contained in the COMMAND register,
provides continuous operation while writing each byte of
this register. The contents of this register are volatile, which
means that the desired output level must be set after every
reset and power cycle event.

Table 21. AUX_DAC Register Definition

Address Default Format Access

0x31, 0x30 0x0000 Binary R/W

General-Purpose I/O

The ADIS16250/ADIS16255 provide two general-purpose pins
that enable digital I/O control using the SPI. The GPIO_CTRL
control register establishes the configuration of these pins and
handles the SPI-to-pin controls. Each pin provides the flexibility of
both input (read) and output (write) operations. For example,
writing a 0x0202 to this register establishes Line 0 as an output and
sets its level as a one. Writing 0x0000 to this register establishes both
lines as inputs, and their status can be read through Bit 0 and Bit 1
of this register.

The digital I/O lines are also available for data-ready and alarm/error
indications. In the event of conflict, the following priority structure
governs the digital I/O configuration:

MSC_CTRL

1.

ALM_CTRL

2.

GPIO_CTRL

3.

Table 23. GPIO_CTRL Register Definition

Address Default Format Access

0x33, 0x32 0x0000 N/A R/W

Table 24. GPIO_CTRL Bit Descriptions

Bit Description

15:10 Not used
9 General-purpose I/O Line 1 polarity

1 = high
0 = low

8 General-purpose I/O Line 0 polarity

1 = high

0 = low
7:2 Not used
1 General-purpose I/O Line 1, data direction control

1 = output

0 = input
0 General-purpose I/O Line 0, data direction control

1 = output

0 = input

STATUS AND DIAGNOSTICS

The ADIS16250/ADIS16255 provide a number of status and
diagnostic functions.
functions, along with their appropriate control registers.

Tabl e 25 provides a summary of these

Table 22. AUX_DAC Bit Descriptions

Bit Description

15:12 Not used
11:0 Data bits

Table 25. Status and Diagnostic Functions

Function Register

Data-ready I/O indicator MSC_CTRL
Self-test, mechanical check for MEMS sensor MSC_CTRL
Status, check for predefined error conditions STATUS
Flash memory endurance ENDURANCE
Alarms, configure and check for user-

specific conditions

Rev. B | Page 16 of 20

ALM_MAG1/2
ALM_SMPL1/2
ALM_CTRL

ADIS16250/ADIS16255

Data-Ready I/O Indicator

The data-ready function provides an indication of updated
output data. The MSC_CTRL register provides the opportu­nity to configure either of the general-purpose I/O pins (DIO0
and DIO1) as a data-ready indicator signal. After each output
register update, the digital I/O changes states, then returns to its
original state, creating a pulsed waveform. The duty cycle of that
waveform is in between 15% and 35%.

Table 26. MSC_CTRL Register Definition

Address Default Format Access

0x35, 0x34 0x0000 N/A R/W

Table 27. MSC_CTRL Bit Descriptions

Bit Description

15:11 Not used
10 Internal self-test enable

1 = enabled
0 = disabled

9 External negative rotation self-test enable

1 = enabled
0 = disabled

8 External positive rotation self-test enable

1 = enabled

0 = disabled
7:3 Not used
2 Data-ready enable

1 = enabled

0 = disabled
1 Data-ready polarity

1 = active high

0 = active low
0 Data-ready line select

1 = DIO1

0 = DIO0

Self-Test

The MSC_CTRL register also provides a self-test function,
which verifies the MEMS sensor’s mechanical integrity.
There are two different self-test options: (1) internal self-test
and (2) external self-test. The internal test provides a simple,
two-step process for checking the MEMS sensor: (1) start
the process by writing a 1 to Bit 10 in the MSC_CTRL
register and (2) check the result by reading Bit 5 of the
STATUS register, after 35 ms.

The external self-test is a static condition that can be enabled
and disabled. In this test, both positive and negative MEMS
sensor movements are available. After writing to the appropri­ate control bit, the GYRO_OUT register reflects the changes
after a delay that reflects the sensor signal chain response
time. For example, the standard 52 Hz bandwidth reflects an
exponential response with a time constant of 3.2 ms. If the

bandwidth is reduced externally (capacitor across RATE and FILT)
or internally (increasing the number of filter taps, SENS/AVG), this
time constant increases. For the internal self-test option, increasing
the delay can produce false alarms, since the internal timing for
this function is optimized for maximum bandwidth. The appropri­ate bit definitions for self-test are listed in Table 26 and Table 27.

Status Conditions

The STATUS register contains the following error-condition flags:
Alarm conditions, self-test status, angular rate over range, SPI
communication failure, control register update failure, and power
supply out of range. See Table 28 and Table 29 for the appropriate
register access and bit assignment for each flag.

The bits assigned for checking power supply range and angular rate
over range automatically reset to 0 when the error condition no
longer exists. The remaining error-flag bits in the STATUS register
require a read in order to return them to 0. Note that a STATUS
register read clears all of the bits to 0.

Table 28. STATUS Register Definition

Address Default Format Access

0x3D, 0x3C 0x0000 N/A Read-only

Table 29. STATUS Bit Descriptions

Bit Description

15:10 Not used
9 Alarm 2 status

1 = active
0 = inactive

8 Alarm 1 status

1 = active

0 = inactive
7:6 Not used
5 Self-test diagnostic error flag

1 = error condition

0 = normal operation
4 Angular rate over range

1 = error condition

0 = normal operation
3 SPI communications failure

1 = error condition

0 = normal operation
2 Control register update failed

1 = error condition

0 = normal operation
1 Power supply above 5.25 V

1 = above 5.25 V

0 = below 5.25 V (normal)
0 Power supply below 4.75 V

1 = below 4.75 V

0 = above 4.75 V (normal)

Rev. B | Page 17 of 20

ADIS16250/ADIS16255

Flash Memory Endurance

The ENDURANCE register maintains a running count of
writes to the flash memory. It provides up to 32,768 counts.
Note that if this count is exceeded, the register wraps around,
and goes back to zero, before beginning to increment again.

Table 30. ENDURANCE Register Definition

Address Default Format Access

0x01, 0x00 N/A Binary Read-only

Table 31. ALM_MAG1 Register Definition

Address Default Format Access

0x21, 0x20 0x0000 N/A R/W

Table 32. ALM_MAG1 Bit Descriptions

Bit Description

15 Comparison polarity: 1 = greater than, 0 = less than
14 Not used
13:0 Data bits: format matches source data format

Alarms

The ADIS16250/ADIS16255 provide two independent alarm
options for event detection. Event detections occur when
output register data meets the configured conditions.
Configuration options are:

•

All output data registers are available for monitoring as

the source data.

The source data can be filtered or unfiltered.

•

Comparisons can be static or dynamic (rate of change).

•

The threshold levels and times are configurable.

•

Comparison can be greater than or less than.

•

The ALM_MAG1 register and the ALM_MAG2 register both
establish the threshold level for detecting events. They take on
the format of the source data and provide a bit for establishing
the greater than/less than comparison direction. When making
dynamic comparisons, the ALM_SMPL1 register and the
ALM_SMPL2 register establish the number of averages taken
for the source data as a reference for comparison. In this con­figuration, each subsequent source data sample is subtracted
from the previous one, establishing an instantaneous delta. The
ALM_CTRL register controls the source data selection,
static/dynamic selection, filtering selection, and digital I/O
usage for the alarms.

The rate of change calculation is

N

DS

1

Y

C

∑

N

1

n

=

DS

)()1(

nyny

−+=

?oris

MYalarmchangeofRate

<>⇒

CC

where:

N

is the number of samples in ALM_SMPL1/2.

DS

y(n) is the sampled output data.

is the magnitude for comparison in ALM_MAG1/2.

M

C

is the factor to be compared with MC.

Y

C

> or < is determined by the MSB in ALM_MAG1/2.

Table 33. ALM_SMPL1 Register Definition

Address Default Format Access

0x25, 0x24 0x0000 Binary R/W

Table 34. ALM_SMPL1 Bit Descriptions

Bit Description

15:8 Not used
7:0 Data bits

Table 35. ALM_MAG2 Register Definition

Address Default Format Access

0x23, 0x22 0x0000 N/A R/W

Table 36. ALM_MAG2 Bit Descriptions

Bit Description

15 Comparison polarity

1 = greater than

0 = less than
14 Not used
13:0 Data bits: format matches source data format

Table 37. ALM_SMPL2 Register Definition

Address Default Format Access

0x27, 0x26 0x0000 Binary R/W

Table 38. ALM_SMPL2 Bit Designations

Bit Description

15:8 Not used
7:0 Data bits

Table 39. ALM_CTRL Register Definition

Address Default Format Access

0x29, 0x28 0x0000 N/A R/W

Rev. B | Page 18 of 20

ADIS16250/ADIS16255

Table 40. ALM_CTRL Bit Descriptions

Bit Value Description

15 Rate of change (ROC) enable for Alarm 2

1 = rate of change

0 = static level
14:12 Alarm 2 source selection
000 Disable
001 Power supply output
010 Gyroscope output
011 Inactive
100 Inactive
101 Auxiliary ADC output
110 Temperature sensor output
111 Inactive
11 Rate of change (ROC) enable for Alarm 1

1 = rate of change

0 = static level
10:8 Alarm 1 source selection
000 Disable
001 Power supply output
010 Gyroscope output
011 Inactive
100 Inactive
101 Auxiliary ADC output
110 Temperature sensor output
111 Inactive
7:5 Not used
4 Filtered data comparison

1 = filtered data

0 = unfiltered data
3 Not used
2 Alarm output enable

1 = enabled

0 = disabled
1 Alarm output polarity

1 = active high

0 = active low
0 Alarm output line select

1 = DIO1

0 = DIO0

Rev. B | Page 19 of 20

ADIS16250/ADIS16255

OUTLINE DIMENSIONS

7.600
BSC

(4×)

BOTTOM VIEW

1

5

610

11.1 5
MAX

TOP VIEW

7.00
TYP

SIDE VIEW

11.0 0
TYP

5.50

MAX

10.173
BSC

(2×)

0.200
MIN

(ALL SIDES)

3.800
BSC

(8×)

16 20

15

11

Figure 24. 20-Terminal Stacked Land Grid Array [LGA]

(CC-20-1)

Dimensions shown in millimeters

ORDERING GUIDE

Model Temperature Range Package Description Package Option

ADIS16250ACCZ
ADIS16255ACCZ
ADIS16250/PCBZ
ADIS16255/PCBZ

1

Z = RoHS Compliant Part.

1

1

1

1

−40°C to +85°C 20-Terminal Stacked Land Grid Array [LGA] CC-20-1

−40°C to +85°C 20-Terminal Stacked Land Grid Array [LGA] CC-20-1
Evaluation Board for the ADIS16250
Evaluation Board for the ADIS16255

PIN 1
INDICATOR

1.000 BSC
(20×)

0.900 BSC
(16×)

0.373 BSC
(20×)

022007-B

©2006–2007 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06070-0-3/07(B)

Rev. B | Page 20 of 20