TCM8230MD (A) Ver. 1.20
TOSHIBA CMOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC
TCM8230MD (A)
TENTATIVE
VGA CAMERA MODULE
The TCM8230MD(A) is a camera module which includes area color image sensor embedded with camera signal
processor that meets with VGA format. In the sensor area 492 vertical and 660 horizontal signal pixels, and the image
size meets with 1/6 inch optical Format. Use of the CMOS process enables low power consumption operations. It
also provides excellent color reproduction through its primary color filter, and embedded camera signal processor
enables small and simple camera system. And this module can be assembled by the socket which is suitable for the
reflow soldering. So it is fit to use as an image input device for digital still cameras, PC cameras and mobile devices.
Features
1. General
• Module size : 6(W) x 6(D) x 4.5(H) mm
2
C BUS I/F
• I
• Sleep mode operation (It can be controlled by the I
• Power supply : 2.8+/-0.2V or 2.5+/-0.2V (Sensor(photo diode), I/O) and 1.5+/-0.1V(Sensor(A/D converter), Digital)
2
C Bus command)
2. Sensor
• Optical size : 1/6 inch optical format
• Total pixel numbers : 698(H)x502(V)
• Signal pixel numbers : 660(H)x492(V)
• Pixel pitch : 3.75um(H)x3.75um(V) (square pixel)
• Color filter : RGB color filter, Bayer arrangement (GR line and GB line are arranged alternately.)
• Frame rate : Max 30fps
• Raw data bit precision : 10bit
• Feed back clamp
3. Camera signal processing
• Maximum exposure time can be adjust from 1V to 15V
• Digital outputs
YUV=4:2:2 or RGB=5:6:5 ( 8bit parallel output )
• Picture size
VGA, QVGA, QQVGA, CIF, QCIF, subQCIF ( Sub-sampling , Windowing )
• Readout internal parameters
Sensor gain setting, Electrical shutter exposure period, ALC and AWB reference value
• Auto electrical shutter control (AES), auto gain control (AGC) and auto white balance (AWB) circuit
• Flickerless auto luminance control (ALC=AES+AGC) and auto flicker detection circuit for AC 50Hz / 60Hz fluorescent light
• Automatically blemish correction
• Vertical and Horizontal flip mode
TOSHIBA is continually working t o improve the qua lity and the rel i abili ty of its products. N evertheless, semiconductor devic es in general can malfunct i on or
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jail due to their inherent electrical sensitivity a nd vulner ability to physical stress. It is the responsibili ty of the buyer, when util i zing TO SHIBA products , to
observe standards of safety, and to avoid situations in which a malfunct i on or failure of a TOSHIBA product could cause loss of human life, bodily inj ur y or
damage to propert y. In developing your des igns, pl ease ensure that TOSHIBA products are used w ithi n spe cified oper ating range as se t for th in the mos t
rec ent product s sp ecif ications. Also, please keep i n m ind t he pr e caut ions and condi tions se t f orth in the TOSHI BA Semiconduct or Reliab ility Handb ook.
The products de scr ibed in this documen t are subject to foreign exchange and f orei gn trade control l aws.
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The information contained herein is presented only as a guide for the applications of our products. No responsibili ty is assumed by TOSHIBA
●
CORPORAT ION f or any in fri ngemen ts o f int ell ect ual pr oper ty or ot her r ig hts o f the t hir d pa rti es whic h may r esul t fr om it s use. No l ice nse is gran ted by
implication or other wise u nder any intell ect ua l property or other righ ts of TOSHIBA CORPORATION or others.
The information contained herein is subj ect to c hange wit hout notice.
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04/01/05 1/27
UPDATE INFORMATION
Ver. 1.20 Jan-05, 2004
Ver. 1.10 Dec-23, 2003
Ver. 1.09 Dec-16, 2003
Ver. 1.08 Oct-29, 2003
Ver. 1.07 Oct-07, 2003
Ver. 1.06 Sep-19, 2003
Ver. 1.05 Sep-08, 2003
Ver. 1.04 Aug-11, 2003
Ver. 1.03 Jul-31, 2003
Ver. 1.02 Jul-16, 2003
Ver. 1.01 Jul-03, 2003
Ver. 1.00 Jun-25, 2003
TCM8230MD (A) Ver. 1.20
04/01/05 2/27
BLOCK DIAGRAM
VGA CMOS Sensor
Image
Area
TCM8230MD (A) Ver. 1.20
Double Lens
CDS / AGC ADC
TCM8230MD
TG / S G
Signal
Processing
AWB ALC
I2C bus I/F
PVDD
IOV DD
(2.8V )
IOVSS
SDA
SCL
Host system
CDS : Correlated Do uble Sampling
AGC : Automatic Gain Control
ADC : Analog to Degital Converter
TG : Timing pulse Generator
SG : Sync pulse Generator
AWB : Auto Whi te Balance
ALC : Auto Luminance Control
Connecting terminals
HD
VD
EXTCLK
RESET
DVDD
(1.5V)
DVSS
AVSS
DOUT0
to
DOUT7
DCLK
04/01/05 3/27
PIN FUNCTIONS
TCM8230MD (A) Ver. 1.20
No. NAME I/O FUNCTION
1 PVDD - VDD for sensor (photo diode) ( 2.8V )
2 EXTCLK I Clock for external input
3 RESET I RESET terminal ("L" active)
4SCL I
5SDAI/O
Clock for I
Data for I
2
C-bus command
2
C-bus command
6DVDD -
VDD for digital circuits, (1.5V )
VDD for sensor (A/D converter) (1.5V )
GND for digital circuits
-DVSS7
GND for sensor (A/D converter)
GND for sensor (photo diode)
8 VD O Vertical syncronization pulse output
9 HD O Holizontal syncronization pulse output
10 DCLK O Clock for output data
11 DOUT0 O Data output (LSB)
12 DOUT1 O Data output
13 DOUT2 O Data output
14 DOUT3 O Data output
15 IOV SS - GND for I/O
16 IOVDD - VDD for I/O ( 2.8V )
17 DOUT4 O Data output
18 DOUT5 O Data output
19 DOUT6 O Data output
20 DOUT7 O Data output (MSB)
04/01/05 5/27
INTERFACE CIRCUITS
TCM8230MD (A) Ver. 1.20
PIN No.
2
3
NAME I/O INTERFACE CIRCUIT
IOVDD
IOVDD IOVDD
EXTCLK I
GND
IOVDD
GND
IOVDD IOVDD
GND
IOVDD
RESET
("L" active)
GND
I
GND
GND
IOVDD
GND
4
5
8-14,
17-20
SCL I
SDA I/O
DOUT0 to DOUT7,
HD, VD, DCLK
GND
GND
IOVDD
GND
GND GND
IOVDD IOVDD
O
GND GND
04/01/05 6/27
PIXEL ARRANGEMENT
1. V_INV=0
Dummypixels OB44pixels Signalpixels 660pixels
492
491
490
489
488
487
Vertical
6
5
4
3
2
1
TCM8230MD (A) Ver. 1.20
Lightshieldedpi xel s
2pixels
B G
B G
B G
B G
r
B G
r
B G
r
B G
r
b
b
RG
RG
r
r
B G
B G
b
b
RG
RG
r
r
B G
B G
b
b
RG
RG
r
r
B G
B G
b
b
RG
RG
r
r
B G
b
b
RG
B G
b
RG
B G
b
RG
B G
b
RG
b
RG
RG
r
r
B G
b
b
RG
RG
r
r
B G
b
b
RG
RG
r
r
B G
b
b
RG
RG
r
r
B G
r
B G
r
B G
r
B G
r
B G
B G
B G
b
b
RG
RG
r
r
B G
B G
b
b
RG
RG
r
r
B G
b
b
RG
B G
b
RG
b
RG
RG
r
r
B G
b
b
RG
RG
r
r
Signalpixels 494pixels
B G
B G
B G
b
b
RG
RG
r
r
B G
B G
b
b
RG
RG
r
r
B G
b
b
RG
B G
b
RG
b
RG
RG
r
r
B G
b
b
RG
RG
r
r
OB: Optical Black R: Red pixels Gr,Gb: Green pixels B: Blue pixels
2. V_INV =1 (Vertical flip mode)
Dummypixels OB44pixels Signalpixels 660pixels
1
2
3
4
5
6
Vertical
487
488
489
490
491
492
12345
Startpixel
B G
B G
b
RG
RG
r
r
B G
B G
b
RG
RG
r
r
B G
B G
b
RG
RG
r
r
B G
B G
b
RG
RG
r
r
6
HorizontalStartpixel
655
656
657
658
659
660
Lightshieldedpi xel s
2pixels
B G
B G
b
r
B G
b
r
B G
b
r
B G
b
r
B G
b
b
RG
B G
b
RG
B G
b
RG
B G
b
RG
b
RG
RG
r
r
B G
b
b
RG
RG
r
r
B G
b
b
RG
RG
r
r
B G
b
b
RG
RG
r
r
B G
r
B G
r
B G
r
B G
r
B G
B G
B G
b
b
RG
RG
r
r
B G
B G
b
b
RG
RG
r
r
B G
b
b
RG
B G
b
RG
b
RG
RG
r
r
B G
b
b
RG
RG
r
r
Signalpixels 494pixels
B G
B G
B G
b
b
RG
RG
r
r
B G
B G
b
b
RG
RG
r
r
B G
b
b
RG
B G
b
RG
b
RG
RG
r
r
B G
b
b
RG
RG
r
r
12345
6
Horizontal
655
656
657
658
659
660
OB: Optical Black R: Red pixels Gr,Gb: Green pixels B: Blue pixels
04/01/05 7/27
TCM8230MD (A) Ver. 1.20
CONTROL I/F
TCM8230MD(A) control interface configuration is based on fast mode I2C bus.
Register setting can be changed via I
All register settings are able to read via I
2
C bus.
2
C bus.
Write mode
Slave AddressS 0 A Sub Address A Data 1 Data n A P
MSB 7bit 8bit 8bit 8bit
A
Read mode
Slave AddressS 0 A Sub Address A Data 1 Data n A P
MSB 7bit 8bit 8bit 8bit
: Host Command
: TCM8230MD(A)
S
P
A
Slave AddressS 1
MSB 7bit
: Start condition
: End condition
: Acknowledge
A
Start condition, End condition Bit Transfer
SDA
SDA
SCL
SP
Startcondition Endconditon
SCL
datalinestable;
datavalid
changeofdataallowed
Acknowledge Slave address
SDA
fromtrancemitter
SDA
from reciver
* TCM8230MD(A) use 7bit Slave address
HiZ
HiZ
A6 A5 A4 A3 A2 A1 A0 R/W
01111001/0
SCL
from master
S
189
Purchase of TOSHIBA I2C components conveys a license under the Philips I2C Patent Rights to use these
components in an I
defined by Philips.
2
C system, provided that the system conforms to the I2C Standard Specification as
04/01/05 8/27
TCM8230MD (A) Ver. 1.20
INTERNAL REGISTER
ADDRESS fast last
DEC BIN HEX
BIT7(MSB) BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0(LSB)
0 0000000000 01110000
1 0000000101 0001 0000
2 0000001002
3 0000001103
4 0000010004
5 0000010105
6 0000011006
7 0000011107 11
8 0000100008
9 0000100109
Test Mode
FPS
0:30fps
1:15fps
DOUTSW
0:ON
1:0FF
V_INV
0:normal
1:invert
ALCSW
0:AUTO
1:MANUAL
ESRSPD
[7:0]
AG
[7:0]
ALCL
ACF
0:50Hz
1:60Hz
DATAH Z
0:OUT
1:Hi-Z
H_INV
0:normal
1:invert
ESRLIM
[7:0]
0h:VGA 1h:QVGA(f) 2h:QVGA(z)
[3:0]
PICSIZ
3h:QQVGA(f) 4h:QQVGA(z) 5h:CIF(f)
6h:QCIF(f) 7h:QCIF(z) 8h:subQCIF(f)
9h:subQCIF(z)
ESRLSW[1:0]
0h : Short 1h :
2h & 3h :
Lon
[1:0]
ALCMODE
0h:Centaer Wei ght
1h:Average
2h:Center only
3h:Backlight
ESRSPD
[1:0]
V_LENGTH
[12:8]
ALCH
[3:0]
[3:0]
DCLKP
0 : normal
1: reverse
PICFMT
0:YUV422
1:RGB565
ACFDET
0 : AUTO
1: MANUAL
CM
0:COLOR
1:B/W
AWBSW
10 000010100A
11 000010110B
12 000011000C
0:AUTO
1:MANUAL
[7:0]
MRG
[7:0]
MBG
GAMSW
13 000011010D
14 000011100E
15 000011110F
16 0001000010
17 0001000111
18 0001001012 0
19 0001001113 0
20 0001010014 00
21 0001010115
22 0001011016
23 0001011117
24 0001100018
25 0001100119
26 000110101A 00100000
0:ON
1:OFF
[7:0]
HDTG
[7:0]
VDTG
HDTCORE
[7:0]
CONT
[7:0]
BRIGHT
MHMODE
0:
1:
[3:0]
[6:0]
VHUE
[6:0]
UHUE
[6:0]
SATU
MHLPFSE
L
0:
1:
VGAIN
UGAIN
YMODE
[5:0]
LENS
[5:0]
[5:0]
[1:0]
VDTCORE
UVCORE
[3:0]
[3:0]
MIXHG
[2:0]
default(ROM data)
B7B6B5 B4 B3B2B1B0
1100 0
10
0
0000 1111
0000 0010
0000 1101
00 0000
0011 1000
0
1000000
0
0000000
0100 0000
0
1000000
000
0010 1111
0000 0100
0010 0010
1001 1010
0001100
0001010
00 1000
0011 1000
0011 1000
0000 0001
0010 0111
00000100
000
00000
00000
HEX
70
10
40
80
0F
02
0D
C0
38
40
00
40
40
00
2F
04
22
9A
0C
0A
08
38
38
01
27
04
20
0:Gain
27 000110111B
28 000111001C
29 000111011D
30 000111101E
31 000111111F
AGLIM
ES100S
ES120S
D_MASK
SLEEPSW
0:ACTIVE
1:SLEEP
[2:0]
[7:0]
[7:0]
[1:0]
CODESW
0:OFF
1:OUT
SRST
0:OFF
1:reset
L
up
1:Gain
CODESEL
0 : original
1 : ITU656
LENSRGAIN
HSYNCSEL
0 : normal
1 :
[3:0]
TESPIC
0:Not out
1:Out
[1:0]
PICSEL
0h:Colorbar 1h:Ramp1
2h :Ramp2
01000110
1001 1110
1000 0011
01101000
00000000
The registers of gray mesh (unassigned registers) are not defined. Input data of the registers of gray mesh
must input “0”. The registers of testmode must input default data.
04/01/05 9/27
46
9E
83
68
00