Rainbow Electronics CLC5957 User Manual
April 2002
CLC5957
12-Bit, 70 MSPS Broadband Monolithic A/D Converter
CLC5957 12-Bit, 70 MSPS Broadband Monolithic A/D Converter
General Description
The CLC5957 is a monolithic 12-bit, 70MSPS analog-todigital converter. The device has been optimized for use in
IF-sampled digital receivers and other applications where
high resolution, high sampling rate, wide dynamic range, low
power dissipation, and compact size are required. The
CLC5957 features differential analog inputs, low jitter differential universal clock inputs, a low distortion track-and-hold
with 0-300MHz input bandwidth, a bandgap voltage reference, data valid clock output, TTL compatible CMOS (3.3V
or 2.5V) programmable output logic, and a proprietary 12-bit
multi-stage quantizer. The CLC5957 is fabricated on the
ABIC-V 0.8 micron BiCMOS process.
The CLC5957 features a 74dBc spurious free dynamic
range (SFDR) and a 67dB signal to noise ratio (SNR). The
wideband track-and-hold allows sampling of IF signals to
greater than 250MHz. The part produces two-tone, dithered,
SFDR of 83dBFS at 75MHz input frequency. The differential
analog input provides excellent common mode rejection,
while the differential universal clock inputs minimize jitter.
The 48-pin TSSOP package provides an extremely small
footprint for applications where space is a critical consideration. The CLC5957 operates from a single +5V power
supply. Operation over the industrial temperature range of
-40˚C to +85˚C is guaranteed. National Semiconductor tests
each part to verify compliance with the guaranteed specifications.
Features
n 70MSPS
n Wide dynamic range:
— SFDR: 74dBc
— SFDR with dither: 85dBFS
— SNR: 67dB
n IF sampling capability
n Input bandwidth = 0-300MHz
n Low power dissipation: 640mW
n Very small package: 48-pin TSSOP
n Single +5V supply
n Data valid clock output
n Programmable output levels: 3.3V or 2.5V
Applications
n Cellular base stations
n Digital communications
n Infrared/CCD imaging
n IF sampling
n Electro-optics
n Instrumentation
n Medical imaging
n High definition video
01502928
Block Diagram
01502902
© 2002 National Semiconductor Corporation DS015029 www.national.com
Pin Configuration
CLC5957
01502901
Ordering Information
CLC5957MTD 48-Pin TSSOP
CLC5957MTDX 48-Pin TSSOP (Taped
Reel)
CLC5957PCASM Evaluation Board
Pin Descriptions
Pin
Name
A
IN
A
IN
ENCODE
ENCODE
V
CM
D0–D11
GND
+AV
+DV
CC
CC
1–4, 8, 11, 12, 15, 19,
20, 23–26, 35, 36, 47, 48
NC 29 No connect. May be left open or grounded.
DAV 27
OUTLEV 28 Output Logic 3.3V or 2.5V option. Open = 3.3V, GND = 2.5V.
Pin
No.
13, 14
9, 10
21
30–34,
39–45
5–7, 16–18, 22
37, 38, 46
Description
Differential input with a common mode voltage of +2.4V. The ADC
full scale input is 1.024 VPPon each of the complimentary input
signals.
Differential clock where ENCODE initiates a new data conversion
cycle on each rising edge. Logic for these inputs are a 50% duty
>
cycle universal differential signal (
internally biased to V
/2 with a termination impedance of 2.5kΩ.
CC
200mV). The clock input is
Internal common mode voltage reference. Nominally +2.4V. Can be
used for the input common mode voltage. This voltage is derived
from an internal bandgap reference. V
should be buffered when
CM
driving any external load. Failure to buffer this signal can cause
errors in the internal bias currents.
Digital data outputs are CMOS and TTL compatible. D0 is the LSB
and D11 is the MSB. MSB is inverted. Output coding is two’s
complement. Current limited to source/sink 2.5mA typical.
Circuit ground.
+5V power supply for the analog section. Bypass to ground with a
0.1 µF capacitor.
+5V power supply for the digital section. Bypass to ground with a
0.1 µF capacitor.
Data Valid Clock. Data is valid on rising edge. Current limited to
source/sink 5mA typical.
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CLC5957
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
Recommended Operating Conditions
please contact the NationalSemiconductorSales Office/
Distributors for availability and specifications.
Positive Supply Voltage (V
) −0.5V to +6V
CC
Differential Voltage between any two
<
100 mV
Positive Supply Voltage (VCC) +5V±5%
Analog Input Voltage Range 2.048 V
PP
Operating Temperature Range −40˚C to +85˚C
Grounds
Analog Input Voltage Range GND to V
Digital Input Voltage Range −0.5V to +V
Output Short Circuit Duration
CC
CC
Package Thermal Resistance (Note 7)
Package θ
JA
48-Pin TSSOP 56˚C/W 16˚C/W
θ
JC
(one-pin to ground) Infinite
Junction Temperature (Note 7) 175˚C
Storage Temperature Range −65˚C to +150˚C
Lead Solder Duration (+300˚C) 10 sec.
Reliability Information
Transistor Count 5000
ESD tolerance
human body model
machine model
2000V
200V
Converter Electrical Characteristics
The following specifications apply for AVCC=DVCC= +5V, 66MSPS. Boldface limits apply for TA=T
+85˚C, all other limits T
= 25˚C (Note 3).
A
Symbol Parameter Conditions Min Typ Max Units
DYNAMIC PERFORMANCE
BW Large-Signal Bandwidth A
Overvoltage Recovery Time A
t
A
t
AJ
Effective Aperture Delay −0.41 ns
Aperture Jitter 0.3 ps(rms)
= −3 dBFS 300 MHz
IN
= 1.5 FS (0.01%) 12 ns
IN
NOISE AND DISTORTION
= 5 MHz, AIN= −1dBFS 67 dBFS
f
IN
SNR
*
(Note 2)
SFDR
IMD
Signal-to-Noise Ratio (without 50
harmonics)
Spurious-Free Dynamic Range
Spurious-Free Dynamic Range
(dithered)
Intermodulation Distortion
Intermodulation Distortion (dithered)
f
= 25 MHz, AIN= −1dBFS
IN
f
= 75 MHz, AIN= −3dBFS 65 dBFS
IN
f
= 150 MHz, AIN= −15dBFS 66 dBFS
IN
f
= 250 MHz, AIN= −15dBFS 66 dBFS
IN
f
= 5 MHz, AIN= −1dBFS 74 dBc
IN
f
= 25 MHz, AIN= −1dBFS
IN
f
= 75 MHz, AIN= −3dBFS 72 dBc
IN
f
= 150 MHz, AIN= −15dBFS 69 dBc
IN
f
= 250 MHz, AIN= −15dBFS 65 dBc
IN
= 19 MHz, AIN= −6dBFS 85 dBFS
f
IN
= 149.84 MHz, f
f
IN1
MHz, A
f
IN1
MHz, A
f
IN1
A
IN
= −10dBFS
IN
= 249.86 MHz, f
= −10dBFS
IN
= 74 MHz, f
= −12dBFS
IN2
IN2
= 75 MHz,
IN2
*
*
= 149.7
= 249.69
60 66 dBFS
60 74 dBc
68 dBFS
58 dBFS
83 dBFS
DC ACCURACY AND PERFORMANCE
DNL Differential Non-Linearity f
INL Integral Non-Linearity f
= 5MHz, AIN= −1dBFS
IN
= 5MHz, AIN= −1dBFS
IN
±
0.65 LSB
±
1.5 LSB
Offset Error (Note 2) −30 0 30 mV
Gain Error 1.2 % FS
V
REF
Reference Voltage (Note 2) 2.2 2.37 2.6 V
No Missing Codes (Note 2) f
= 5MHz, AIN= -1dBFS Guaranteed
IN
= −40˚C to T
min
max
diff.
=
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Converter Electrical Characteristics (Continued)
The following specifications apply for AVCC=DVCC= +5V, 66MSPS. Boldface limits apply for TA=T
+85˚C, all other limits T
CLC5957
= 25˚C (Note 3).
A
Symbol Parameter Conditions Min Typ Max Units
ANALOG INPUTS
V
IN
RIN(SE)
R
IN
C
IN
Analog Diff Input Voltage Range 2.048 V
Analog Input Resistance
(Single-Ended)
500 Ω
(Diff) Analog Input Resistance (Differential) 1000 Ω
Analog Input Capacitance
(Single-ended)
2pF
ENCODE INPUTS (UNIVERSAL)
V
IH
V
IL
Logic Input High Voltage (Note
4),(Note 5)
Logic Input Low Voltage(Note
4),(Note 5)
Differential Input Swing (Note
4),(Note 5)
0V
0.2 V
DIGITAL OUTPUTS
V
OL
V
OH
Logic Output Low Voltage (Note 2) 0.01 0.4 V
Logic Output High Voltage (Note 2)
OUTLEV = 1 (open) 3.2 3.5 3.8 V
OUTLEV = 0 (GND) 2.4 2.7 3.0 V
TIMING (Note 6)
t
t
t
t
t
t
t
P
M
DNV
DGV
DAV
S
H
Maximum Conversion Rate
(ENCODE) (Note 2)
Minimum Conversion Rate
(ENCODE)
Pulse Width High (ENCODE) (Note
4)
50% threshold 7.1 ns
Pulse Width Low (ENCODE) (Note 4) 50% threshold 7.1 ns
ENCODE falling edge to DATA not
valid (Note 4)
ENCODE falling edge to DATA
guaranteed valid (Note 4)
Rising ENCODE to rising DAV delay
(Note 4)
50% threshold 8.3 12.6 ns
DATA setup time before rising DAV
(Note 4)
DATA hold time after rising DAV
(Note 4)
70 75 MSPS
10 MSPS
8.3 ns
−2.4 ns
t
M
−1.6 ns
t
P
Pipeline latency 3.0 clk cycle
= −40˚C to T
min
5V
17.8 ns
max
=
PP
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Converter Electrical Characteristics (Continued)
The following specifications apply for AVCC=DVCC= +5V, 66MSPS. Boldface limits apply for TA=T
+85˚C, all other limits T
= 25˚C (Note 3).
A
Symbol Parameter Conditions Min Typ Max Units
POWER REQUIREMENTS
I
CC
Total Operating Supply Current (Note
2)
128 150 mA
Power Dissipation (Note 2) 640 750 mW
Power Supply Rejection Ratio 64 dB
Note 1: “Absolute Maximum Ratings” are limiting values, to be applied individually, and beyond which the serviceability of the circuit may be impaired. Functional
operability under any of these conditions is not necessarily implied. Exposure to maximum ratings for extended periods may affect device reliability.
Note 2: These parameters are guaranteed by test.
Note 3: Typical specifications are based on the mean test values of deliverable converters from the first three diffusion lots.
Note 4: Values guaranteed based on characterization and simulation.
Note 5: See page 14, Figure 3 for ENCODE inputs circuit.
Note 6: C
Note 7: The absolute maximum junction (T
junction-to-ambient thermal resistance (θ
TSSOP, θ
under normal operation will typically be about 650 mW (640 mW quiescent power + 10 mW due to 1 TTL load on each digital output). The values of absolute
maximum power dissipation will only be reached when the CLC5957 is operated in a severe fault condition (e.g., when input or output pins are driven beyond the
power supply voltages, or the power supply polarity is reversed). Obviously, such conditions should always be avoided.
= 7pF DATA; 10pF DAV.
L
is 56˚C/W, so PDmax = 2.68W at 25˚C and 1.6W at the maximum operating ambient temperature of 85˚C. Note that the power dissipation of this device
JA
max) temperature for this device is 175˚C. The maximum allowable power dissipation is dictated by TJmax, the
J
), and the ambient temperature (TA), and can be calculated using the formula PDmax=(TJmax – TA)/θJA. For the 48-pin
JA
= −40˚C to T
min
max
CLC5957
=
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