Rainbow Electronics CLC001 User Manual

CLC001
Serial Digital Cable Driver with Adjustable Outputs

CLC001 Serial Digital Cable Driver with Adjustable Outputs

March 2001

General Description

The CLC001 is a monolithic, high-speed cable driver
designed for use in SMPTE 259M serial digital video and
ITU-T G.703 serial digital data transmission applications.
The CLC001 drives 75Ω transmission lines (Belden 8281 or
equivalent) at data rates up to 622 Mbps. Controlled output
rise and fall times (400 ps typical) minimize transition­induced jitter. The output voltage swing is adjustable from
800 mV

The CLC001’soutput stage consumes less power than other
designs. The differential inputs accept LVDS signal levels,
LVPECL levels directly or PECL with attenuation networks.

All these make the CLC001 an excellent general purpose
high speed driver for high-speed, long distance data
transmission applications.

The CLC001 is powered from a single +3.3V supply and
comes in a small 8-pin SOIC package.

p-p

to 1.0 V

using an external resistor.

p-p

Key Specifications

n 400 ps rise and fall times
n Data rates to 622 Mbps
n 100 mV differential input threshold
n Low residual jitter

Features

n Adjustable output amplitude
n Differential input and output
n Accepts LVPECL or LVDS input swings
n Low power dissipation
n Single +3.3V supply

Applications

n Digital routers and distribution amplifiers
n Coaxial cable driver for digital transmission lines
n Twisted pair driver
n Serial digital video interfaces for the commercial and

broadcast industry

n SMPTE, Sonet/SDH, and ATM compatible driver
n Buffer applications

DS101329-10

622 Mbps Eye Pattern with STM-4 Signal Mask

Connection Diagram (8-Pin SOIC)

DS101329-2

Order Number CLC001AJE

See NS Package Number M08A

Typical Application

DS101329-1

© 2001 National Semiconductor Corporation DS101329 www.national.com

Absolute Maximum Ratings (Note 1)

If Military/Aerospace specified devices are required,

CLC001

please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.

Supply Voltage 4V
Output Current 27 mA
Maximum Junction Temperature +125˚C
Storage Temperature Range −65˚C to +150˚C
Lead Temperature

(Soldering 10 seconds) +300˚C

ESD Rating (HBM) ≥ 7kV
ESD Rating (MM) ≥ 500V
Package Thermal Resistance

Surface Mount AJE 125˚C/W

θ

JA

Surface Mount AJE 105˚C/W

θ

JC

Reliability Information

Transistor count 291

Recommended Operating
Conditions

Supply Voltage Range (VDD-VSS) +3.0V to +3.6V
Operating Free Air Temperature (T

Range (applied to VBBinput)

R

BB

(Note 6) 1.3kΩ to 11.5kΩ

) -40˚C to +85˚C

A

Electrical Characteristics

Over recommended operating supply and temperature ranges unless otherwise specified (Notes 2 and 3)

Symbol Parameter Conditions Min Typ Max Units

OUTPUT DC SPECIFICATIONS

V

SDO

INPUT DC SPECIFICATIONS

V

TH

V

TL

V

CMR

I

IN

I

INB

SUPPLY CURRENT

I

DD

MISCELLANEOUS PARAMETERS

L

GEN

R

GEN

I

BB

Serial Driver Output Voltage RL=75Ω1%,

= 1.91 kΩ 1% (for 800 mV

R

REF

),

p-p

720 800 880 mV

Figure 1

R

=75Ω1%,

L

= 1.5 kΩ 1% (for 1.0 V

R

REF

),

p-p

900 1000 1100 mV

Figure 1

Differential Input High Threshold VCM= +0.05V or +1.2V or +3.25V, 0 +100 mV
Differential Input Low Threshold VDD= 3.3V −100 0 mV
Common Mode Voltage Range VID= 100mV, VDD= 3.3V 0.05 3.25 V
Input Current VIN= 0V or +3.0V, VDD= 3.6V or 0V
Input Current Balance VIN= 0V or +3.0V, VDD= 3.6V or 0V,

±

0.23 µA

±

1

10 µA

(Note 8)

Total Dynamic Power Supply Current
(includes load current)

RL=75Ω,

= 1.91 kΩ 1%

R

REF

= 800 mV

(V

SDO

=75Ω,

R

L

= 1.5 kΩ 1%

R

REF

= 1.0 V

(V

SDO

p-p

p-p

@

270 Mbps)

@

622 Mbps)

70 115 mA

85 130 mA

Output Inductance 6nH
Output Resistance 25 kΩ
VBBCurrent R

= 1.91 kΩ 1%, (Note 6) 250 µA

REF

R

= 1.5 kΩ 1%, (Note 6) 315 µA

REF

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AC Electrical Characteristics

Over recommended operating supply and temperature ranges unless otherwise specified (Note 3)

Symbol Parameter Conditions Min Typ Max Units

t

r,tf

t

os

t

jit

t

pd

Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices
should be operated at these limits. The table of “Electrical Characteristics” specifies conditions of device operation.

Note 2: Current flow into device pins is defined as positive. Current flow out of device pins is defined as negative. All voltages are stated referenced to V
Note 3: Typical values are at 25˚C and 3.3V.
Note 4: This parameter is Guaranteed by Design.
Note 5: R
Note 6: The V

power other devices.

Note 7: R
Note 8: Input Current Balance (I

Rise time, Fall time 20%–80%, (Notes 4, 5) 400 800 ps
Output overshoot 5%
Output jitter (Note 7) 25 ps
Propagation delay (Note 5) 1.9 ns

=0V.

SS

=75Ω, AC-coupled at 270 Mbps, R

L

output is intended as a bias supply pin for the inputs of this device only. It is not designed as a power supply output and should not be used to

BB

=75Ω, AC-coupled at 622 Mbps, R

L

) is the difference between the Input Current (IIN)onV

INB

= 1.91 kΩ 1% (for V

REF

= 1.5 kΩ 1% (for V

REF

SDO

SDO

= 800 mV

= 1.0 V

±

10%), CLnot greater than 5pF (See

p-p

±

10%), clock pattern input.

p-p

IN+

and V

for the same bias condition.

IN−

Figure 1

)

Test Loads

CLC001

FIGURE 1. Test Loads

DS101329-4

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Test Loads (Continued)

CLC001

Pin Descriptions

DS101329-3

FIGURE 2. Test Circuit

Pin # Name Description

1V

BB

Optional, bias voltage (may be used to bias inputs) - see device operation

section for details. If unused leave as no connect (NC).
2V
3V
4R

IN+
IN­REF

Positive input pin

Negative input pin

Output driver level control. Connect a resistor to ground to set output voltage

swing.
5V

SS

Negative power supply
6 SDO Serial data true output
7 SDO
8V

DD

Serial data complement output

Positive power supply

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Device Operation

INPUT INTERFACING

Numerous input configurations exist for applying PECL,
LVPECL, and LVDS signals to the input of the CLC001.
Inputs may be single-ended or differential, AC or DC
coupled.

The V
the inputs. Leave this pin as a no connect when no bias is
needed. Note that DC-coupled inputs such as direct
LVDS and LVPECL connections are self-biasing and do
not require use of the V
by the V
I

BB

determined by the value of resistance, R
V
corresponds to some common VBBvalues with R
at 1.91 kΩ and 1.5 kΩ, respectively.Some common input
configurations are shown in

pin may be used to provide a DC bias voltage to

BB

pin. IBB, the current produced

pin, depends on R

BB

BB

. For a given R

REF

REF

current will remain constant, and the bias voltage is

, between the

pin and ground.

BB

Figure 3

and

Figure 5

Figure 4

through

BB

show how R

REF

Figure 9

, the

BB

held

.

CLC001

FIGURE 3. RBBvs. VBBfor R

FIGURE 4. RBBvs. VBBfor R

REF

REF

DS101329-11

= 1.91 kΩ

DS101329-12

= 1.5 kΩ

www.national.com5

Device Operation (Continued)

Figure 5

CLC001

ended input connection. The 82.5Ω resister in parallel

shows the CLC001 with an AC-coupled, single

FIGURE 5. Single Ended 75Ω Coaxial Cable, AC-coupled

with 825Ω gives the equivalent termination resistance of
75Ω.R

set at 5kΩ provides 1.25V of DC bias to the

BB

input.

DS101329-5

A typical DC-coupled, twisted pair cable connection is
shown in

Figure 6

. The CLC001 is driven differentially.
The line is terminated with a termination resistor equal to
the impedance of the linebeing driven. The actual resistor
value is media specific, but typically is between 100 and

FIGURE 6. Twisted Pair Cable, DC-coupled

120Ω depending upon the cable. This resistor should be
located close to the CLC001 inputs pins to minimize the
resulting stub length between the resistor and device
pads.

DS101329-6

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Device Operation (Continued)

Figure 7

application. It implements a center tap capacitance

shows an AC-coupled, twisted pair cable

FIGURE 7. Twisted Pair Cable, AC-coupled

termination used in conjunction with two 50Ω resistors to
filter common mode noise. R

set at 5kΩ provides 1.25V

BB

of DC bias to each input.

DS101329-7

CLC001

PECL or LVPECL drivers may be interfaced to the
CLC001 as shown in

Figure 8

. The voltage divider
network will reduce the PECL output to the proper levels.
For LVPECL, the 100Ω series resistors should be

FIGURE 8. PECL, DC-coupled

removed, since the common mode range inputs of the
CLC001 are wide enough to accept LVPECL levels
directly. No external DC biasing is required for
PECL/LVPECL connections.

DS101329-8

www.national.com7

Device Operation (Continued)

Atypical LVDS input connection is shown in

CLC001

media is driven differentially by an LVDS driver.The line is
terminated with a termination resistor equal to the
impedance of the line being driven. The actual resistor
value is media specific, but typically is between 100 and

120Ω. This resistor should be located close to the
CLC001 inputs pins to minimize the resulting stub length

Figure 9

. The

FIGURE 9. LVDS, DC-coupled

between the resistor and device pads. The CLC001
supports
common mode range of 0.1V to 2.3V for a 200mV
differential signal.

±

100mV thresholds across the entire LVDS

DS101329-9

www.national.com 8

CLC001

Device Operation (Continued)

OUTPUT INTERFACING

The CLC001 has two complementary, ground referenced
outputs designed to drive AC-coupled and terminated
75Ω coaxial cables. The outputs are single ended;
however, they could be treated as a single differential
output as long as current paths from each output go to
ground.

The output of the CLC001 is a high impedance current
source. It expects to see a 75Ω shunt resistor before
driving cable to convert the current output to a voltage
and provide proper back-matching. No series back­matching resistors should be used. Refer to

Application

Output levels range from 800 mV

for an illustration.

p-p

to 1.0 V
75Ω AC-coupled, back-matched loads. Output level is
controlled by the value of R
is 1.91 kΩ±1% for 800 mV
V

p-p

R

REF

. Refer to

.

Figure 10

connected to pin 4. R

REF

, and 1.5 kΩ±1% for 1.0

p-p

for the output level’s sensitivity to

FIGURE 10. Output level’s sensitivity to R

The CLC001 is designed as an AC-coupled 75Ω cable
driver. It is not intended to drive 50Ω loads. The current
source output does not provide enough current to allow
for 800mV across a 50Ω doubly terminated load.

±

10% into

p-p

DS101329-13

Typical

REF

REF

Evaluation Board

Evaluation boards are available for a nominal charge that
demonstrate the basic operation of the SDI/SDV/SDH
devices. The evaluation boards can be ordered through
National’s Distributors. Supplies are limited, please check for
current availability.

The SD001EVK evaluation kit for the CLC001, Serial Digital
Cable Driver with Adjustable Outputs, provides an operating
environment in which the cable driver can be evaluated by
system / hardware designers. The evaluation board has all
the needed circuitry and connectors for easy connection and
checkout of the device circuit options as discussed in the
CLC001 datasheet. A schematic, parts list and pictorial
drawing are provided with the board.

From the WWW, the following information may be viewed /
downloaded for most evaluation boards:
www.national.com/appinfo/interface

Device Datasheet and / or EVK User Manual

•

View a picture of the EVK

•

View the EVK Schematic

•

View the top assembly drawing and BOM

•

View the bottom assembly drawing and BOM

•

PCB Layout Recommendations

Printed circuit board layout affects the performance of the
CLC001. The following guidelines will aid in achieving
satisfactory device performance.

Use a ground plane or power/ground plane sandwich

•

design for optimum performance.
Bypass device power with a 0.01 µF monolithic ceramic

•

capacitor in parallel with a 6.8 µF tantalum electrolytic
capacitor located no more than 0.1″ (2.5 mm) from the
device power pins.

Provide short, symmetrical ground return paths for:

•

— inputs,
— supply bypass capacitors and
— the output load.
Provide short, grounded guard traces located

•

— under the centerline of the package,
— 0.1″ (2.5 mm) from the package pins
— on both top and bottom of the board with connecting

vias.

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Physical Dimensions inches (millimeters) unless otherwise noted

Order Number CLC001AJE
NS Package Number M08A

CLC001 Serial Digital Cable Driver with Adjustable Outputs

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DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL
COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:

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into the body, or (b) support or sustain life, and
whose failure to perform when properly used in
accordance with instructions for use provided in the
labeling, can be reasonably expected to result in a
significant injury to the user.

2. A critical component is any component of a life
support device or system whose failure to perform
can be reasonably expected to cause the failure of
the life support device or system, or to affect its
safety or effectiveness.

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Corporation

Americas
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National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.

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