Rainbow Electronics BR24L32FV-W User Manual

BR24L32-W / BR24L32F-W / BR24L32FJ-W / BR24L32FV-W

Memory ICs

4k×8 bit electrically erasable PROM

BR24L32-W / BR24L32F-W / BR24L32FJ-W
BR24L32FV-W

The BR24L32-W series is 2-wire (I2C BUS type) serial EEPROMs which are electrically programmable.

2

C BUS is a registered trademark of Philips.

I

∗

Applications

z

General purpose

Features

z

1) 4k registers × 8 bits serial architecture.

2) Single power supply (1.8V to 5.5V).

3) T wo w ire seri al in terfa ce.

4) Automatic erase.

5) 32byte Page Write Mode.

6) Low power consumption.
Write
Read (5V) : 0.2mA (Typ.)
Standby (5V) : 0.1µA (Typ .)

7) DATA security
Write protect feature (WP pin).
Inhibit to WRITE at low V

8) Small package - - - DIP8 / SOP8 / SSOP-B8 pin

9) High reliability EEPROM with Double-Cell structure.

10) High reliability fine pattern CMOS technology.

11) Endurance : 1,000,000 erase / write cycles

12) Data retent ion : 40 y ears

13) Filtered inputs in SCL,SDA for noise suppression.

14) Initial data FFh in all address.

(5V) : 1.5 mA (Typ.)

CC

.

Absolute maximum ratings

z

Parameter Symbol Limits Unit

Supply voltage −0.3 to +6.5 V

Power dissipation mW

Storage temperature
Operating temperature
Terminal voltage

∗1 Degradation is done at 8.0mW/°C for operation above 25°C.
∗2,3 Degradation is done at 4.5mW/°C for operation above 25°C.
∗4 Degradation is done at 3.0mW/°C for operation above 25°C.

(T a=25°C)

CC

V

Pd

Tstg

Topr

−

800(DIP8)

450(SOP8)

450(SOP-J8)

300(SSOP-B8)

−65 to +125

−40 to +85

−0.3 to VCC+0.3

∗1
∗2
∗3
∗4

°C
°C

V

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BR24L32-W / BR24L32F-W / BR24L32FJ-W / BR24L32FV-W

Memory ICs

Recommende d operat ing condi tions

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Parameter Symbol Limits Unit
Supply voltage
Input voltage V

CC

V

IN

(Ta=25°C)

1.8 to 5.5
0 to V

V

CC

V

DC operating ch aract eristi cs

z

(Unless otherwise specified T a=−40 to 85°C, V

Parameter Symbol Min. Typ. Max. Unit Conditions

0.7V

"HIGH" input volatge 1
"LOW" input volatge 1
"HIGH" input volatge 2
"LOW" input volatge 2
"LOW" output volatge 1
"LOW" output volatge 2
Input leakage current I
Output leakage current I

IH1

V
V

IL1

V

IH2

V

IL2

OL1

V

OL2

V

LI

LO

I

CC1

−−

0.8V

−−

−−

−−

−1

−1 −

−

Operating current

I

CC2

Standby current I

This product is not designed for protection against radioactive rays.

SB

−

−

CC

−−

CC

−−

−

−

−

−

0.3V

CC

0.2V

CC

0.4 V

0.2 V
1 µA
1 µA

3.0 mA

0.5 mA

2.0

CC

1.8 to 5.5V)

=

<

V
V
V
V

<

2.5V V

=

<

2.5V V

=

1.8V V

=<=

<

1.8V V

=

CC
CC
CC
CC

=

<

=

<
<

=

5.5V

5.5V

2.5V

2.5V

IOL=3.0mA, 2.5V V
I

OL

=0.7mA, 1.8V V

VIN=0V to V

OUT

=0V to V

V

CC

=5.5V, f

V

SCL

Byte Write, Page Write

CC

=5.5V, f

V
Random Read, Current Read,
Sequential Read

CC

V

µA

A0,A1,A2=GND, WP=GND

SCL

=5.5V, SDA,SCL=VCC,

<

<

CC

5.5V, (SDA)

=

=

<

<

CC

5.5V, (SDA)

=

=

CC

CC

=400kHz, tWR=5ms,

=400kHz

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BR24L32-W / BR24L32F-W / BR24L32FJ-W / BR24L32FV-W

Memory ICs

Dimension

z

9.3±0.3

85

7.62

14

0.51Min.

0.3

±

3.4

0.2

±

2.54

3.2

Fig.1(a) PHYSICAL DIMENSION (Units : mm) DIP8 (BR24L32-W)

6.5±0.3

0.3±0.1

0° ~ 15°

0.5±0.1

5.0±0.2

85

4.4±0.2

6.2±0.3

1.5±0.1

0.11

Fig.1(b) PHYSICAL DIMENSION (Units : mm) SOP8 (BR24L32F-W)

41

1.27

0.4±0.1

0.3Min.

0.15±0.1

0.1

4.9±0.2
85

76

3.9±0.2

6.0±0.3

1.375±0.1

0.175

Fig.1(c) PHYSICAL DIMENSION (Units : mm) SOP-J8 (BR24L32FJ-W)

4123

1.27

0.42±0.1

0.45Min.

0.2±0.1

0.1

3.0±0.2

548

0.2

±

4.4

6.4±0.3

1

0.1

1.15±0.1

(0.52)

Fig.1(d) PHYSICAL DIMENSION (Units : mm) SSOP-B8 (BR24L32FV-W)

0.22±0.1

0.65

0.3Min.

0.15±0.1

0.1

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BR24L32-W / BR24L32F-W / BR24L32FJ-W / BR24L32FV-W

Memory ICs

Block diagra m

z

1

A0

32kbit EEPROM array

VCC8

GND 4

Pin configur ation

z

A1 2

A2 3

12bit

Address
decoder

12bits

Slave word

address register

STOPSTART

Control logic

High voltage generator Vcc level detect

Fig.2 BLOCK DIAGRAM

V

CC

WP

SCLA2SDA

BR24L32-W
BR24L32F-W
BR24L32FJ-W
BR24L32FV-W

8bit

Data

WP7

register

6 SCL

ACK

SDA5

5678

Pin name

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Pin name

V

CC

GND

A0, A1, A2

SCL
SDA

WP

∗ An open drain output requires a pull-up resistor.

I / O

−

−

IN
IN

IN / OUT

IN

Power supply
Ground (0V)
Slave address set
Serial clock input
Slave and word address,

serial data input, serial data output
Write protect input

1234

A0

A1

GND

Fig.3 PIN LAYOUT

Function

∗

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BR24L32-W / BR24L32F-W / BR24L32FJ-W / BR24L32FV-W

Memory ICs

AC operatin g ch aract eris tics

z

Parameter Symbol

Clock frequency
Data clock "HIGH" period
Data clock "LOW" period tLOW

SDA and SCL rise time
SDA and SCL fall time tF
Start condition hold time
Start condition setup time
Input data hold time
Input data setup time
Output data delay time
Output data hold time
Stop condition setup time
Bus free time
Write cycle time
Noise spike width (SDA and SCL)
WP hold time
WP setup time
WP high period

∗ Not 100% tested.

(Unless otherwise specified T a=−40 to 85°C, V

∗
∗

tHD:STA
tSU:STA
tHD:DAT
tSU:DAT

tSU:STO

tHIGH:WP

CC

1.8 to 5.5V)

=

Fast-mode

2.5V Vcc 5.5V

Min.

fSCL kHz

tHIGH

tR

tPD

tDH

tBUF

tWR

tI

tHD:WP

tSU:WP

−

0.6

1.2

−

−

0.6

0.6
0

100

0.1

0.1

0.6

1.2

−

−

0

0.1

1.0

<

=<=

Max.

Typ.

400

−

−

−

−

−

−

−

−

−

−

−

−

−

−

−

−

−−

−−

−

−

0.3

0.3

−

−

−

−

0.9

−

−

−

5

0.1

−

Standard-mode

<

1.8V Vcc 5.5V

Min.

−

4.0

4.7

−

−

4.0

4.7
0

250

0.2

0.2

4.7

4.7

−

−

0

0.1

1.0

<

=

=

Typ.

−

−

−

−

−

−

−

−

−

−

−

−

−

−

−

−

−−

−−

Max.

100

−

−

1.0

0.3

−

−

−

−

3.5

−

−

−µs

5

0.1

−

Unit

µs
µs
µs
µs
µs
µs

ns
ns

µs
µs
µs

ms

µs
ns

µs
µs

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BR24L32-W / BR24L32F-W / BR24L32FJ-W / BR24L32FV-W

Memory ICs

Synchronous d ata timin g

z

t

HIGH

t

DH

SCL

SDA

(IN)

SDA

(OUT)

t

R

t

HD :

STA t

t

BUF

tSU : DAT tHD : DAT

t

F

t

LOW

PD

SCL

SDA

START BIT STOP BIT

Fig.4 SYNCHRONOUS DATA TIMING

SDA data is latched into the chip at the rising edge of SCL clock.

•

Output data toggles at the falling edge of SCL clock.

•

Write cy cle timing

z

SCL

SDA

WRITE DATA (n)

ACKD0

tSU : STOtHD : STAtSU : STA

t

WR

START CONDITIONSTOP CONDITION

Fig.5 WRITE CYCLE TIMING

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BR24L32-W / BR24L32F-W / BR24L32FJ-W / BR24L32FV-W

Memory ICs

WP timing

z

SCL

DATA (n)DATA (1)

SDA

WP

SCL

SDA

WP

D1

t

SU : WP

D0

ACKACK

t

WR

STOP BIT

t

HD : WP

Fig.6(a) WP TIMING OF THE WRITE OPERATION

DATA (n)DATA (1)

D1

D0

t

HIGH : WP

ACKACK

Fig.6(b) WP TIMING OF THE WRITE CANCEL OPERATION

•For the WRITE operation, WP must be “LOW” during the period of time from the rising edge of the clock which takes in
D0 of first byte until the end of t

WR

. ( See Fig. 6 (a) )

During this period, WRITE operation is canceled by setting WP “HIGH”. ( See Fig.6 (b) )

•In the case of setting WP “HIGH” during t

WR

, WRITE operation is stopped in the middle and the data of accessing

address is not guaranteed. Please write correct data again in the case.

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BR24L32-W / BR24L32F-W / BR24L32FJ-W / BR24L32FV-W

Memory ICs

Device oper ation

z

1) Start condition (Recognition of start bit)

• All commands are proceeded by the start condition, which is a HIGH to LOW transition of SDA when SCL is HIGH.

• The device continuously monitors the SDA and SCL lines for the start condition and will not respond to any command
until this condition has been met. (See Fig.4 SYNCHRONOUS DATA TIMING)

2) Stop condition (Recognition of stop bit)

• All communications must be terminated by a stop condition, which is a LOW to HIGH transition of SDA when SCL is
HIGH. (Se e Fig.4 SY NCHRONOUS D AT A TIM ING)

3) Notice about write command

• In the case that stop condition is not executed in WRITE mode, transferred data will not be written in a memory.

4) Device addressing

• Following a START condition, the master output the slave address to be accessed.

• The most sig nifica nt four bi ts of th e slave ad dress ar e the “de vice ty pe ident ifier”, f or thi s devic e it is fixe d as “1010” .

• The next three bit (device address) identify the specified device on the bus.
The device address is defined by the state of A0, A1 and A2 input pins. This IC works only when the device address
inputted from SDA pin correspond to the state of A0, A1 and A2 input pins. Using this address scheme, up to eight
devices may be connected to the bus. The last bit of the stream (R/W - - - READ / WRITE) determines the operation

to the performed.

• The last bit of the stream (R/W - - - READ / WRITE) determines the operation to be performed. When set to “1”, a read
operation is selected ; when set to “0”, a write operation is selected.

R / W set to “0” - - - - - - WRITE (including word address input of Random Read)
R / W set to “1” - - - - - - READ

5) Write protect (WP)
When WP pin set to V
When WP pin set to GND (L level), enable to write 4,096 words (all address).
Either control this pin or connect to GND (or V

A2 A1 A01010 R / W

CC

(H level), write protect is set for 4,096 words (all address).

CC

). It is inhibited from being left unconnected.

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