Rainbow Electronics BR24L08FVM-W User Manual

BR24L08-W / BR24L08F-W / BR24L08FJ-W

Memory ICs BR24L08FV-W / BR24L08FVM-W

1024×8 bit electrically erasable PROM

BR24L08-W / BR24L08F-W / BR24L08FJ-W / BR24L08FV -W / BR24L08FVM-W

The BR24L08-W series is 2-wire (I2C BUS type) serial EEPROMs which are electrically programmable.

∗ I2C BUS is a registered trademark of Philips.

zApplications General purpose

zFeatu res

1) 1024 registers × 8 bits serial architecture.

2) Single power supply (1.8 V to 5.5V).

3) Two wire serial interface.

4) Self-timed write cycle with automatic erase.

5) 16byte Page Write mode.

6) Low power consumption. Write Read (5V) : 0.2mA (Typ.) Standby (5V) : 0.1µA (Typ.)

7) DATA security Write protect feature (WP pin). Inhibit to WRITE at low V

8) Small package - - - DIP8 / SOP8 / SOP-J8 / SSOP-B8 / MSOP-8

9) High reliability EEPROM with Double-Cell structure.

10) High reliability fine patte rn CMOS te chnology.

11) Endurance : 1,000,000 erase / write cycles

12) Data retention : 40 years

13) Filtered inputs in SCL

14) Initial data FFh in all address.

zAbsolute maximum ratings (T a=25°C)

Supply voltage −0.3 to +6.5 V

Power dissipation mW

Storage temperature Operating temperature Terminal voltage

∗1 Reduced by 8.0mW for each increase in Ta of 1°C over 25°C. ∗2 Reduced by 4.5mW for each increase in Ta of 1°C over 25°C. ∗3 Reduced by 3.0mW for each increase in Ta of 1°C over 25°C. ∗4 Reduced by 3.1mW for each increase in Ta of 1°C over 25°C.

(5V) : 1.5mA (T yp.)

CC.

•SDA for noise suppression.

Parameter Symbol Limits Unit

V

CC

∗1 ∗2 ∗2 ∗3 ∗4

°C °C

V

Pd

Tstg

Topr

−

800(DIP8)

450(SOP8)

450(SOP-J8)

300(SSOP-B8)

310(MSOP8)

−65 to +125

−40 to +85

−0.3 to VCC+0.3

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BR24L08-W / BR24L08F-W / BR24L08FJ-W

Memory ICs BR24L08FV-W / BR24L08FVM-W

zRecommended operating conditions (Ta=25°C)

Parameter Symbol Limits Unit

CC

Supply voltage Input voltage V

zDC operating charac teristics (Unless otherwise specified Ta=−40 to 85°C, VCC=1.8 to 5.5V)

Parameter Symbol Min. Typ. Max. Unit Conditions "HIGH" input volatge 1 "LOW" input volatge 1 "HIGH" input volatge 2 "LOW" input volatge 2 "LOW" output volatge 1 "LOW" output volatge 2 Input leakage current I Output leakage current I

Operating current

Standby current I

This product is not designed for protection against radioactive rays.

V

IN

IH1

IL1

IH2

IL2

OL1

OL2

LI

LO

SB

0.7V

0.8V

V V V V

V V

I

CC1

CC2

I

1.8 to 5.5 0 to V

CC

−−

CC

−−

−1

−

−1 −

−

CC

0.3V

CC

0.2V

0.4 V

0.2 V 1 µA 1 µA

2.0 mA

0.5 mA

2.0

V V

V V V V

CC

2.5V≤V

≤5.5V

2.5V≤VCC≤5.5V

CC

1.8V≤V

<2.5V

1.8V≤VCC<2.5V IOL=3.0mA, 2.5V≤VCC≤5.5V, (SDA)

OL

=0.7mA, 1.8V≤VCC≤5.5V, (SDA)

I VIN=0V to V

OUT

V V

CC

=0V to V

=5.5V, f

CC

SCL

=400kHz, tWR=5ms,

Byte Write, Page Write

CC

=5.5V, f

SCL

V Random Read, Current Read, Sequential Read

CC

=5.5V, SDA•SCL=VCC,

V

µA

A0, A1, A2=GND, WP=GND

=400kHz

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BR24L08-W / BR24L08F-W / BR24L08FJ-W

Memory ICs BR24L08FV-W / BR24L08FVM-W

zDimension

9.3±0.3

85

5.0±0.2

6.2±0.3

1.5±0.1

85

4.4±0.2

1.27

0.11

41

0.4±0.1

0.3Min.

0.15±0.1

0.1

14

0.51Min.

0.3

±

3.4

0.2

±

2.54

3.2

0.5±0.1

6.5±0.3

7.62

0.3±0.1

0° ~ 15°

Fig.1(a) PHYSICAL DIMENSION (Units : mm) DIP8 (BR24L08-W)

4.9±0.2

85

76

6.0±0.3

3.9±0.2

1.375±0.1

0.175

Fig.1(c) PHYSICAL DIMENSION (Units : mm) SOP-J8 (BR24L08FJ-W)

4123

1.27

0.42±0.1

0.45Min.

0.2±0.1

0.1

2.9±0.1

58

0.1

4.0±0.2

0.475

±

2.8

41

0.29±0.15

0.145

0.6±0.2

+0.05

−0.03

Fig.1(b) PHYSICAL DIMENSION (Units : mm) SOP8 (BR24L08F-W)

3.0±0.2

548

0.2

±

4.4

6.4±0.3

1

0.1

0.22±0.1

1.15±0.1

(0.52)

Fig.1(d) PHYSICAL DIMENSION (Units : mm) SSOP-B8 (BR24L08FV-W)

0.65

0.3Min.

0.15±0.1

0.1

+0.05

0.22

0.9Max.

0.65

0.75±0.05

0.08±0.05

Fig.1(e) PHYSICAL DIMENSION (Units : mm) MSOP8 (BR24L08FVM-W)

−0.04

0.08 S

0.08

M

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BR24L08-W / BR24L08F-W / BR24L08FJ-W

Memory ICs BR24L08FV-W / BR24L08FVM-W

zBlock diagram

A1 2

A2 3

GND 4

zPin configuration

1A0

10bit

Address decoder

Control logic

High voltage generator Vcc level detect

32kbit EEPROM array

10bit

V

address register

Fig.2 BLOCK DIAGRAM

CC

WP

BR24L08-W BR24L08F-W BR24L08FJ-W BR24L08FV-W BR24L08FVM-W

Slave word

STOPSTART

SCL

SDA

5678

ACK

8bit

Data register

V

CC8

WP7

6 SCL

SDA5

zPin name

Pin name

CC

V

GND

A2

SCL SDA

WP

∗1 An open drain output requires a pull-up resistor.

I / O

−

IN IN

IN / OUT

IN

Power supply Ground (0V) Out of useA0, A1 Slave address set Serial clock input Slave and word address,

serial data input, serial data output Write protect input

1234

A0

Function

A1

Fig.3 PIN LAYOUT

A2

∗1

GND

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BR24L08-W / BR24L08F-W / BR24L08FJ-W

Memory ICs BR24L08FV-W / BR24L08FVM-W

zAC operating characteristics (Unless otherwise specified Ta=−40 to 85°C, V

Fast-mode

Parameter Symbol

Clock frequency Data clock "HIGH" period Data clock "LOW" period tLOW

SDA and SCL rise time SDA and SCL fall time tF Start condition hold time Start condition setup time Input data hold time Input data setup time Output data delay time Output data hold time Stop condition setup time Bus free time Write cycle time Noise spike width (SDA and SCL) WP hold time WP setup time WP high period

∗1 Not 100% tested.

∗1 ∗1

fSCL kHz

tHIGH

tR

tHD:STA tSU:STA tHD:DAT ns tSU:DAT ns

tPD

tDH

tSU:STO µs

tBUF

tWR

tl

tHD:WP tSU:WP

tHIGH:WP

2.5V ≤ Vcc ≤ 5.5V

Min.

Typ.

−

0.6

−

1.2

−

0.6

−

0.6

−

0

−

100

0.1

0.6

1.2

−

0

0.1

1.0

−

−−

CC=1.8 to 5.5V)

1.8V ≤ Vcc ≤ 5.5V

Max.

Min.

400

4.0

−

4.7

−

0.3

4.0

−

4.7

−

250

−

0.9

0.2

−

4.7

−

4.7

5

0.1

−

0.1

1.0

Standard-mode

Typ.

−

0

−

0

−

−−

Max.

100

−

1.0

0.3

−

3.5

−

−µs

5

0.1

−

Unit

µs µs µs µs µs µs

µs µs

ms

µs ns

µs µs

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BR24L08-W / BR24L08F-W / BR24L08FJ-W

Memory ICs BR24L08FV-W / BR24L08FVM-W

zSynchronous dat a timing

t

HIGH

t

DH

SCL

SDA

(IN)

SDA

(OUT)

t

R

t

HD :

STA t

t

BUF

tSU : DAT tHD : DAT

t

F

LOW

t

PD

SCL

SDA

START BIT STOP BIT

Fig.4 SYNCHRONOUS DATA TIMING

•SDA data is latched into the chip at the rising edge of SCL clock.

•Output data toggles at the falling edge of SCL clock.

zWrite cy cle timing

SCL

SDA

WRITE DATA (n)

ACKD0

tSU : STOtHD : STAtSU : STA

t

WR

START CONDITIONSTOP CONDITION

Fig.5 WRITE CYCLE TIMING

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BR24L08-W / BR24L08F-W / BR24L08FJ-W

Memory ICs BR24L08FV-W / BR24L08FVM-W

zWP timing

SCL

DATA (n)DATA (1)

SDA

WP

SCL

SDA

WP

D1

t

SU : WP

D0

Fig.6(a) WP TIMING OF THE WRITE OPERATION

DATA (n)DATA (1)

D0

t

HIGH : WP

ACKACK

t

WR

STOP BIT

t

HD : WP

ACKACK

Fig.6(b) WP TIMING OF THE WRITE CANCEL OPERATION

•For the WRITE operation, WP must be “LOW” during the period of time from the rising edge of the clock which takes in D0 of first byte until the end of t

WR. ( See Fig.6 (a) )

During this period, WRITE operation is canceled by setting WP “HIGH”. ( See Fig.6 (b) )

•In the case of setting WP “HIGH” during tWR, WRITE operation is stopped in the middle and the data of accessing address is not guaranteed. Please write correct data again in the case.

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BR24L08-W / BR24L08F-W / BR24L08FJ-W

Memory ICs BR24L08FV-W / BR24L08FVM-W

zDevice operation

1) Start condi tion (Recognition of st art bit)

• All commands are proceeded by the start condition, which is a HIGH to LOW transition of SDA when SCL is HIGH.

• The device continuously monitors the SDA and SCL lines for the start condition and will not respond to any command until this condition has been met. (See Fig.4 SYNCHRONOUS DAT A TIMING)

2) Stop conditio n (Recognition of sto p bit)

• All communications must be terminated by a stop condi tion, which is a LOW to HIGH transition of SDA when SCL is HIGH. (See Fig.4 SYNCHRONOUS DAT A TIMING)

3) Notice about write command

• In the case that stop condition is not executed in WRITE mode, transferred dat a will not be w ritten in a memory.

4) Device addressing

• Following a START condition, the master output the slave address to be accessed.

• The most significant four bits of the slave address are the “device type identifier”, for this device it is fixed as “1010”.

• The next bit (device address) identify the specified device on the bus. The device address is defined by the state of A2 input pin. This IC works only when the device address inputted from SDA pin correspond to the state of A2 input pin. Using this address scheme, up to two devices may be

connected to the bus.

• The nex t two bits (P1 , P0) are used by the master to select t four 256 word p age of memory.

P1, P0 set to “0” “0” - - - - - - 1page (000 to 0FF) P1, P0 set to “0” “1” - - - - - - 2page (100 to 1FF) P1, P0 set to “1” “0” - - - - - - 3page (200 to 2FF) P1, P0 set to “1” “1” - - - - - - 4page (300 to 3FF)

• The last bit of the stream (R/W - - - READ / WRITE) determines the operation to be performed. When set to “1”, a read operation is selected ; when set to “0”, a write operation is selected.

R / W set to “0” - - - - - - WRITE (including word address input of Random Re ad) R / W set to “1” - - - - - - READ

5) Write protect (WP) When WP pin set to V When WP pin set to GND (L level), enable to write 1024 words (all address). Either control this pin or connect to GND (or VCC). It is inhibited from being left unconnected.

A2 P1 P01010 R / W

CC (H level), write protect is set for 1024 words (all address).

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