Rainbow Electronics BR24L02FVM-W User Manual

BR24L02-W / BR24L02F-W / BR24L02FJ-W /

Memory ICs

BR24L02FV-W / BR24L02FVM-W

256×8 bit electrically erasable PROM

BR24L02-W / BR24L02F-W / BR24L02FJ-W
BR24L02FV-W / BR24L02FVM-W

The BR24L02-W series is 2-wire (I2C BUS type) serial EEPROMs which are electrically programmable.

2

C BUS is a registered trademark of Philips.

I

∗

Applications

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General purpose

Features

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1) 256 registers × 8 bits serial arc hitec ture.

2) Single power supply (1.8V to 5.5V).

3) T wo w ire seri al in terfa ce.

4) Self-timed write cycle with automatic erase.

5) 8 byte page wr ite mode .

6) Low power consumption.
Write
Read (5V) : 0.2mA (Typ.)
Standby (5V) : 0.1µA (Ty p.)

7) DATA security
Write protect feature (WP pin) .
Inhibit to WRITE at low V

8) Small package - - - DIP 8 / SOP8 / SOP-J8 / SSOP-B 8 / MSOP-8

9) High reliability EEPROM with Double-Cell structure

10) High reliability fine pattern CMOS technology.

11) Endurance : 1,000,000 erase / write cycles

12) Data retent ion : 40 y ears

13) Filtered inputs in SC L

14) Initial data FFh in all address.

(5V) : 1.2 mA (Typ.)

CC

•

SDA for noise suppression.

.

Absolute maximum ratings

z

Parameter Symbol Limits Unit

Supply voltage −0.3 to +6.5 V

Power dissipation mW

Storage temperature
Operating temperature
Terminal voltage

∗1 Degradation is done at 8.0mW/°C for operation above 25°C.
∗2, 3 Degradation is done at 4.5mW/°C for operation above 25°C.
∗4 Degradation is done at 3.0mW/°C for operation above 25°C.
∗5 Degradation is done at 3.1mW/°C for operation above 25°C.

(T a=25°C)

V

CC

Pd

Tstg

Topr

−

800 (DIP8)

450 (SOP8)

450 (SOP-J8)

300 (SSOP-B8)

310 (MSOP8)

−65 to +125

−40 to +85

−0.3 to VCC+0.3

∗1
∗2

∗3
∗4
∗5

°C
°C

V

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BR24L02-W / BR24L02F-W / BR24L02FJ-W /

Memory ICs

Recommende d operat ing condi tions

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Parameter Symbol Limits Unit
Supply voltage
Input voltage V

DC operating ch aract eristi cs

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Parameter Symbol Min. Typ. Max. Unit Conditions

"HIGH" input volatge 1
"LOW" input volatge 1
"HIGH" input volatge 2
"LOW" input volatge 2
"LOW" output volatge 1
"LOW" output volatge 2
Input leakage current I
Output leakage current I

Operating current

Standby current I

This product is not designed for protection against radioactive rays.

CC

V

IN V

(Unless otherwise specified T a=−40 to 85°C, VCC=1.8 t o 5.5V)

0.7V

IH1

V
V

IL1

V

IH2

0.8V

V

IL2

OL1

V

OL2

V

LI

LO

I

CC1

I

CC2

SB

1.8 to 5.5
0 to V

CC

CC

−−

−−

CC

−−

−−

−−

−−

−1

−

−1 −

−

−

−

−

−

−

BR24L02FV-W / BR24L02FVM-W

V

0.3V

CC

0.2V

CC

0.4 V

0.2 V
1 µA
1 µA

2.0 mA

0.5 mA

2.0

V
V
V
V

µA

CC

2.5V≤V

≤5.5V

2.5V≤VCC≤5.5V

CC

1.8V≤V

≤2.5V

1.8V≤VCC≤2.5V
IOL=3.0mA, 2.5V≤VCC≤5.5V, (SDA)

I

OL

=0.7mA, 1.8V≤VCC≤5.5V, (SDA)

VIN=0V to V

OUT

V

CC

V

=0V to V

=5.5V, f

CC

CC

SCL

=400kHz, tWR=5ms,

Byte Write, Page Write

CC

=5.5V, f

SCL

V
Random Read, Current Read,
Sequential Read

CC

=5.5V, SDA·SCL=VCC,

V

=400kHz

A0, A1, A2=GND, WP=GND

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BR24L02-W / BR24L02F-W / BR24L02FJ-W /

Memory ICs

Dimension

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9.3±0.3

85

0.5±0.1

6.5±0.3

7.62

0° ~ 15°

14

0.51Min.

0.3

±

3.4

0.2

±

2.54

3.2

0.3±0.1

BR24L02FV-W / BR24L02FVM-W

5.0±0.2

85

6.2±0.3

1.5±0.1

4.4±0.2

0.11

41

1.27

0.4±0.1

0.3Min.

0.15±0.1

0.1

Fig.1(a) PHYSICAL DIMENSION (Units : mm)
DIP8 (BR24L02-W)

4.9±0.2

85

76

6.0±0.3

3.9±0.2

1.375±0.1

0.175

Fig.1(c) PHYSICAL DIMENSION (Units : mm)
SOP-J8 (BR24L02FJ-W)

4123

1.27

0.42±0.1

0.45Min.

0.2±0.1

0.1

2.9±0.1

58

0.1

4.0±0.2

0.475

±

2.8

41

0.29±0.15

0.145

0.6±0.2

+0.05

−0.03

Fig.1(b) PHYSICAL DIMENSION (Units : mm)
SOP8 (BR24L02F-W)

3.0±0.2

548

0.2

±

4.4

6.4±0.3

1

0.1

0.22±0.1

1.15±0.1

(0.52)

Fig.1(d) PHYSICAL DIMENSION (Units : mm)
SSOP-B8 (BR24L02FV-W)

0.65

0.3Min.

0.15±0.1

0.1

+0.05

0.22

0.9Max.

0.65

0.75±0.05

0.08±0.05

Fig.1(e) PHYSICAL DIMENSION (Units : mm)
MSOP8 (BR24L02FVM-W)

−0.04

0.08 S

0.08

M

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BR24L02-W / BR24L02F-W / BR24L02FJ-W /

Memory ICs

Block diagra m

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1

A0

2kbit EEPROM array

BR24L02FV-W / BR24L02FVM-W

VCC8

GND 4

Pin configur ation

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A1 2

A2 3

8bit

Address
decoder

High voltage generator Vcc level detect

8bits

Control logic

Fig.2 BLOCK DIAGRAM

V

CC

Slave word

address register

STOPSTART

WP

SCL

BR24L02-W
BR24L02F-W
BR24L02FJ-W
BR24L02FV-W
BR24L02FVM-W

SDA

5678

ACK

8bit

Data
register

WP7

6 SCL

SDA5

Pin name

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Pin name

V

CC

GND

A0, A1, A2

SCL
SDA

WP

∗1 An open drain output requires a pull-up resistor.

I / O

−

−

IN
IN

IN / OUT

IN

Power supply
Ground (0V)
Slave address set
Serial clock input
Slave and word address,

serial data input, serial data output
Write protect input

1234

A0

Function

A1

Fig.3 PIN LAYOUT

A2

∗1

GND

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BR24L02-W / BR24L02F-W / BR24L02FJ-W /

Memory ICs

BR24L02FV-W / BR24L02FVM-W

AC operatin g ch aract eris tics

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Parameter Symbol

Clock frequency
Data clock "HIGH" period
Data clock "LOW" period tLOW

SDA and SCL rise time
SDA and SCL fall time tF
Start condition hold time
Start condition setup time
Input data hold time
Input data setup time
Output data delay time
Output data hold time
Stop condition setup time
Bus free time
Write cycle time
Noise spike width (SDA and SCL)
WP hold time
WP setup time
WP high period

∗1 Not 100% tested.

(Unless otherwise specified T a=−40 to 85°C, V

∗1
∗1

tHD:DAT
tSU:DAT

tSU:STO

tHIGH:WP

CC

=1.8 to 5.5V)

Fast-mode

2.5V ≤ Vcc ≤ 5.5V

Min.

Typ.

Max.

−

−

fSCL kHz

tHIGH

tR

tHD:STA
tSU:STA

tPD

tDH

tBUF

tWR

tl

tHD:WP
tSU:WP

0.6

1.2

−

−

0.6

0.6
0

100

0.1

0.1

0.6

1.2

−

−

0

0.1

1.0

400

−

−

−

−

−

−

−

−

−

−

−

−

−

−

−

−−

−−

1.8V ≤ Vcc ≤ 5.5V

Min.

4.0

−

4.7

−

0.3

0.3

4.0

−

4.7

−

−

250

−

0.9

0.2

0.2

−

−

4.7

−

4.7

5

0.1

−

0.1

1.0

Standard-mode

Typ.

−

−

−

−

−

−

−

−

−

−

0

−

−

−

−

−

−

−

−

−

−

0

−

−−

−−

Max.

100

−

−

1.0

0.3

−

−

−

−

3.5

−

−

−µs

5

0.1

−

Unit

µs
µs
µs
µs
µs
µs

ns
ns

µs
µs
µs

ms

µs
ns

µs
µs

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BR24L02-W / BR24L02F-W / BR24L02FJ-W /

Memory ICs

Synchronous d ata timin g

z

SCL

t

HD :

STA t

SDA

(IN)

t

BUF

SDA

(OUT)

BR24L02FV-W / BR24L02FVM-W

t

t

t

F

LOW

PD

t

R

tSU : DAT tHD : DAT

HIGH

t

DH

SCL

SDA

START BIT STOP BIT

Fig.4 SYNCHRONOUS DATA TIMING

SDA data is latched into the chip at the rising edge of SCL clock.

•

Output data toggles at the falling edge of SCL clock.

•

Write cy cle timing

z

SCL

SDA

WRITE DATA (n)

ACKD0

tSU : STOtHD : STAtSU : STA

t

WR

START CONDITIONSTOP CONDITION

Fig.5 WRITE CYCLE TIMING

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BR24L02-W / BR24L02F-W / BR24L02FJ-W /

Memory ICs

WP timing

z

SCL

DATA (n)DATA (1)

BR24L02FV-W / BR24L02FVM-W

SDA

WP

SCL

SDA

WP

D1

D1

t

SU : WP

D0

Fig.6(a) WP TIMING OF THE WRITE OPERATION

DATA (n)DATA (1)

D0

t

HIGH : WP

ACKACK

t

WR

STOP BIT

t

HD : WP

ACKACK

Fig.6(b) WP TIMING OF THE WRITE CANCEL OPERATION

•For the WRITE operation, WP must be “LOW” during the period of time from the rising edge of the clock which takes in
D0 of first byte until the end of t

WR

. ( See Fig. 6 (a) )

During this period, WRITE operation is canceled by setting WP “HIGH”. ( See Fig.6 (b) )

•In the case of setting WP “HIGH” during t

WR

, WRITE operation is stopped in the middle and the data of accessing

address is not guaranteed. Please write correct data again in the case.

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BR24L02-W / BR24L02F-W / BR24L02FJ-W /

Memory ICs

Device oper ation

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1) Start condition (Recognition of start bit)

• All commands are proceeded by the start condition, which is a HIGH to LOW transition of SDA when SCL is HIGH.

• The device continuously monitors the SDA and SCL lines for the start condition and will not respond to any command
until this condition has been met. (See Fig.4 SYNCHRONOUS DATA TIMING)

2) Stop condition (Recognition of stop bit)

• All communications must be terminated by a stop condition, which is a LOW to HIGH transition of SDA when SCL is
HIGH. (Se e Fig.4 SY NCHRONOUS D AT A TIM ING)

3) Notice about write command

• In the case that stop condition is not executed in WRITE mode, transferred data will not be written in a memory.

4) Device addressing

• Following a START condition, the master output the slave address to be accessed.

• The most sig nifica nt four bi ts of th e slave ad dress ar e the “de vice ty pe ident ifier”, f or thi s devic e it is fixe d as “1010” .

• The next three bit (device address) identify the specified device on the bus.
The device address is defined by the state of A0, A1 and A2 input pins. This IC works only when the device address
inputted from SDA pin correspond to the state of A0, A1 and A2 input pins. Using this address scheme, up to eight
device may be connected to the bus. The last bit of the stream (R/W - - - READ / WRITE) determines the operation to
the performed.

• The last bit of the stream (R/W - - - READ / WRITE) determines the operation to be performed. When set to “1”, a read
operation is selected ; when set to “0”, a write operation is selected.

BR24L02FV-W / BR24L02FVM-W

R / W set to “0” - - - - - - WRITE (including word address input of Random Read)
R / W set to “1” - - - - - - READ

5) Write protect (WP)
When WP pin set to V
When WP pin set to GND (L level), enable to write 256 words (all address).
Either control this pin or connect to GND (or V

A2 A1 A01010 R / W

CC

(H level), wri te pr ote ct is set for 256 w ords (all addr ess) .

CC

). It is inhibited from being left unconnected.

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