BR24L02-W / BR24L02F-W / BR24L02FJ-W /
Memory ICs
BR24L02FV-W / BR24L02FVM-W
256×8 bit electrically erasable PROM
BR24L02-W / BR24L02F-W / BR24L02FJ-W
BR24L02FV-W / BR24L02FVM-W
The BR24L02-W series is 2-wire (I2C BUS type) serial EEPROMs which are electrically programmable.
2
C BUS is a registered trademark of Philips.
I
∗
Applications
z
General purpose
Features
z
1) 256 registers × 8 bits serial arc hitec ture.
2) Single power supply (1.8V to 5.5V).
3) T wo w ire seri al in terfa ce.
4) Self-timed write cycle with automatic erase.
5) 8 byte page wr ite mode .
6) Low power consumption.
Write
Read (5V) : 0.2mA (Typ.)
Standby (5V) : 0.1µA (Ty p.)
7) DATA security
Write protect feature (WP pin) .
Inhibit to WRITE at low V
8) Small package - - - DIP 8 / SOP8 / SOP-J8 / SSOP-B 8 / MSOP-8
9) High reliability EEPROM with Double-Cell structure
10) High reliability fine pattern CMOS technology.
11) Endurance : 1,000,000 erase / write cycles
12) Data retent ion : 40 y ears
13) Filtered inputs in SC L
14) Initial data FFh in all address.
(5V) : 1.2 mA (Typ.)
CC
•
SDA for noise suppression.
.
Absolute maximum ratings
z
Parameter Symbol Limits Unit
Supply voltage −0.3 to +6.5 V
Power dissipation mW
Storage temperature
Operating temperature
Terminal voltage
∗1 Degradation is done at 8.0mW/°C for operation above 25°C.
∗2, 3 Degradation is done at 4.5mW/°C for operation above 25°C.
∗4 Degradation is done at 3.0mW/°C for operation above 25°C.
∗5 Degradation is done at 3.1mW/°C for operation above 25°C.
(T a=25°C)
V
CC
Pd
Tstg
Topr
−
800 (DIP8)
450 (SOP8)
450 (SOP-J8)
300 (SSOP-B8)
310 (MSOP8)
−65 to +125
−40 to +85
−0.3 to VCC+0.3
∗1
∗2
∗3
∗4
∗5
°C
°C
V
1/25
BR24L02-W / BR24L02F-W / BR24L02FJ-W /
Memory ICs
Recommende d operat ing condi tions
z
Parameter Symbol Limits Unit
Supply voltage
Input voltage V
DC operating ch aract eristi cs
z
Parameter Symbol Min. Typ. Max. Unit Conditions
"HIGH" input volatge 1
"LOW" input volatge 1
"HIGH" input volatge 2
"LOW" input volatge 2
"LOW" output volatge 1
"LOW" output volatge 2
Input leakage current I
Output leakage current I
Operating current
Standby current I
This product is not designed for protection against radioactive rays.
CC
V
IN V
(Unless otherwise specified T a=−40 to 85°C, VCC=1.8 t o 5.5V)
0.7V
IH1
V
V
IL1
V
IH2
0.8V
V
IL2
OL1
V
OL2
V
LI
LO
I
CC1
I
CC2
SB
1.8 to 5.5
0 to V
CC
CC
−−
−−
CC
−−
−−
−−
−−
−1
−
−1 −
−
−
−
−
−
−
BR24L02FV-W / BR24L02FVM-W
V
0.3V
CC
0.2V
CC
0.4 V
0.2 V
1 µA
1 µA
2.0 mA
0.5 mA
2.0
V
V
V
V
µA
CC
2.5V≤V
≤5.5V
2.5V≤VCC≤5.5V
CC
1.8V≤V
≤2.5V
1.8V≤VCC≤2.5V
IOL=3.0mA, 2.5V≤VCC≤5.5V, (SDA)
I
OL
=0.7mA, 1.8V≤VCC≤5.5V, (SDA)
VIN=0V to V
OUT
V
CC
V
=0V to V
=5.5V, f
CC
CC
SCL
=400kHz, tWR=5ms,
Byte Write, Page Write
CC
=5.5V, f
SCL
V
Random Read, Current Read,
Sequential Read
CC
=5.5V, SDA·SCL=VCC,
V
=400kHz
A0, A1, A2=GND, WP=GND
2/25
BR24L02-W / BR24L02F-W / BR24L02FJ-W /
Memory ICs
Dimension
z
9.3±0.3
85
0.5±0.1
6.5±0.3
7.62
0° ~ 15°
14
0.51Min.
0.3
±
3.4
0.2
±
2.54
3.2
0.3±0.1
BR24L02FV-W / BR24L02FVM-W
5.0±0.2
85
6.2±0.3
1.5±0.1
4.4±0.2
0.11
41
1.27
0.4±0.1
0.3Min.
0.15±0.1
0.1
Fig.1(a) PHYSICAL DIMENSION (Units : mm)
DIP8 (BR24L02-W)
4.9±0.2
85
76
6.0±0.3
3.9±0.2
1.375±0.1
0.175
Fig.1(c) PHYSICAL DIMENSION (Units : mm)
SOP-J8 (BR24L02FJ-W)
4123
1.27
0.42±0.1
0.45Min.
0.2±0.1
0.1
2.9±0.1
58
0.1
4.0±0.2
0.475
±
2.8
41
0.29±0.15
0.145
0.6±0.2
+0.05
−0.03
Fig.1(b) PHYSICAL DIMENSION (Units : mm)
SOP8 (BR24L02F-W)
3.0±0.2
548
0.2
±
4.4
6.4±0.3
1
0.1
0.22±0.1
1.15±0.1
(0.52)
Fig.1(d) PHYSICAL DIMENSION (Units : mm)
SSOP-B8 (BR24L02FV-W)
0.65
0.3Min.
0.15±0.1
0.1
+0.05
0.22
0.9Max.
0.65
0.75±0.05
0.08±0.05
Fig.1(e) PHYSICAL DIMENSION (Units : mm)
MSOP8 (BR24L02FVM-W)
−0.04
0.08 S
0.08
M
3/25
BR24L02-W / BR24L02F-W / BR24L02FJ-W /
Memory ICs
Block diagra m
z
1
A0
2kbit EEPROM array
BR24L02FV-W / BR24L02FVM-W
VCC8
GND 4
Pin configur ation
z
A1 2
A2 3
8bit
Address
decoder
High voltage generator Vcc level detect
8bits
Control logic
Fig.2 BLOCK DIAGRAM
V
CC
Slave word
address register
STOPSTART
WP
SCL
BR24L02-W
BR24L02F-W
BR24L02FJ-W
BR24L02FV-W
BR24L02FVM-W
SDA
5678
ACK
8bit
Data
register
WP7
6 SCL
SDA5
Pin name
z
Pin name
V
CC
GND
A0, A1, A2
SCL
SDA
WP
∗1 An open drain output requires a pull-up resistor.
I / O
−
−
IN
IN
IN / OUT
IN
Power supply
Ground (0V)
Slave address set
Serial clock input
Slave and word address,
serial data input, serial data output
Write protect input
1234
A0
Function
A1
Fig.3 PIN LAYOUT
A2
∗1
GND
4/25
BR24L02-W / BR24L02F-W / BR24L02FJ-W /
Memory ICs
BR24L02FV-W / BR24L02FVM-W
AC operatin g ch aract eris tics
z
Parameter Symbol
Clock frequency
Data clock "HIGH" period
Data clock "LOW" period tLOW
SDA and SCL rise time
SDA and SCL fall time tF
Start condition hold time
Start condition setup time
Input data hold time
Input data setup time
Output data delay time
Output data hold time
Stop condition setup time
Bus free time
Write cycle time
Noise spike width (SDA and SCL)
WP hold time
WP setup time
WP high period
∗1 Not 100% tested.
(Unless otherwise specified T a=−40 to 85°C, V
∗1
∗1
tHD:DAT
tSU:DAT
tSU:STO
tHIGH:WP
CC
=1.8 to 5.5V)
Fast-mode
2.5V ≤ Vcc ≤ 5.5V
Min.
Typ.
Max.
−
−
fSCL kHz
tHIGH
tR
tHD:STA
tSU:STA
tPD
tDH
tBUF
tWR
tl
tHD:WP
tSU:WP
0.6
1.2
−
−
0.6
0.6
0
100
0.1
0.1
0.6
1.2
−
−
0
0.1
1.0
400
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−−
−−
1.8V ≤ Vcc ≤ 5.5V
Min.
4.0
−
4.7
−
0.3
0.3
4.0
−
4.7
−
−
250
−
0.9
0.2
0.2
−
−
4.7
−
4.7
5
0.1
−
0.1
1.0
Standard-mode
Typ.
−
−
−
−
−
−
−
−
−
−
0
−
−
−
−
−
−
−
−
−
−
0
−
−−
−−
Max.
100
−
−
1.0
0.3
−
−
−
−
3.5
−
−
−µs
5
0.1
−
Unit
µs
µs
µs
µs
µs
µs
ns
ns
µs
µs
µs
ms
µs
ns
µs
µs
5/25
BR24L02-W / BR24L02F-W / BR24L02FJ-W /
Memory ICs
Synchronous d ata timin g
z
SCL
t
HD :
STA t
SDA
(IN)
t
BUF
SDA
(OUT)
BR24L02FV-W / BR24L02FVM-W
t
t
t
F
LOW
PD
t
R
tSU : DAT tHD : DAT
HIGH
t
DH
SCL
SDA
START BIT STOP BIT
Fig.4 SYNCHRONOUS DATA TIMING
SDA data is latched into the chip at the rising edge of SCL clock.
•
Output data toggles at the falling edge of SCL clock.
•
Write cy cle timing
z
SCL
SDA
WRITE DATA (n)
ACKD0
tSU : STOtHD : STAtSU : STA
t
WR
START CONDITIONSTOP CONDITION
Fig.5 WRITE CYCLE TIMING
6/25
BR24L02-W / BR24L02F-W / BR24L02FJ-W /
Memory ICs
WP timing
z
SCL
DATA (n)DATA (1)
BR24L02FV-W / BR24L02FVM-W
SDA
WP
SCL
SDA
WP
D1
D1
t
SU : WP
D0
Fig.6(a) WP TIMING OF THE WRITE OPERATION
DATA (n)DATA (1)
D0
t
HIGH : WP
ACKACK
t
WR
STOP BIT
t
HD : WP
ACKACK
Fig.6(b) WP TIMING OF THE WRITE CANCEL OPERATION
•For the WRITE operation, WP must be “LOW” during the period of time from the rising edge of the clock which takes in
D0 of first byte until the end of t
WR
. ( See Fig. 6 (a) )
During this period, WRITE operation is canceled by setting WP “HIGH”. ( See Fig.6 (b) )
•In the case of setting WP “HIGH” during t
WR
, WRITE operation is stopped in the middle and the data of accessing
address is not guaranteed. Please write correct data again in the case.
7/25
BR24L02-W / BR24L02F-W / BR24L02FJ-W /
Memory ICs
Device oper ation
z
1) Start condition (Recognition of start bit)
• All commands are proceeded by the start condition, which is a HIGH to LOW transition of SDA when SCL is HIGH.
• The device continuously monitors the SDA and SCL lines for the start condition and will not respond to any command
until this condition has been met. (See Fig.4 SYNCHRONOUS DATA TIMING)
2) Stop condition (Recognition of stop bit)
• All communications must be terminated by a stop condition, which is a LOW to HIGH transition of SDA when SCL is
HIGH. (Se e Fig.4 SY NCHRONOUS D AT A TIM ING)
3) Notice about write command
• In the case that stop condition is not executed in WRITE mode, transferred data will not be written in a memory.
4) Device addressing
• Following a START condition, the master output the slave address to be accessed.
• The most sig nifica nt four bi ts of th e slave ad dress ar e the “de vice ty pe ident ifier”, f or thi s devic e it is fixe d as “1010” .
• The next three bit (device address) identify the specified device on the bus.
The device address is defined by the state of A0, A1 and A2 input pins. This IC works only when the device address
inputted from SDA pin correspond to the state of A0, A1 and A2 input pins. Using this address scheme, up to eight
device may be connected to the bus. The last bit of the stream (R/W - - - READ / WRITE) determines the operation to
the performed.
• The last bit of the stream (R/W - - - READ / WRITE) determines the operation to be performed. When set to “1”, a read
operation is selected ; when set to “0”, a write operation is selected.
BR24L02FV-W / BR24L02FVM-W
R / W set to “0” - - - - - - WRITE (including word address input of Random Read)
R / W set to “1” - - - - - - READ
5) Write protect (WP)
When WP pin set to V
When WP pin set to GND (L level), enable to write 256 words (all address).
Either control this pin or connect to GND (or V
A2 A1 A01010 R / W
CC
(H level), wri te pr ote ct is set for 256 w ords (all addr ess) .
CC
). It is inhibited from being left unconnected.
8/25
BR24L02-W / BR24L02F-W / BR24L02FJ-W /
Memory ICs
6) Acknow ledg e
• Acknowledge is a software convention used to indicate successful data transfers.
The transmitter device will release the bus after transmitting eight bits.
(When inputting the slave address in the write or read operation, transmitter is µ-COM. When outputting the data in
the r ead oper atio n, it is t his devi ce.)
• During the ninth clock cycle, the receiver will pull the SDA line LOW to Acknowledge that the eight bits of data has
been received.
(When inputting the slave address in the write or read operation, receiver is this device. When outputting the data in
the read operation, it is µ-COM.)
• The device will respond with an Acknowledge after recognition of a START condition and its slave address (8bit).
• In the WRITE mode, the device will respond with an Acknowledge, after the receipt of each subsequent 8-bit word
(word address and write data).
• In the READ mode, the device will transmit eight bit of data, release the SDA line, and monitor the line for an
Acknowledge.
• If an Acknowledge is detected, and no STOP condition is generated by the master, the device will continue to transmit
the data. If an Acknowledge is not detected, the device will terminate further data transmissions and await a STOP
condition before returning to the standby mode. (See Fig.7 ACKNOWLEDGE RESPONSE FROM RECEIVER)
START CONDITION
(START BIT)
BR24L02FV-W / BR24L02FVM-W
SCL
(From µ−COM)
SDA
(µ−COM
OUTPUT DATA)
SDA
(IC OUTPUT DATA)
189
Acknowledge Signal
(ACK Signal)
Fig.7 ACKNOWLEDGE RESPONSE FROM RECEIVER
9/25
BR24L02-W / BR24L02F-W / BR24L02FJ-W /
Memory ICs
Byte write
z
BR24L02FV-W / BR24L02FVM-W
SDA
LINE
WP
S
T
A
R
T
SLAVE
ADDRESS
10 01
W
R
I
T
E
A0A1A2
R
A
/
C
W
K
Fig.8 BYTE WRITE CYCLE TIMING
WA
7
WORD
ADDRESS
WA
0
A
C
K
D7
DATA
D0
S
T
O
P
A
C
K
• By using this command, the data is programmed into the indicated word address.
• When the master generates a STOP condition, the device begins the internal write cycle to the nonvolatile memory
array.
Page write
z
W
R
I
T
E
A0A1A2
R
/
W
WORD
ADDRESS (n)
WA
7
A
C
K
Fig.9 PAGE WRITE CYCLE TIMING
WA
0
DATA (n)
D7
A
C
K
D0
A
C
K
DATA (n+7)
D0
S
T
O
P
A
C
K
SDA
LINE
WP
S
T
A
R
T
10 01
SLAVE
ADDRESS
• This device is capable of eight byte page write operation.
• When two or more byte data are inputted, the three low order address bits are internally incremented by one after the
receipt of each word. The five higher order bits of the address (WA7 to WA3) remain constant.
• If the master transmits more than eight words, prior to generating the STOP condition, the address counter will
“roll over”, and the previous transmitted data will be overwritten.
10/25
BR24L02-W / BR24L02F-W / BR24L02FJ-W /
Memory ICs
Current read
z
S
T
A
R
T
SLAVE
ADDRESS
R
E
A
D
BR24L02FV-W / BR24L02FVM-W
S
DATA
T
O
P
SDA
LINE
11
00
A2 A1 A0
Fig.10 CURRENT READ CYCLE TIMING
D7 D0
R
A
/
C
W
K
A
C
K
• In case that the p revi ous o perat ion is Ra ndom or C urren t Rea d (w hich incl udes S eque ntia l Rea d r espect ively ), t he
internal address counter is increased by one from the last accessed address (n).
Thus Current Read outputs the data of the next word address (n+1).
If the last command is Byte or Page Write, the internal address counter stays at the last address (n).
Thus Current Read outputs the data of the word address (n).
• If an Acknowledge is detected, and no STOP condition is generated by the master (µ-COM), the device will continue
to transmit the data. [ It can transmit all data (2kbit 256word)
]
• If an Acknowledge is not detected, the device will terminate further data transmissions and await a STOP condition
before returning to the standby mode.
Note) If an Acknowledge is detected with “Low” level, not “High” level, command will become Sequential Read.
So the device transmits the next data, Read is not terminated. In the case of terminating Read, input
Acknowledge with “High” always, then input stop condition.
Random read
z
S
T
A
R
T
SLAVE
ADDRESS
W
R
I
T
E
WORD
ADDRESS(n)
S
T
A
R
T
SLAVE
ADDRESS
R
E
A
D
DATA(n)
S
T
O
P
SDA
LINE
110 0 A2A1A0 A2A1A0
WA
7
R
A
/
C
W
K
Fig.11 RANDOM READ CYCLE TIMING
WA
110 0 D7 D0
0
A
C
K
A
R
C
/
K
W
A
C
K
• Random read operation allows the master to access any memory location indicated word address.
• If an Acknowledge is detected, and no STOP condition is generated by the master (µ-COM), the device will continue to
transmit the data. [ It can transmit all data (2kbit 256word)
]
• If an Acknowledge is not detected, the device will terminate further data transmissions and await a STOP condition
before returning to the standby mode.
Note) If an Acknowledge is detected with “Low” level, not “High” level, command will become Sequential Read.
So the device transmits the next data, Read is not terminated. In the case of terminating Read, input
Acknowledge with “High” always, then input stop condition.
11/25
BR24L02-W / BR24L02F-W / BR24L02FJ-W /
Memory ICs
Sequential r ead
z
S
T
A
R
T
SLAVE
ADDRESS
R
E
A
D
DATA(n)
BR24L02FV-W / BR24L02FVM-W
S
T
DATA(n+x)
O
P
SDA
LINE
1100A2
A1 A0
D7 D7D0 D0
A
R
C
/
K
W
Fig.12 SEQUENTIAL READ CYCLE TIMING
(Current Read)
A
C
K
A
C
K
A
C
K
• If an Acknowledge is detected, and no STOP condition is generated by the master (µ-COM), the device will continue to
transmit the data. [ It can transmit all data (2kbit 256word)
]
• If an Acknowledge is not detected, the device will terminate further data transmissions and await a STOP condition
before returning to the standby mode.
• The Sequential Read operation can be performed with both Current Read and Random Read.
Note) If an Acknowledge is detected with “Low” level, not “High” level, command will become Sequential Read.
So the device transmits the next data, Read is not terminated. In the case of terminating Read, input
Acknowledge with “High” always, then input stop condition.
12/25
BR24L02-W / BR24L02F-W / BR24L02FJ-W /
Memory ICs
Application
z
1) WP effe ctive ti ming
WP is fixed to “H” or “L” usually. But in case of controlling WP to cancel the write command, please pay attention to
[WP effectiv e timi ng] as follows.
During write command input, write command is canceled by controlling WP “H” within the WP cancellation effective
period.
The period from the start condition to the rising edge of the clock which take in D0 of the data (the first byte of the data
for Page Write) is the cancellation invalid period. WP input is don’t care during the period. Setup time for rising edge of
the SCL which takes in D0 must be more than 100ns.
The period from the rising edge of SCL which takes in D0 to the end of internal write cycle (t
effective period. In case of setting WP to “H” during t
accessing address is not guaranteed, so that write correct data again please.
It is not necessary waiting t
WR
, WRITE operation is stopped in the middle and the data of
WR
(5msmax.) after stopping command by WP, because the device is stand by state.
· The rising edge of the clock
which take in D0
BR24L02FV-W / BR24L02FVM-W
WR
) is the cancellation
SDA
WP
S
T
A
ADDRESS
R
T
SCL
SDA D1 D0 ACK
AN ENLARGEMENT
SLAVE
A
C
ADDRESS
K
L
WP cancellation invalid period WP cancellation effective period
WORD
A
C
K
L
A
C
DATAD7 D6 D5 D4 D3 D2 D1 D0
K
L
No data will be written
Fig.13 WP EFFECTIVE TIMING
SCL
SDA D0 ACK
AN ENLARGEMENT
A
A
C
K
L
S
C
T
K
O
L
P
· The rising edge
of SDA
tWR
Stop of the write
operation
Data is not
guaranteed
13/25
BR24L02-W / BR24L02F-W / BR24L02FJ-W /
Memory ICs
2) Software reset
Please execute software reset in case that the device is an unexpected state after power up and / or the command
input need to be reset.
There are som e kinds of s oftwar e reset. Here we sh ow thre e types o f example as follow s.
During dummy clock, please release SDA bus ( tied to V
During that time, the device may pull the SDA line LOW for Acknowledge or outputting or read data.
If the master controls the SDA line HIGH, it will conflict with the device output LOW then it makes a current overload.
It may cause instantaneous power down and may damage the device.
CC
DUMMY CLOCK × 14 START × 2
BR24L02FV-W / BR24L02FVM-W
by pull up resistor ).
SCL
SDA
SDA
12 1413
Fig.14-(a) DUMMY CLOCK × 14 + START + START
START START
Fig.14-(b) START+ DUMMY CLOCK × 9 + START
123 789SCL
DUMMY CLOCK × 9
12 89SCL
START × 9
COMMAND
COMMAND
COMMAND
COMMAND
COMMAND
SDA
COMMAND starts with start condition.
∗
COMMAND
Fig.14-(c) START × 9
14/25
BR24L02-W / BR24L02F-W / BR24L02FJ-W /
Memory ICs
3) Acknowledge polling
Since the device ignore all input commands during the internal write cycle, no ACK will be returned.
When the master send the next command after the wire command, if the device returns the ACK, it means that the
program is completed. If no ACK id returned, it means that the device is still busy.
By using Acknowledge polling, the waiting time is minimized less than t
In case of operating Write or Current Read right after Write, first, send the slave address (R / W is “HIGH” or “LOW”
respectively). After the device returns the ACK, continue word address input or data output respectively.
THE FIRST WRITE COMMAND
BR24L02FV-W / BR24L02FVM-W
WR
=5ms.
During the internal write cycle,
no ACK will be returned.
(ACK=HIGH)
• • •
S
T
A
R
T
WRITE COMMAND
S
T
A
ADDRESS
R
T
SLAVE
t
WR
S
T
O
P
A
C
K
H
S
T
SLAVE
A
ADDRESS
R
T
S
T
SLAVE
A
ADDRESS
R
T
A
C
K
H
THE SECOND WRITE COMMAND
A
C
WORD
K
ADDRESS
L
S
T
SLAVE
A
ADDRESS
R
T
t
WR
A
C
K
L
DATA
A
C
• • •
K
H
A
S
C
T
K
O
L
P
After the internal write cycle
is completed ACK will be returned
(ACK=LOW). Then input next
Word Address and data.
Fig.15 SUCCESSIVE WRITE OPERATION BY ACKNOWLEDGE POLLING
15/25
BR24L02-W / BR24L02F-W / BR24L02FJ-W /
Memory ICs
4) Command ca ncell ation by start a nd stop c onditi on
During a command input, it is canceled by the successive inputs of start condition and stop condition. (Fig.4)
But during ACK or data output, the device may output the SDA line LOW. In such cases, operation of start and stop
condition is impossible, so that the reset can’t work. Execute the software reset in the cases. (See Page14)
Operating the command cancel by start and stop condition during the command of Random Read or Sequential Read
or Current Read, internal address counter is not confirmed.
Therefore operation of Current Read after this in not valid. Operate a Random Read in this case.
SCL
BR24L02FV-W / BR24L02FVM-W
SDA
Fig.16 COMMAND CANCELLATION BY START AND STOP CONDITION
DURING THE INPUT OF SLAVE ADDRESS
1100
START
CONDITION
STOP
CONDITION
16/25
BR24L02-W / BR24L02F-W / BR24L02FJ-W /
Memory ICs
5) Notes for power supply
CC
V
rises through the low voltage region in which internal circuit of IC and the controller are unstable, so that device
may not work pr operly due to an in compl ete rese t of int ernal circ uit.
T o pr event th is, the d evice h as the fea ture of P.O.R . and LV
In the case of power up, keep the following conditions to ensure functions of P.O.R and L V
(1) It is necessary to be “SDA=H” and “SCL=’L’ or ‘H’ ”.
(2) Follow the recommended conditions of t
(3) Prevent SDA and SCL from being “Hi-Z”.
In case that condition 1. and / or 2. cannot be met, take following actions.
A) Unable to keep co ndition 1. (SDA is “LO W” duri ng power up .)
→
R
OFF
, t
, Vbot for the function of P.O.R. durning power up.
t
R
CC
V
t
OFF
0
VCC rising wave from
Control SDA, SC L to be “HIGH” a s figur e below .
BR24L02FV-W / BR24L02FVM-W
CC
.
CC
.
R
, t
OFF
, Vbot
Vbot
Below 0.3V
Below 0.2V
Vbot
Recommended conditions of t
t
R
Below 10ms
Below 100ms
t
OFF
Above 10ms
Above 10ms
V
CC
SCL
SDA
After VCC becomes stable
a) SCL="H" and SDA="L"
B) Unable to keep condition 2.
After power becomes stable, execute software reset. (See page14 )
→
C) Unable to keep condition 1 and 2.
Follow the instruction A first, then the instruction B.
→
t
LOW
After VCC becomes stable
t
DH
t
SU:DAT
b) SCL="L" and SDA="L"
t
SU:DAT
17/25
BR24L02-W / BR24L02F-W / BR24L02FJ-W /
Memory ICs
• LVCC circuit
CC
LV
(Typ.=1.2V), write operation is inhibited.
6) I / O circuit
• Pull up resister of SDA pin
The pull up resister is needed because SDA is NMOS open drain. Decide the value of this resister (R
by considering V
If large R
circuit inhibit write operation at low voltage, and prevent an inadvertent write. Below the LVCC voltage
IL
, IL characteristics of a controller which control the device and VOH, IOL charact erist ics of t he dev ic e.
PU
is chosen, clock frequency need to be slow. In case of small RPU, the operating current increases.
BR24L02FV-W / BR24L02FVM-W
PU
) properly,
• Maximum of R
PU
Maximum of RPU is determined by following factor.
① SDA rise time determined by R
And the other timing must keep the conditions of AC spec.
② When SDA bus is HIGH, the voltage A of SDA bus determined by a total input leak (I
connected to the bus and RPU must be enough higher than input HIGH level of a controller and the device,
including noise margin 0.2 VCC.
VCC − ILRPU − 0.2VCC ≥ V
0.8VCC − V
RPU ≤
Examples : When V
IL
According to
0.8×3−0.7×3
R
PU
≤
≤ 300 [kΩ]
PU
and the capacitance of bus line (CBUS) must be less than TR.
IH
IH
CC
=3V IL=10µA VIH=0.7V
2
−6
10×10
MICRO
COMPUTER
CC
R
PU
A
IL IL
THE CAPACITANCE OF
BUS LINE (CBUS)
L
) of the a ll devi ces
BR24LXX
SDA PIN
18/25
BR24L02-W / BR24L02F-W / BR24L02FJ-W /
Memory ICs
BR24L02FV-W / BR24L02FVM-W
• The mini mum v alu e R
PU
The minimum value of RPU is determined by following factors.
① Meet the condition that V
VCC − V
OL
≤ I
R
PU
② V
RPU ≥
OLMAX
(=0.4V) must be lower than the input LOW level of the controller and the EEPROM including
recommended noise margin (0.1 VCC).
Examples : V
OL
VCC − V
OL
I
OL
V
OLMAX
≤ VIL − 0.1V
CC
=3V, VOL=0.4V, IOL=3mA, the VIL of the controller and the EEPROM is VIL=0.3V
According to
and
OLMAX
CC
1
=0.4V , I
RPU ≥
V
V
OLMAX
≥ 867 [Ω]
OL
=0.4[V]
IL
=0.3×3
=0.9[V]
=3mA when the device output low on SDA line.
3−0.4
−3
3×10
CC
so that condition is met
2
• Pull up r esis ter o f SC L pin
In the case that SCL is controlled by CMOS output, the pull up resister of SCL is not needed.
But in the case that there is a timing at which SCL is Hi-Z, connect SCL to V
CC
with pull u p resist er .
Several ∼ several dozen kΩ is recommended as a pull up resister, which is considered with the driving ability of the
output port of the controller.
7) Connections of A0, A1, A2, WP pin
• Connections of device address pin (A0, A1, A2)
The state of device address PIN are compared with the device address send by the master, then one of the devices
which are connected to the identical bus is selected. Pull up or down these pins, or connect them to V
CC
or GND .
Pins which is not used as device address (N.C. PIN) may be either HIGH, LOW, and Hi-Z.
The ty pe of the devic e whi ch hav e N.C. PIN BR24L16 / F / FJ / FV / FVM-W A0, A1, A2
BR24L08 / F / FJ / FV / FVM -W A0, A1
BR24L04 / F / FJ / FV / FVM -W A0
• Connections of WP pin
The WP input allows or inhibits write operations. When WP is HIGH, only READ is available and WRITE to any
address is inhibited. Both Read and Write are available when WP is LOW.
In the case that the device is used as a ROM, it is recommended that WP is pulled up or connected to V
CC
.
In the case that both READ and WRITE are operated, WP pin must be pulled down or connected to GND or
controlled.
19/25
BR24L02-W / BR24L02F-W / BR24L02FJ-W /
Memory ICs
BR24L02FV-W / BR24L02FVM-W
8) Notes for n oise on V
CC
• About by pass c apac itor
Noise and surges on power line may cause the abnormal function. It is recommended that the bypass capacitors
(0.1µF) are attached on the V
CC
and GND line beside the device.
The attachment of bypass capacitors on the board near by connector is also recommended.
PRINT BASE
IC
GND V
CC
capacitor 10 to 100µF
capacitor 0.01 to 0.1µF
9) The notice about the connection of controller
• About R
S
The open drain interface is recommended for SDA port in I2CBUS. But, in the case that Tri-state CMOS interface is
applied to SDA, insert a series resister R
S
between SDA pin of the device and a pull up resister RPU. It limits the
current from PM OS of contro ller to NMOS of EEPROM.
S
R
also protect s SDA pin fr om surg es. Ther efore, RS is able to be used though SDA port is open drain.
SCL
SDA
R
CONTROLLER EEPROM
"H" OUTPUT OF
CONTROLLER
The "H" output of controller
and the "L" output of EEPROM may cause
current overload to SDA line.
PU
R
S
ACK
"L" OUTPUT OF
EEPROM
20/25
BR24L02-W / BR24L02F-W / BR24L02FJ-W /
Memory ICs
BR24L02FV-W / BR24L02FVM-W
The maxi mum va lue of R
•
S
The maximum value of RS is determined by following factors.
c SDA rise tim e det ermin ed by R
PU
and the capacitance of bus line (CBUS) of SDA must be less than tR. And the
other timing must also keep the conditions of the AC timing.
d When the device outputs LOW on SDA line, the voltage of the bus A determined by R
lower than the inputs LOW level of the controller, including recommended noise margin (0.1V
(VCC−VOL) × R
RPU+R
RS ≤ × R
Examples : when V
According to
RS ≤ × 20×10
S
OL
+0.1VCC ≤ V
+ V
S
VIL−VOL−0.1V
1.1VCC−V
CC
=3V, VIL=0.3VCC, VOL=0.4V, RPU=20kΩ
CC
IL
IL
PU
2
0.3×3−0.4−0.1×3
3
1.1×3−0.3×3
≤ 1.67 [kΩ]
V
CC
A
R
PU
R
S
I
OL
V
OL
CAPACITANCE OF
BUS LINE (CBUS)
PU
and RS must b e
CC
).
V
IL
CONTROLLER EEPROM
• The minimum value of R
S
The minimum value of RS is determined by the current overload due to the conflict on the bus.
The current overload may cause noise on the power line and instantaneous power down.
The followin g condit ions m ust be met , where Ι is the maximum permissible current.
The maximum permissible current depends on V
CC
line impedance and so on. It need to be less than 10mA for
EEPROM.
V
CC
≤ Ι
R
S
V
CC
RS ≥
Ι
R
PU
R
S
MAXIMUM
Ι
"H" OUTPUT
CONTROLLER EEPROM
CURRENT
"L" OUTPUT
Examples : When V
R
S
≥
10×10
≥ 300 [Ω]
CC
=3V, Ι=10mA
3
−3
21/25
BR24L02-W / BR24L02F-W / BR24L02FJ-W /
Memory ICs
10) The special character DATA
The followin g charac teri stic data are typ v alue.
BR24L02FV-W / BR24L02FVM-W
6
5
(V)
IH
4
3
SPEC
2
H INPUT VOLTAGE : V
1
0
01 34 65
2
SUPPLY VOLTAGE : VCC (V)
Fig.17 High input voltage VIH
(A0,A1,A2,SCL,SDA,WP)
1
0.8
0.6
0.4
0.2
L OUTPUT VOLTAGE : VOL (V)
0
01 34 65
L OUTPUT CURRENT : IOL (mA)
SPEC
Ta=85°C
2
Ta=25°C
Ta=85°C
Ta=−40°C
Ta=25°C
Ta=−40°C
6
5
(V)
IL
4
3
2
L INPUT VOLTAGE : V
1
0
01 34 65
1.2
1
0.8
0.6
0.4
INPUT LEAK CURRENT : ILI (µA)
0.2
0
01 34 65
Ta=85°C
Ta=−40°C
Ta=25°C
SPEC
2
SUPPLY VOLTAGE : VCC (V)
Fig.18 Low input voltage VIL
(A0,A1,A2,SCL,SDA,WP)
SPEC
Ta=85°C
Ta=25°C
Ta=−40°C
2
SUPPLY VOLTAGE : VCC (V)
1
0.8
0.6
0.4
SPEC
0.2
L OUTPUT VOLTAGE : VOL (V)
0
01 34 65
L OUTPUT CURRENT : IOL (mA)
Fig.19 Low output voltage VOL−I
(VCC=1.8V)
1.2
1
0.8
0.6
0.4
0.2
OUTPUT LEAK CURRENT : ILO (µA)
0
01 34 65
SUPPLY VOLTAGE : VCC (V)
Ta=85°C
2
2
SPEC
Ta=25°C
Ta=−40°C
Ta=85°C
Ta=25°C
Ta=−40°C
OL
Fig.20 Low output voltage VOL−I
(VCC=2.5V)
2.5
1 (mA)
2
CC
f
SCL
=400kHz
DATA=AAh
1.5
AT WRITING : I
1
Ta=25°C
Ta=85°C
Ta=−40°C
0.5
CURRENT CONSUMPTION
0
01 34 65
2
SUPPLY VOLTAGE : VCC (V)
Fig.23 Write operating current
CC
1 (f
SCL
I
SPEC
=400kHz)
OL
0.6
(mA)
2
0.5
CC
0.4
0.3
AT READING : I
0.2
0.1
CURRENT CONSUMPTION
0
Fig.21 Input leakage current ILI
(A0,A1,A2,SCL,WP)
SPEC
f
SCL
=400kHz
DATA=AAh
Ta=85°C
01 34 65
2
SUPPLY VOLTAGE : VCC (V)
Ta=25°C
Ta=−40°C
Fig.24 Read operating current
CC
2 (f
SCL
=400kHz)
I
Fig.22 Output leakage current
2.5
1 (mA)
2
CC
f
SCL
=100kHz
DATA=AAh
1.5
AT WRITING : I
1
Ta=−40°C
0.5
CURRENT CONSUMPTION
0
01 34 65
SUPPLY VOLTAGE : VCC (V)
Fig.25 Write operating current
CC
I
I
LO
2
1 (f
(SDA)
Ta=25°C
Ta=85°C
SCL
SPEC
=100kHz)
22/25
BR24L02-W / BR24L02F-W / BR24L02FJ-W /
Memory ICs
BR24L02FV-W / BR24L02FVM-W
0.6
(mA)
0.5
2
CC
f
SCL
=100kHz
0.4
DATA=AAh
0.3
AT READING : I
0.2
Ta=85°C
0.1
CURRENT CONSUMPTION
0
01 34 65
2
SUPPLY VOLTAGE : VCC (V)
Fig.26 Read operating current
CC
2 (f
SCL
I
5
4
(µs)
HIGH
SPEC1 : FAST-MODE
SPEC2 : STANDARD-MODE
3
2
Ta=−40°C
Ta=25°C
1
Ta=85°C
DATA CLK H TIME : t
0
01 34 65
SUPPLY VOLTAGE : VCC (V)
SPEC2
2
SPEC
Ta=−40°C
=100kHz)
SPEC1
Ta=25°C
2.5
2
(µA)
SB
1.5
1
0.5
STANDBY CURRENT : I
0
01 34 65
5
4
(µs)
LOW
3
2
1
DATA CLK L TIME : t
0
01 34 65
Ta=85°C
2
SUPPLY VOLTAGE : VCC (V)
Fig.27 Standby current I
SPEC2
SPEC1 : FAST-MODE
SPEC2 : STANDARD-MODE
Ta=85°C
Ta=25°C
Ta=−40°C
2
SUPPLY VOLTAGE : VCC (V)
SPEC
SPEC1
Ta=25°C
Ta=−40°C
SB
10000
1000
(kHz)
SCL
100
SPEC2
10
SCL FREQUENCY : f
1
01 34 65
2
SUPPLY VOLTAGE : VCC (V)
Fig.28 Clock frequency f
5
(µs)
HD:STA
4
SPEC1 : FAST-MODE
SPEC2 : STANDARD-MODE
3
2
Ta=−40°C
1
Ta=25°C
Ta=85°C
0
START CONDITION HOLD TIME : t
01 34 65
2
SUPPLY VOLTAGE : VCC (V)
SPEC2
SPEC1
Ta=85°C
Ta=25°C
Ta=−40°C
SPEC1
SCL
Fig.29 Data clock "H" period t
6
(µs)
SU:STA
5
4
SPEC1 : FAST-MODE
SPEC2 : STANDARD-MODE
SPEC2
3
2
Ta=−40°C
1
Ta=25°C
Ta=85°C
0
01 34 65
START CONDITION SET UP TIME : t
SUPPLY VOLTAGE : VCC (V)
SPEC1
2
Fig.32 Start condition setup time
SU:STA
t
HIGH
Fig.30 Data clock "L" period t
50
(ns)
0
SPEC1 : FAST-MODE
HD:DAT
SPEC2 : STANDARD-MODE
−50
−100
−150
INPUT DATA HOLD TIME : t
−200
01 34 65
SUPPLY VOLTAGE : VCC (V)
Fig.33 Input data hold time
Ta=85°C
Ta=25°C
Ta=−40°C
2
HD:DAT
t
SPEC1,2
(HIGH)
LOW
Fig.31 Start condition hold time
50
(ns)
0
SPEC1 : FAST-MODE
HD:DAT
SPEC2 : STANDARD-MODE
−50
−100
−150
Ta=25°C
INPUT DATA HOLD TIME : t
−200
01 34 65
SUPPLY VOLTAGE : VCC (V)
Fig.34 Input data hold time
HD:STA
t
2
t
SPEC1,2
Ta=−40°C
HD:DAT
Ta=85°C
(LOW)
23/25
BR24L02-W / BR24L02F-W / BR24L02FJ-W /
Memory ICs
BR24L02FV-W / BR24L02FVM-W
300
(ns)
SPEC1 : FAST-MODE
200
SU:DAT
SPEC2 : STANDARD-MODE
100
0
Ta=85°C
Ta=25°C
−100
INPUT DATA SET UP TIME : t
−200
Ta=−40°C
01 34 65
2
SUPPLY VOLTAGE : VCC (V)
Fig.35 Input data setup time
SU:DAT
(HIGH)
t
4
(µs)
PD
3
SPEC1 : FAST-MODE
SPEC2 : STANDARD-MODE
2
Ta=−40°C
Ta=25°C
Ta=85°C
1
SPEC2
SPEC1
OUTPUT DATA DELAY TIME : t
0
01 34 65
2
SUPPLY VOLTAGE : VCC (V)
SPEC2
SPEC2
SPEC1
SPEC1
300
(ns)
SPEC1 : FAST-MODE
200
SU:DAT
SPEC2 : STANDARD-MODE
100
0
Ta=25°C
−100
INPUT DATA SET UP TIME : t
−200
01 34 65
SUPPLY VOLTAGE : VCC (V)
Fig.36 Input data setup time
4
(µs)
DH
3
SPEC1 : FAST-MODE
SPEC2 : STANDARD-MODE
2
Ta=85°C
Ta=25°C
Ta=−40°C
1
SPEC2
OUTPUT DATA HOLD TIME : t
SPEC1
0
01 34 65
SUPPLY VOLTAGE : VCC (V)
2
SU:DAT
t
2
Ta=85°C
Ta=−40°C
(LOW)
SPEC2
SPEC2
SPEC1
SPEC1
4
(µs)
PD
3
SPEC1 : FAST-MODE
SPEC2 : STANDARD-MODE
2
Ta=85°C
Ta=25°C
Ta=−40°C
1
SPEC2
SPEC1
OUTPUT DATA DELAY TIME : t
0
01 34 65
SUPPLY VOLTAGE : VCC (V)
Fig.37 Output data delay time
4
(µs)
DH
3
SPEC1 : FAST-MODE
SPEC2 : STANDARD-MODE
2
Ta=−40°C
Ta=25°C
Ta=85°C
1
SPEC2
SPEC1
OUTPUT DATA HOLD TIME : t
0
01 34 65
SUPPLY VOLTAGE : VCC (V)
SPEC2
SPEC1
2
PD
0
t
SPEC2
SPEC1
2
Fig.38 Output data delay time
PD
1
t
5
(µs)
SU:STO
4
3
SPEC1 : FAST-MODE
SPEC2 : STANDARD-MODE
SPEC2
2
Ta=85°C
1
Ta=25°C
Ta=−40°C
0
STOP CONDITION SET UP TIME : t
01 34 65
SUPPLY VOLTAGE : VCC (V)
SPEC1
2
Fig.41 Stop condition setup time
SU:STO
t
Fig.39 Output data hold time
5
(µs)
4
BUF
SPEC1 : FAST-MODE
SPEC2 : STANDARD-MODE
3
2
Ta=−40°C
1
Ta=25°C
BUS OPEN TIME
Ta=85°C
BEFORE TRANSMISSION : t
0
01 34 65
DH
0
t
SPEC2
SPEC1
2
SUPPLY VOLTAGE : VCC (V)
Fig.42 BUS free time t
BUF
Fig.40 Output data hold time
DH
1
t
6
(ms)
5
WR
4
3
2
1
SPEC1 : FAST-MODE
SPEC2 : STANDARD-MODE
0
01 34 65
INTERNAL WRITING CYCLE TIME : t
2
SUPPLY VOLTAGE : VCC (V)
Fig.43 Write cycle time t
SPEC1,2
Ta=−40°C
Ta=25°C
Ta=85°C
WR
24/25
BR24L02-W / BR24L02F-W / BR24L02FJ-W /
Memory ICs
BR24L02FV-W / BR24L02FVM-W
0.6
SPEC1 : FAST-MODE
SPEC2 : STANDARD-MODE
0.5
0.4
(SCL H) (µs)
I
Ta=25°C
0.3
0.2
EFFECTIVE TIME : t
0.1
NOISE REDUCTION
0
01 34 65
2
SUPPLY VOLTAGE : VCC (V)
Fig.44 Noise spike width
I
(SCL H)
t
0.6
SPEC1 : FAST-MODE
SPEC2 : STANDARD-MODE
0.5
0.4
(SDA L) (µs)
I
0.3
Ta=25°C
0.2
EFFECTIVE TIME : t
0.1
NOISE REDUCTION
0
01 34 65
2
SUPPLY VOLTAGE : VCC (V)
Ta=−40°C
Ta=85°C
SPEC1,2
Ta=85°C
SPEC1,2
Ta=−40°C
0.6
SPEC1 : FAST-MODE
SPEC2 : STANDARD-MODE
0.5
0.4
(SCL L) (µs)
I
0.3
0.2
Ta=25°C
EFFECTIVE TIME : t
0.1
NOISE REDUCTION
0
01 34 65
2
SUPPLY VOLTAGE : VCC (V)
Fig.45 Noise spike width
0.2
(µs)
0
SPEC1 : FAST-MODE
SU:WP
SPEC2 : STANDARD-MODE
−0.2
−0.4
WP SET UP TIME : t
Ta=25°C
−0.6
01 34 65
2
SUPPLY VOLTAGE : VCC (V)
Ta=−40°C
Ta=85°C
I
(SCL L)
t
SPEC1,2
Ta=85°C
SPEC1,2
Ta=−40°C
0.6
SPEC1 : FAST-MODE
SPEC2 : STANDARD-MODE
0.5
0.4
(SDA H) (µs)
I
Ta=25°C
0.3
0.2
EFFECTIVE TIME : t
0.1
NOISE REDUCTION
0
01 34 65
2
SUPPLY VOLTAGE : VCC (V)
Fig.46 Noise spike width
1.2
(µs)
1
HIGH:WP
0.8
SPEC1 : FAST-MODE
SPEC2 : STANDARD-MODE
0.6
0.4
0.2
WP EFFECTIVE TIME : t
0
01 34 65
SUPPLY VOLTAGE : VCC (V)
I
(SDA H)
t
SPEC1,2
2
Ta=−40°C
Ta=85°C
SPEC1,2
Ta=−40°C
Ta=25°C
Ta=85°C
Fig.47 Noise spike width
I
(SDA L)
t
Fig.48 WP setup time t
SU:WP
Fig.49 WP high period t
HIGH:WP
25/25
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