Rainbow Electronics BR24C21FV User Manual

BR24C21 / BR24C21F / BR24C21FJ / BR24C21FV

Memory ICs

ID ROM for CRT display

BR24C21 / BR24C21F / BR24C21FJ / BR24C21FV

The BR24C21 series are 1kbits serial EEPROMs and support DDC1TM and DDC2TM interfaces for PLUG&PLAY displays.

!Features

1) 128 x 8 bits serial EEPROM

2) Operating voltage range (2.5V∼5.5V)

3) Completely implements DDC1

TM

/ DDC2TM interface

for monitor identification Transmit-Only Mode Recovery Mode Bi-directional Mode

4) Page write function : 8 bytes

5) Low current consumption Active (at 5V) : 1.5mA (Typ.) Standby (at 5V) : 10µA (Typ.)

6) DATA security Write enable feature Inhibit to WRITE at low Vcc

7) Compact packages

8) High reliability fine pattern CMOS technology

9) Rewriting possible up to 100,000 times

10) Data can be stored for ten years without corruption

11) Noise filters at SCL, SDA and VCLK pins

!!!!Absolute maximum ratings (Ta=25°C)

Parameter Symbol Limits Unit

V

Supply voltage −0.3

Power disssipation

Storage temperature range −65 Operating temperature range Terminal voltage

∗1 Degradation is done at 8.0mW/°C for operation above 25°C. ∗2 Degradation is done at 4.5mW/°C for operation above 25°C. ∗3 Degradation is done at 3.5mW/°C for operation above 25°C.

CC

Pd

Tstg Topr

−

450(SOP-J8)

350(SSOP-B8)

−0.3~VCC+0.3

!!!!Recommended operating conditions (Ta=25°C)

Parameter Symbol Limits Unit Supply voltage Input voltage V

CC

V

IN

2.5~5.5

~

+6.5 V

800(DIP8)

450(SOP8)

~

+125

−40

~

+85

0~V

CC

∗1 ∗2 ∗2 ∗3

mW

°C °C

V

V V

BR24C21 / BR24C21F / BR24C21FJ / BR24C21FV

Memory ICs

!!!!Block diagram

N.C.

1

1kbits EEPROM array

VCC8

N.C. 2

N.C. 3

GND 4

!!!!Pin assignment

7bits

Address decoder

7bits

Slave word

address register

STOPSTART

Control logic

High voltage generator Vcc level detecter

SCL

VCC

VCLK

SDA

BR24C21 BR24C21F BR24C21FJ BR24C21FV

1234

N.C.

GND

8bits

Data

VCLK7

register

6 SCL

ACK

SDA5

5678

!!!!Pin descriptions

Pin name Function

1 2 3 4

5 6 7 8

∗ An open drain output requires a pull-up resistor.

N.C. N.C. N.C.

GND SDA

SCL

VCLK

V

CC

I / OPin No.

−

No connection

−

No connection

−

No connection Ground (0V)

−

Slave and word address,

I / O

serial data input, serial data output

I

Serial clock input for Bi-directional Mode Clock input (Transmit-Only Mode)

I

Write enable (Bi-directional Mode)

−

Power supply

∗

BR24C21 / BR24C21F / BR24C21FJ / BR24C21FV

Memory ICs

!!!!Electrical characteristics (Unless otherwise noted, Ta=−40∼85°C, VCC=2.5∼5.5V)

Parameter Symbol Min. Typ. Max. Unit Conditions

"HIGH" input volatge1 "LOW" input volatge1 "HIGH" input volatge2 "LOW" input volatge2 "LOW" input volatge3 "LOW" output volatge Input leakage current I Output leakage current I Operating current I Standby current

∗1 Transmit-Only Mode…After the power is on, the BR24C21, BR24C21F, BR24C21FJ and BR24C21FV are in Standby state without providing the clock on the VCLK pin.

Bi-directional Mode…The BR24C21, BR24C21F, BR24C21FJ and BR24C21FV are in Standby state after each command is porformed.

0.7V

IH1

V V

IL1

V

IH2

V

IL2

V

IL3

V

OL

LI

LO

CC

I

SB

After the VCLK pin is provided the clock, the device is switched from Standby to Transmit-Only Mode, and the operating current runs.

CC

−−

2.0

−−

−1

−

−1 −

−

10 100

CC

0.3V

0.8 V

0.2V

CC

0.4 V 1 µA 1 µA

3.0 mA

µA

V V V

V

SCL, SDA SCL, SDA

VCLK VCLK,

V

CC≥

4.0V

VCLK,

V

CC<

4.0V

SDA, I

OL

=3.0mA

SCL,

VCLK,

VIN=0V~V

OUT

=0V~V

SCL

=400kHz

CC

SDA, V V

CC

=5.5V, f

V

CC

=5.5V, SDA=SCL=VCC,

CC

=GND

∗1

VCLK

!!!!

Operating timing characteristics

(Unless otherwise noted, Ta=−40∼85°C, VCC=2.5∼5.5V)

Parameter Symbol

SCL frequency Data clock "HIGH" time Data clock "LOW" time t

SDA/SCL rise time t SDA/SCL fall time t Start condition hold time Start condition setup time Input data hold time Input data setup time Output data delay time (SCL) t Stop condition setup time Bus open time before start or transfer t

Noise erase valid time (SCL and SDA) t <Transmit-Only Mode> Output data delay time (VCLK) t VCLK "HIGH" time VCLK

"LOW" time t VCLK setup time t VCLK hold time t Mode transition time t Transmit-Only powerup time t Noise erase valid time (VCLK) t

t

t t t

t

HD

SU

HD

SU

SCL

f

t

HIGH

LOW

R

: STA

: STA : DAT : DAT

PD

: STO

BUF

t

WR

VPD

VHIGH

t

VLOW

VSU

VHD

VHZ

VPU

VI

Fast-mode

Vcc=2.5~5.5V

Min.

Typ.

Max.

−

400

0.6

−

1.3

−

F

−

0.6

0.6 0

100

−

0.6

1.3

−

I

−

0.6

1.3 0

0.6

−

0

−

0.3

−

0.3

−

0.9

−

10

−

0.1

1.0 −

−

−−

−

− 0.5

−

0.1

−

Standard-mode

Vcc=2.5~5.5V

Min.

Typ.

−

4.0

−

4.7

−

4.0

−

4.7

−

0

−

250

−

4.0

−

4.7

−

4.0

−−

4.7

−

0

−

4.0

−

− 1.0

0

−

Max.

100

−

1.0

0.3

−

3.5

−

10 msInternal write cycle time

0.1

2.0

−

0.1

Unit

kHz

µs µs µs µs µs µs

ns ns

µs µs µs

µs

µs µs µs µs µs µs µs µs

BR24C21 / BR24C21F / BR24C21FJ / BR24C21FV

Memory ICs

!!!!Timing charts

SYNCHRONOUS DATA TIMING

t

HIGH

SCL

SDA

(IN)

SDA

(OUT)

t

R

t

HD :

STA t

t

BUF

tSU : DAT tHD : DAT

t

F

LOW

t

PD

SCL

SDA

START BIT STOP BIT

Fig.7

•SDA data is latched into the chip at the rising edge of the SCL clock.

•Output data toggles at the falling edge of the SCL clock.

WRITE CYCLE TIMING

SCL

SDA

WRITE DATA

(n)

ACKD0

Fig.8

WRITE ENABLE TIMING

START BIT

STOP BIT

tSU : STOtHD : STAtSU : STA

t

WR

START CONDITIONSTOP CONDITION

SCL

SDA

VCLK

t

VSU

WRITE COMMAND

Fig.9

t

VHD