Rohm's BD48XXG/FVE and BD49XXG/FVE are series of high-accuracy, low-power VOLTAGE DETECTOR ICs
with a CMOS process. For flexible choice according to the application, BD48XXG/FVE series with N channel
open drain output and BD49XXG/FVE series with CMOS output are available in 38 voltage types from 2.3 V to
6.0 V in steps of 0.1 V in different packages, totaling 152 models.
Applications
Every kind of appliances with microcontroller and logic circuit
Features
1) Detection voltage: 0.1V step line-up 2.3 to 6.0V (Typ.)
Pin layout of VSOF5(EMP5) and SSOP5(SMP5C2) is different as shown below. (Fig.1, Fig.2)
When used as replacement, please consider the difference. (The detail of packages is shown at P14.)
BD48XXG/BD49XXG
BD48XXFVE/BD49XXFVE
1VOUTVDD
2SUB
3N.C.GND
VSOF5
(EMP5)
Package
1.2mm
5
1.6mm
4
VDD
GND
1VOUTN.C.
SSOP5
(SMP5C2)
2
Package
3
1.6mm
5
2.9mm
4 N.C.
Fig.1Fig.2
(Note) Connect SUB pin with GND pin.
Rev.A
2/15
BD48XXG/FVE
Voltage detectors
Block diagram
Two output types can be used. One is BD48XXG/FVE (Fig.3) of open drain output type, and the other is
BD49XXG/FVE (Fig.4) of CMOS output type.
BD48XXG/FVE : Open drain outputBD49XXG/FVE : CMOS output
VDD
VDD
BD49XXG/FVE
Vref
GND
VOUT
Vref
GND
Fig.4Fig.3
VOUT
Absolute maximum rating (Ta=25°C)
To prevent the functional deterioration or thermal damage of semiconductor devices and ensure their service
life and reliability, they must be designed and reviewed in such a way that the absolute maximum rating can
not be exceeded in any cases or even at any moment.
ParameterSymbolUnit
Power supply voltage
Output
voltage
Power dissipation SSOP5 (SMP5C2)
Power dissipationVSOF5 (EMP5)
Nch Open drain output
CMOS output
*
*
*
*
Operating temperature
Storage temperature
*1 Derating : 1.5mW/°C for operation above Ta=25°C
*2 Derating : 1.0mW/°C for operation above Ta=25°C
*3 When only IC is used.
VDD – GND
VOUT
1
3
2
3
GND – 0.3 to VDD + 0.3
Pd
Pd
Topr
Tstg
Limits
– 0.3 to + 10
GND – 0.3 to + 10
150
100
– 40 to + 85
– 55 to + 125
V
V
mW
mW
°C
°C
• Power supply voltage
This voltage is the applied voltage between VDD and GND. The applied voltage should not exceed the
indicated value.
• Output voltage
VOUT pin voltage should not exceed the indicated value. For Nch open drain output type, VDD applied
voltage and VOUT pin H output voltage can be used independently. Both of them should not exceed the
each indicated value.
• Operating temperature range
The circuit function is guaranteed within the temperature range. However, the operating characteristics
are different from that of Ta=25°C. If they are any questions about the extent of guarantee of circuit
functions in this operating temperature range, please ask for more technical information.
• Storage temperature range
This IC can be stored up to this temperature range without deterioration of characteristics. However,
an abrupt thermal shock of extreme temperature fluctuations may cause the deterioration of characteristics.
Rev.A
3/15
BD48XXG/FVE
Voltage detectors
Power dissipation
Power consumption of the IC
Circuit current at ON/OFF is very small. Power consumption in output depends on each load connected with
VOUT pin. Please note that total power consumption must be within a power dissipation range in the secure
area of the entire operating temperature. Power dissipation of these packages; SSOP5 (SMP5C2) package
(BD48XXG/BD49XXG) Fig.5, and VSOF5 (EMP5) package (BD48XXFVE/BD49XXFVE) Fig.6 is shown below.
When it is used in the ambient temperature of (Ta)=25°C and more, make reference to each thermal derating
characteristics of used package. Both Fig.5 and Fig.6 show these characteristic when only IC is used.
Electrical characteristics (Unless otherwise noted; Ta=-25°C to 85°C)
*1 Operation is guaranteed forTa=25°C.
*2 TPLH : VDD=(VS typ.–0.5V) (VS typ.+0.5V).
Note) RL is not necessary for CMOS output type.
Note) Minimum operating voltage
VOUT output becomes inconsistent if the VDD is equal to or lower than the operating limit voltage. It goes open, H, or L.
Note) Hysteresis voltage=(Reset release voltage)-(Reset detection voltage) [V]
Ileak
—
0.80
0.85
0.90
—
2.40
2.55
2.70
—
0.1
VDD=Vs+2V
A
*1
>
-
mAIOL"L" output current
VDS=0.5V, VDD=2.4V (VS 2.7V)
VDS=0.5V, VDD=4.8V
mAIOH"H" output current
VDS=0.5V, VDD=6.0V VS=4.3 to 5.2V
VDS=0.5V, VDD=8.0V VS=5.3 to 6.0V
VDD=VDS=10V *1
A
*2
VS=3.2 to 4.2V
VS=4.3 to 5.2V
VS=3.2 to 4.2V
VS=4.3 to 5.2V
VS=5.3 to 6.0V
>
-
VS=2.3 to 4.2V
ReferenceTap.Parameter
Fig.12,13
15,17
Fig.33
Fig.31
Fig.28
Fig.31
Fig.29
Fig.30
Fig.32
Term explanation
• Detection voltage (VS) : VDD voltage when the output (Vout) goes from "H" to "L".
• Release voltage (VS+ VS) : VDD voltage when output (Vout) goes from "L" to "H".
• Hysteresis voltage : The difference between detection voltage and release voltage. Malfunction due to noise in VDD
(within hysteresis voltage) could be avoided by hysteresis voltage.
Rev.A
4/15
BD48XXG/FVE
Voltage detectors
Operating explanation
Ex.) For both open drain type (Fig.7) and CMOS output type (Fig.8), detection voltage and release voltage are
threshold voltage. When voltage applied to VDD pin reaches each threshold voltage, VOUT pin voltage goes
"H" "L" or "L" "H". BD48XXG/FVE series are open drain types and pull-up resistor must be connected
to VDD, or other power supply. (In this case, output (VOUT) H voltage is VDD, or other power supply voltage.)
BD49XXG/FVE
VDD
Vref
R1
R2
R3Q1
GND
Fig.7 (BD48XX type Internal block diagram)Fig.8 (BD49XX Internal block diagram)
RL
Vref
VOUT
R1
R2
R3Q1
VDD
Q2
VOUT
GND
• SWEEP DOWN for VDD
When VDD is equal to or more than the release voltage (Vs+ Vs), output VOUT is in "H" mode. (Nch output
transistor Q1 is OFF, Pch output transistor Q2 is ON.) When VDD is gradually decreased, output (VOUT)
turns "L" in the detection voltage (Vs). (Nch output transistor Q1 is ON, Pch output transistor Q2 is OFF.)
• SWEEP UP for VDD
When VDD is equal to or lower than the detection voltage (Vs+ Vs), output VOUT is in "L" mode. (Nch output
transistor Q1 is ON, Pch output transistor Q2 is OFF.) When VDD is gradually increased, output (VOUT) turns
"H" in the release voltage (Vs). (Nch output transistor Q1 is OFF, Pch output transistor Q2 is ON.)
• Some hysteresis is given such a way that the release voltage is the detection voltage X (1.05 Typ.).
• The output becomes inconsistent if the VDD is equal to or lower than the operating limit voltage.
Timing waveform
Ex.) The relation between input voltage VDD and output voltage VOUT when VDD is increased and decreased
is shown below. (Circuit is shown above. Fig7, 8)
1
VDD
VOUT
VDD
VS+ VS
D
VS
VOPL
0V
VOH
If the VDD is equal to or lower than the operating limit
voltage (VOPL) at power-up, the output is inconsistent.
2
When the VDD is equal to or lower than the reset release
voltage (Vs+ Vs), VOUT=L.
3
When VDD exceeds the Reset Release Voltage, VOUT
turns H with a delay of TPLH. See Fig. 15 and 17 for the
reference waveform.
TPLH
VOL
TPHL
TPLH
4
If the VDD goes below the detection (Vs) at power-down
or instantaneous power failure, VOUT turns L with a delay
of TPHL.
See Fig.16 and 18 for the reference waveform.
234111
Fig.9
The potential difference between the detection voltage
and the release voltage is called hysteresis ( Vs).
The products are designed so as to prevent power supply
fluctuation within this hysteresis from causing fluctuation
in output in order to avoid malfunction due to noise.
Rev.A
5/15
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