Rohm's BD48XXG/FVE and BD49XXG/FVE are series of high-accuracy, low-power VOLTAGE DETECTOR ICs
with a CMOS process. For flexible choice according to the application, BD48XXG/FVE series with N channel
open drain output and BD49XXG/FVE series with CMOS output are available in 38 voltage types from 2.3 V to
6.0 V in steps of 0.1 V in different packages, totaling 152 models.
Applications
Every kind of appliances with microcontroller and logic circuit
Features
1) Detection voltage: 0.1V step line-up 2.3 to 6.0V (Typ.)
Pin layout of VSOF5(EMP5) and SSOP5(SMP5C2) is different as shown below. (Fig.1, Fig.2)
When used as replacement, please consider the difference. (The detail of packages is shown at P14.)
BD48XXG/BD49XXG
BD48XXFVE/BD49XXFVE
1VOUTVDD
2SUB
3N.C.GND
VSOF5
(EMP5)
Package
1.2mm
5
1.6mm
4
VDD
GND
1VOUTN.C.
SSOP5
(SMP5C2)
2
Package
3
1.6mm
5
2.9mm
4 N.C.
Fig.1Fig.2
(Note) Connect SUB pin with GND pin.
Rev.A
2/15
BD48XXG/FVE
Voltage detectors
Block diagram
Two output types can be used. One is BD48XXG/FVE (Fig.3) of open drain output type, and the other is
BD49XXG/FVE (Fig.4) of CMOS output type.
BD48XXG/FVE : Open drain outputBD49XXG/FVE : CMOS output
VDD
VDD
BD49XXG/FVE
Vref
GND
VOUT
Vref
GND
Fig.4Fig.3
VOUT
Absolute maximum rating (Ta=25°C)
To prevent the functional deterioration or thermal damage of semiconductor devices and ensure their service
life and reliability, they must be designed and reviewed in such a way that the absolute maximum rating can
not be exceeded in any cases or even at any moment.
ParameterSymbolUnit
Power supply voltage
Output
voltage
Power dissipation SSOP5 (SMP5C2)
Power dissipationVSOF5 (EMP5)
Nch Open drain output
CMOS output
*
*
*
*
Operating temperature
Storage temperature
*1 Derating : 1.5mW/°C for operation above Ta=25°C
*2 Derating : 1.0mW/°C for operation above Ta=25°C
*3 When only IC is used.
VDD – GND
VOUT
1
3
2
3
GND – 0.3 to VDD + 0.3
Pd
Pd
Topr
Tstg
Limits
– 0.3 to + 10
GND – 0.3 to + 10
150
100
– 40 to + 85
– 55 to + 125
V
V
mW
mW
°C
°C
• Power supply voltage
This voltage is the applied voltage between VDD and GND. The applied voltage should not exceed the
indicated value.
• Output voltage
VOUT pin voltage should not exceed the indicated value. For Nch open drain output type, VDD applied
voltage and VOUT pin H output voltage can be used independently. Both of them should not exceed the
each indicated value.
• Operating temperature range
The circuit function is guaranteed within the temperature range. However, the operating characteristics
are different from that of Ta=25°C. If they are any questions about the extent of guarantee of circuit
functions in this operating temperature range, please ask for more technical information.
• Storage temperature range
This IC can be stored up to this temperature range without deterioration of characteristics. However,
an abrupt thermal shock of extreme temperature fluctuations may cause the deterioration of characteristics.
Rev.A
3/15
BD48XXG/FVE
Voltage detectors
Power dissipation
Power consumption of the IC
Circuit current at ON/OFF is very small. Power consumption in output depends on each load connected with
VOUT pin. Please note that total power consumption must be within a power dissipation range in the secure
area of the entire operating temperature. Power dissipation of these packages; SSOP5 (SMP5C2) package
(BD48XXG/BD49XXG) Fig.5, and VSOF5 (EMP5) package (BD48XXFVE/BD49XXFVE) Fig.6 is shown below.
When it is used in the ambient temperature of (Ta)=25°C and more, make reference to each thermal derating
characteristics of used package. Both Fig.5 and Fig.6 show these characteristic when only IC is used.
Electrical characteristics (Unless otherwise noted; Ta=-25°C to 85°C)
*1 Operation is guaranteed forTa=25°C.
*2 TPLH : VDD=(VS typ.–0.5V) (VS typ.+0.5V).
Note) RL is not necessary for CMOS output type.
Note) Minimum operating voltage
VOUT output becomes inconsistent if the VDD is equal to or lower than the operating limit voltage. It goes open, H, or L.
Note) Hysteresis voltage=(Reset release voltage)-(Reset detection voltage) [V]
Ileak
—
0.80
0.85
0.90
—
2.40
2.55
2.70
—
0.1
VDD=Vs+2V
A
*1
>
-
mAIOL"L" output current
VDS=0.5V, VDD=2.4V (VS 2.7V)
VDS=0.5V, VDD=4.8V
mAIOH"H" output current
VDS=0.5V, VDD=6.0V VS=4.3 to 5.2V
VDS=0.5V, VDD=8.0V VS=5.3 to 6.0V
VDD=VDS=10V *1
A
*2
VS=3.2 to 4.2V
VS=4.3 to 5.2V
VS=3.2 to 4.2V
VS=4.3 to 5.2V
VS=5.3 to 6.0V
>
-
VS=2.3 to 4.2V
ReferenceTap.Parameter
Fig.12,13
15,17
Fig.33
Fig.31
Fig.28
Fig.31
Fig.29
Fig.30
Fig.32
Term explanation
• Detection voltage (VS) : VDD voltage when the output (Vout) goes from "H" to "L".
• Release voltage (VS+ VS) : VDD voltage when output (Vout) goes from "L" to "H".
• Hysteresis voltage : The difference between detection voltage and release voltage. Malfunction due to noise in VDD
(within hysteresis voltage) could be avoided by hysteresis voltage.
Rev.A
4/15
BD48XXG/FVE
Voltage detectors
Operating explanation
Ex.) For both open drain type (Fig.7) and CMOS output type (Fig.8), detection voltage and release voltage are
threshold voltage. When voltage applied to VDD pin reaches each threshold voltage, VOUT pin voltage goes
"H" "L" or "L" "H". BD48XXG/FVE series are open drain types and pull-up resistor must be connected
to VDD, or other power supply. (In this case, output (VOUT) H voltage is VDD, or other power supply voltage.)
BD49XXG/FVE
VDD
Vref
R1
R2
R3Q1
GND
Fig.7 (BD48XX type Internal block diagram)Fig.8 (BD49XX Internal block diagram)
RL
Vref
VOUT
R1
R2
R3Q1
VDD
Q2
VOUT
GND
• SWEEP DOWN for VDD
When VDD is equal to or more than the release voltage (Vs+ Vs), output VOUT is in "H" mode. (Nch output
transistor Q1 is OFF, Pch output transistor Q2 is ON.) When VDD is gradually decreased, output (VOUT)
turns "L" in the detection voltage (Vs). (Nch output transistor Q1 is ON, Pch output transistor Q2 is OFF.)
• SWEEP UP for VDD
When VDD is equal to or lower than the detection voltage (Vs+ Vs), output VOUT is in "L" mode. (Nch output
transistor Q1 is ON, Pch output transistor Q2 is OFF.) When VDD is gradually increased, output (VOUT) turns
"H" in the release voltage (Vs). (Nch output transistor Q1 is OFF, Pch output transistor Q2 is ON.)
• Some hysteresis is given such a way that the release voltage is the detection voltage X (1.05 Typ.).
• The output becomes inconsistent if the VDD is equal to or lower than the operating limit voltage.
Timing waveform
Ex.) The relation between input voltage VDD and output voltage VOUT when VDD is increased and decreased
is shown below. (Circuit is shown above. Fig7, 8)
1
VDD
VOUT
VDD
VS+ VS
D
VS
VOPL
0V
VOH
If the VDD is equal to or lower than the operating limit
voltage (VOPL) at power-up, the output is inconsistent.
2
When the VDD is equal to or lower than the reset release
voltage (Vs+ Vs), VOUT=L.
3
When VDD exceeds the Reset Release Voltage, VOUT
turns H with a delay of TPLH. See Fig. 15 and 17 for the
reference waveform.
TPLH
VOL
TPHL
TPLH
4
If the VDD goes below the detection (Vs) at power-down
or instantaneous power failure, VOUT turns L with a delay
of TPHL.
See Fig.16 and 18 for the reference waveform.
234111
Fig.9
The potential difference between the detection voltage
and the release voltage is called hysteresis ( Vs).
The products are designed so as to prevent power supply
fluctuation within this hysteresis from causing fluctuation
in output in order to avoid malfunction due to noise.
Rev.A
5/15
Voltage detectors
Application circuit
1)Application circuit as ordinal supply detection reset is shown below.
BD48XXG/FVE
BD49XXG/FVE
VDD1
BD48XXX
RL
()
CL
(Noise filtering
capacitor)
RST
Micro
controller
VDD2
GND
VDD1
GND
BD49XXX
()
CL
RST
(Noise filtering
capacitor)
Micro
controller
Fig.10 Open collector output typeFig.11 CMOS output type
Output type of BD48XXG/FVE series (Open drain type) and BD49XXG/FVE series (CMOS type) is different.
An example of usage is shown below.
• When the power supply of microcontroller (VDD2) and power supply for the reset detection (VDD1) is different.
Provide RL for the output of a product with open drain output (BD48XXG/FVE series) on the VDD2 side,
as shown in Fig.10.
• When the power supply of microcontroller and that of reset is same (VDD1).
A product with CMOS output (BD49XXG/FVE series) can be used as shown in Fig.11. Or if RL is provided
with open drain output (BD48XXG/FVE series) on the VDD1 side, it can be used.
When the capacitor CL for noise filtering and for delay time setting is connected to VOUT pin (reset signal input
pin of microcontroller), make a setting in consideration of the wave rounding of the rise and fall of VOUT.
(See the delay shown in Fig.14 as the reference.)
10000
1000
( s)
100
delay time
10
Output delay time "L H"
[BD4842G/FVE]
1000100
CL Capacitance
(pF)
80
79
78
77
76
( s)
75
74
73
delay time
72
71
70
10000
5V
Output delay time "H L"
[BD4842G/FVE]
1000100
CL Capacitance
(pF)
10000
5V
Release voltage
(VS+ VS)
VDD
VOUT
VDD
VOUT
VS±0.5V
GND
Fig.12
TPLH
Fig.14 Delay time I/O condition
RL=100K
CL
0.5V
0.5V
TPHL
RL=100K
CL
VS±0.5V
VDD
VOUT
GND
Fig.13
Detection voltage VS [V]
5V
VOUT=5V X 0.5 [V]
Rev.A
6/15
Voltage detectors
• Test data
BD48XXG/FVE
BD49XXG/FVE
VDD
VOUT
VDD
TPLH
TPLH
Fig.15
BD4845G TPLH output waveform
VDD
VOUT
TPHL
Fig.16
BD4845G TPHL output waveform
VDD
VOUT
VOUT
T
PLH
Fig.17
BD4945G TPLH output waveform
Reference data : BD4845G test data
RL=100k
CL=100pF
Reference data : BD4945G test data
CL=100pF
TPHL
Fig.18
BD4945G TPHL output waveform
100k
VDD
BD4845G
VDDVOUT
BD4945G
VOUT
100pF
GND
100pF
GND
Rev.A
7/15
BD48XXG/FVE
Voltage detectors
2)Application circuit when microcontroller is reset with OR connection of the two types of the detection voltage
is shown below.
BD49XXG/FVE
VDD1
BD48XXX
VDD2
BD48XXX
Fig.19
RL
RST
Micro
controller
VDD3
GND
When there is more than one system power supply and it is necessary to individually monitor the power supply
(VDD1, VDD2) to reset the microcontroller, open drain output type BD48XXG/FVE series can be connected to
form an OR circuit as shown in Fig.19 for pulling up to an arbitrary voltage (VDD3) to adjust the H voltage of the
output to the microcontroller power supply (VDD3).
3)Application circuit when it is used as Power-on reset is shown below.
(However, it can be used for only BD48XXG/FVE series.)
VDD
Di
R
BD48XXX
C
Fig.20
RL
Micro
controller
GND
If the power supply voltage is lower than the guaranteed range, power-on reset of the microcontroller is necessary
to prevent program runaways and unwanted memory register updates. A power-on reset circuit used with
BD48XXG/FVE series (Nch open drain) is shown in Fig.20. C and R conneceted to VDD pin of RESET IC make
the wave rounding of the VDD pin and generate input signal with time constant. When the input power supply is
fallen, the electric charge of the capacitor is discharged through Di connected between VDD pin and VDD.
The value of the resister R should be enough to prevent malfunction caused by circuit current through
BD48XXG/FVE series. Set in such a way that the following expression stands:
Hysteresis > R X { (Circuit current at ON) - (Circuit current at OFF) }
Do not use BD49XXG/FVE series (CMOS output) for the power-on reset because malfunction may occur.
(Oscillation at output etc.) The feed through current (CMOS output) at detection may cause malfunction
mentioned above. (Feed through current is the current flowed from VDD into GND instantly when output
goes "H" "L". )
VDD
Feed through current
VOUT
GND
Fig.21
CMOS output circuit
ICC
Feed through current
0VDD
VS
Fig.22
Current consumption Vs. power supply voltage
Rev.A
8/15
BD48XXG/FVE
Voltage detectors
Establishment of RESET transfer delay time
Delay time at the rise and fall of VDD can be established by RL, CL connected to VOUT pin.
• Delay time at the rise of VDD TPLH : Time until when VOUT is 1/2 of VDD after the rise of VDD, and beyond
the release voltage (Vs+ Vs).(See P7). It is the total time established
by IC internal transfer delay time TD and external RL, and CL.
RESET pin voltage
VDD
VDD
BD49XXG/FVE
OUT
RL
RESET
63%
50%
=CL X RL
Output Tr
OFF
CL
VOUT voltage [V]
0t
0.69 X
Fig.24 RESET pin voltageFig.23
Time
If the threshold voltage of the RESET terminals is 1/2 of VCC, delay time TPLH at the rise of VDD is shown
in the expression below.
TPLH=0.69 X CL X RL+TD
TD=Internal circuit delay of BD48XX : About 35 s (typ.) VDD=(Vs–0.5V) (Vs+0.5V)
CL : Capacity of external capacitor beween VOUT pin and GND
RL : External resistance between VOUT pin and power supply
• Delay time at the fall of VDD TPHL : Time until when VOUT is 1/2 of VDD after across the detection
voltage (Vs).(See P7). It is the total time established by IC internal
transfer delay time TD and external RL, and CL.
VDD
Vs
Vout voltage[V]
0t
Fig.26 RESET pin voltage
B
A
Time
Output Tr
ON
VOUT
IOL
VDD
RL
RESET
CL
Fig.25
=A+B
PHL
T
A = About 70 s(Typ.) :
B =
IOL
C
CL X Vs
Capacity of external capacitor beween
L :
:
Delay time by external C
Internal IC transfer delay time of
VOUT pin and GND
Vs : Detection voltage
: "L" output current of BD48XX
OL
I
Make sure to test in actual because it depends
on detection voltage.
Reference:V
=2.4V, VDD
S
L
, R
L
=About 8mA at A:typ.
VDD
VOUT
BD4842
Release voltage
(VS+ VS)
0.5V
0.5V
TPLH
Fig.27 Delay time I/O condition
TPHL
Rev.A
Detection voltage VS [V]
5V
VOUT=5V X 0.5 [V]
9/15
Voltage detectors
Characteristic data (Reference data)
BD48XXG/FVE
BD49XXG/FVE
1.5
1.0
[ A]
DD
I
0.5
[V]
VOUT
[BD4842G/FVE]
0
A
VDD
52143107698
[V]
VDD
VDD
GND
VOUT
Fig.28
Circuit current
9
8
7
6
5
4
3
2
1
Ta=25°C
0
VDD
[V]
[BD4842G/FVE]
Ta=25°C
3.50.51.52.5 34.545.5521
18
15
10
mA]
[
IOL
5
0.51
0
VDD
Fig.29
"L" output current
4
3
2
1
0
-1
Ileak [ A]
-2
-3
-4
24
0
[BD4842G/FVE]
VDD=2.4V
VDD=1.2V
1.522.5
[V]
VDS
VDD
VOUT
GND
[BD4842G/FVE]
681012
[V]
VDS
A
VDS
45
40
35
30
25
[mA]
20
IDS
15
10
5
12
0
VDD
Fig.30
"H" output current
[BD4942G/FVE]
=8.0V
DD
V
=6.0V
DD
V
VDD=4.8V
3456
[V]
VDS
VDD
GND
A
VOUT
VDS
VDD
VDD
VOUT
GND
Fig.31
I/O characteristic
RL=470K
V
VDD
VDD
GND
Fig.32
Output leak current
VOUT
A
VDS
Rev.A
10/15
Voltage detectors
BD48XXG/FVE
BD49XXG/FVE
low to high(VS+ VS)
[°C]
Ta
VDD
VOUT
GND
[BD4842G/FVE]
high to low(VS)
VDD
[V]
VS
5.4
5.0
4.6
4.2
3.8
3.4
050–40
Fig.33
Detection voltage (VS)
Release voltage (VS+ VS)
RL=470K
V
[BD4842G/FVE]
1.0
[ A]
DD
I
0.5
90
-40
A
VDD
20-200100408060
[°C]
Ta
VDD
GND
Fig.34
Circuit current on ON (VS-0.2V)
VOUT
[BD4842G/FVE]
1.0
[ A]
DD
I
0.5
-40
A
VDD
20-200100408060
[°C]
Ta
VDD
VOUT
GND
Fig.35
Circuit current on OFF (VS+0.2V)
[BD4842G/FVE]
2
1
[ A]
0
leak
I
-1
-2
-20100
-40
VDD
200408060
[°C]
Ta
VDD
VOUT
GND
Fig.36
Output leak current
[BD4842G/FVE]
1.0
[V]
OPL
0.5
V
-40
VDD
A
VDS
20-200408060
[°C]
Ta
VDD
VOUT
GND
100
RL=470K
V
Fig.37
Operating limit voltage
Rev.A
11/15
Voltage detectors
Taping specification
1)Dimension of tape
BD48XXG/FVE
BD49XXG/FVE
Rectangular recess to hold a component
B
t
K
Package SSOP5 (SMP5C2)
Circular feed hole
D1
A
Fig.38
P2
P0
P1
D0
E
F
W
(mm)
Symbol
Dimension
Symbol
Dimension
Package VSOF5 (EMP5)
Symbol
Dimension
Symbol
Dimension
A
3.2±0.1
P2
2.0±0.05t0.3±0.05K1.3±0.1W8.0±0.2
A
1.83±0.1B1.83±0.1
P2
2.0±0.05t0.25±0.05K0.75±0.1
B
3.1±0.1
1.5
1.5
D0
+0.1
–0
D0
+0.1
–0
D1
1.1±0.1
D1
0.5±0.1
W
8.0±0.2
E
1.75±0.1
E
1.75±0.1
F
3.5±0.05P04.0±0.1
F
3.5±0.05P04.0±0.1
P1
4.0±0.1
(mm)
P1
4.0±0.1
Rev.A
12/15
Voltage detectors
BD48XXG/FVE
BD49XXG/FVE
2)Dimension of reel
TMAX
E
D
C
B
Symbol
DimensionA180 Max.B60±2.0
A
C
13.0±0.5
Fig.39
D
20.2 Min.
E
1.5 Min.
W
9.0±0.3
t
W
Label side(1.0)
Back side(1.2)
t
TMax.
17.4
3)Standard packaged quantity and IC direction
The standard packaged quantity is 3,000 pcs/reel. Orders should be in multiples of the standard packaged
quantity. The ICs are TR oriented (as shown below).
First pin
(mm)
Fig.40
(Leader side)
Rev.A
13/15
Voltage detectors
Recommended mounting conditions
• SSOP5 (SMP5C2) allows either reflow or flow soldering mounting.
• VSOF5 (EMP5) allows reflow mounting.
The mounting conditions are shown below.
BD48XXG/FVE
BD49XXG/FVE
1)Reflow
Up to two reflows are allowed.
2)Flow soldering
Treatment
140°C
process
Preheating
section
Solder bath
90±30s
Condition
Temperature
150±10°C
Max. 260°C
Max. 10s
Max.240°C
235°C
160°C
Fig.41
Time
60 to 120s
Max. 10s
3)Product storage conditions
Store the products in an environment of 5 to 30°C in temperature and 70% RH or lower in humidity.
Dimension
0.42
0.1
(UNIT:mm)
4° + 6°
-4°
0.2MIN
+0.05
0.13
–0.03
+0.05
-0.04
1.6±0.05
0.6MAX
1.2±0.05
1.6±0.05
1.0±0.05
4
5
3
1
2
Lot No.
0.22±0.05
0.5
VSOF5
(EMP5)
(UNIT:mm)
0.13±0.05
0.08
M
0.2MAX
0.2
±
2.8
0.2
+
0.1
-
1.6
2.9±0.2
(5)
(4)
(2)(1)
(3)
0.05
1.1±
1.25MAX
0.95
0.05
±
0.05
(SMP5C2)
SSOP5
Rev.A
14/15
Voltage detectors
Reference land pattern
BD48XXG/FVE
BD49XXG/FVE
VSOF5
(EMP5)
SSOP5
(SMP5C2)
ee
e1
2
b2
2
ee
e1
b2
Fig.42Fig.43
Lead pitcheLead pitch
e1
Land length
2
0.501.350.350.25
Unit:mm
Land width
b2
Lead pitcheLead pitch
e1
Land length
2
0.952.401.000.60
Unit:mm
Land width
b2
For actual designing, take the board density, mountability, dimension tolerance, etc. for optimization.
Part number and marking of samples
The BD48XX and BD49XX series products allow optimum selection of detection voltage, output circuit type
and package according to the application.
Part No.SpecificationContents
Part No.
B D 4 X X X X
123
Marking Voltage Part No. Marking Voltage Part No. Marking Voltage Part No. Marking Voltage Part No.
No technical content pages of this document may be reproduced in any form or transmitted by any
means without prior permission of ROHM CO.,LTD.
The contents described herein are subject to change without notice. The specifications for the
product described in this document are for reference only. Upon actual use, therefore, please request
that specifications to be separately delivered.
Application circuit diagrams and circuit constants contained herein are shown as examples of standard
use and operation. Please pay careful attention to the peripheral conditions when designing circuits
and deciding upon circuit constants in the set.
Any data, including, but not limited to application circuit diagrams information, described herein
are intended only as illustrations of such devices and not as the specifications for such devices. ROHM
CO.,LTD. disclaims any warranty that any use of such devices shall be free from infringement of any
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whatsoever nature in the event of any such infringement, or arising from or connected with or related
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Upon the sale of any such devices, other than for buyer's right to use such devices itself, resell or
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ROHM CO., LTD. is granted to any such buyer.
Products listed in this document are no antiradiation design.
Notes
The products listed in this document are designed to be used with ordinary electronic equipment or devices
(such as audio visual equipment, office-automation equipment, communications devices, electrical
appliances and electronic toys).
Should you intend to use these products with equipment or devices which require an extremely high level of
reliability and the malfunction of with would directly endanger human life (such as medical instruments,
transportation equipment, aerospace machinery, nuclear-reactor controllers, fuel controllers and other
safety devices), please be sure to consult with our sales representative in advance.
About Export Control Order in Japan
Products described herein are the objects of controlled goods in Annex 1 (Item 16) of Export Trade Control
Order in Japan.
In case of export from Japan, please confirm if it applies to "objective" criteria or an "informed" (by MITI clause)
on the basis of "catch all controls for Non-Proliferation of Weapons of Mass Destruction.
Appendix1-Rev1.1
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