• Advanced, High-speed Programmable Logic Device – Superset of 22V10
– Improved Performance - 7.5 ns t
– Enhanced Logic Flexibility
– Backward Compatible with ATV750(L) Software and Hardware
• New Flip-flop Features
– D- or T-type
– Product Term or Direct Input Pin Clocking
• High-speed Erasable Programmable Logic Devices
– 7.5 ns Maximum Pin-to-pin Delay
DeviceICC, Standby
ATV750B125 mA
ATV750BL15 mA
, 95 MHz External Operation
PD
High-speed UV
Erasable
Programmable
• Highest Density Programmable Logic Available in a 24-pin Package
• Increased Logic Flexibility
– 42 Array Inputs, 20 Sum Terms and 20 Flip-flops
• Enhanced Output Logic Flexibility
– All 20 Flip-flops Feed Back Internally
– 10 Flip-flops are Also Available as Outputs
• Full Military, Commercial and Industrial Temperature Ranges
Logic Diagram
Description
The ATV750B(L) is twice as powerful as most other 24-pin programmable logic
devices. Increased product terms, sum terms, flip-flops and output logic configurations
translate into more usable gates. High-speed logic and uniform, predictable delays
guarantee fast in-system performance.
Logic Device
ATV750B
ATV750BL
Commercial and
industrial versions
are obsolete. Please
use ATF750C.
Military versions
continue to be available,
but please do not
use for new designs.
For new military
applications, recommend
multiple ATF22V10s.
Pin Configurations
Pin NameFunction
CLKClock
INLogic Inputs
I/OBi-directional Buffers
*No Internal Connection
V
CC
+5V Supply
CLK/IN
GND
DIP/SOIC
1
2
IN
3
IN
4
IN
5
IN
6
IN
7
IN
8
IN
9
IN
10
IN
11
IN
12
PLCC/LCC
24
VCC
23
I/O
22
I/O
21
I/O
20
I/O
19
I/O
18
I/O
17
I/O
16
I/O
15
I/O
14
I/O
13
IN
5
IN
6
IN
7
IN
8
*
9
IN
10
IN
11
IN
ININCLK/IN*VCC
432
12131415161718
IN
IN
GND
1
*
I/O
282726
IN
I/O
I/O
25
24
23
22
21
20
19
I/O
I/O
I/O
I/O
*
I/O
I/O
I/O
Rev. 0301I–08/01
1
Each of the ATV750B(L) 22 logic pins can be used as an input. Ten of these can be used as
Combined TermsSeparate Terms
inputs, outputs or bi-directional I/O pins. Each flip-flop is individually configurable as either Dor T-type. Each flip-flop output is fed back into the array independently. This allows burying of
all the sum terms and flip-flops.
There are 171 total product terms available. A variable format is used to assign between four
to eight product terms per sum term. There are two sum terms per output, providing added
flexibility. Much more logic can be replaced by this device than by any other 24-pin PLD. With
20 sum terms and flip-flops, complex state machines are easily implemented with logic to
spare.
Product terms provide individual clocks and asynchronous resets for each flip-flop. Each flipflop may also be individually configured to have direct input pin controlled clocking. Each output has its own enable product term. One product term provides a common synchronous
preset for all flip-flops. Register preload functions are provided to simplify testing. All registers
automatically reset upon power-up.
The ATV750BL is a low-power device with speeds as fast as 15 ns. The ATV750BL provides
the optimum low-power PLD solution, with full CMOS output levels. This device
significantly reduces total system power, thereby allowing battery-powered operation.
Absolute Maximum Ratings*
Temperature Under Bias................................ -55°C to +125°C
Storage Temperature..................................... -65°C to +150°C
Voltage on Any Pin with
Respect to Ground .........................................-2.0V to +7.0V
Voltage on Input Pins
with Respect to Ground
During Programming.....................................-2.0V to +14.0V
Programming Voltage with
Respect to Ground .......................................-2.0V to +14.0V
*NOTICE:Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any
(1)
(1)
(1)
2
Note:1. Minimum voltage is -0.6V DC which may under-
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect
device reliability.
shoot to -2.0V for pulses of less than
20 ns.Maximum output pin voltage is V
DC which may overshoot to +7.0V for pulses of
less than 20 ns.
+ 0.75V
CC
Logic Options
Combinatorial Output
2
ATV750B(L)
Registered Output
Combined TermsSeparate Terms
0301I–08/01
Clock Mux
C
Output Options
CLOCK
PRODUCT
TERM
CKi
CLK
PIN
ATV750B(L)
CK MUX
TO
LOGI
CELL
SELECT
DC and AC Operating Conditions
Operating Temperature 0°C - 70°C
V
Power Supply5V ± 5%5V ± 10%5V ± 10%5V ± 10%
CC
Note:1. See ordering information for valid speed and temperature combination.
(1)
Commercial
-7, -10, -15
(Ambient)
Commercial
-25IndustrialMilitary
0°C - 70°C
(Ambient)
-40°C - 85°C
(Ambient)
-55°C - 125°C
(Case)
0301I–08/01
3
DC Characteristics
SymbolParameterConditionMinTypMaxUnits
I
LI
I
LO
Input Load CurrentVIN = -0.1V to VCC + 1V10µA
Output Leakage
CurrentV
= -0.1V to VCC + 0.1V
OUT
10µA
Com.125180mA
B-7, -10
Ind., Mil.125190mA
Com.125180mA
B-15, -25
= MAX,
V
Power Supply
I
CC
(1)
I
OS
V
IL
V
IH
Current, Standby
Output Short
Circuit CurrentV
Input Low Voltage4.5 ≤ VCC ≤ 5.5V-0.60.8V
Input High Voltage2.0V
Output Low
V
OL
Voltage
Output High
V
OH
Voltage
CC
= MAX,
V
IN
Outputs Open
= 0.5V
OUT
VIN = VIH or VIL,
V
= MIN
CC
VIN = VIH or VIL,
= MIN
V
CC
BL-15
= 16 mA Com., Ind.0.5V
I
OL
I
= 12 mA Mil.0.5V
OL
I
= 24 mA Com.0.8V
OL
= -100 µAVCC - 0.3V
I
OH
I
= -4.0 mA2.4V
OH
Ind., Mil.125190mA
Com.1530mA
Ind., Mil.1530mA
-120mA
+ 0.75V
CC
Note:1. Not more than one output at a time should be shorted. Duration of short circuit test should not exceed 30 sec.
Input Test Waveforms and Measurement Levels
Output Test Load
4
ATV750B(L)
tR, tF < 3 ns (10% to 90%)
0301I–08/01
ATV750B(L)
AC Waveforms, Product Term Clock
(1)
Note:1. Timing measurement reference is 1.5V. Input AC driving levels are 0.0V and 3.0V, unless otherwise specified.
AC Characteristics, Product Term Clock
(1)
-7-10B/BL-15B/BL-25
SymbolParameter
UnitsMinMaxMinMaxMinMaxMinMax
t
PD
t
EA
t
ER
t
CO
t
CF
t
S
t
SF
t
H
t
P
t
W
f
MAX
t
AW
t
AR
t
AP
Input or Feedback to
7.5101525ns
Non-Registered Output
Input to Output Enable7.5101525ns
Input to Output Disable7.5101525ns
Clock to Output37.5410512620ns
Clock to Feedback1547.559510ns
Input Setup Time348/1214ns
Feedback Setup Time3477ns
Hold Time125/75/7ns
Clock Period7111417ns
Clock Width3.55.578.5ns
External Feedback 1/(tS+tCO)957150/4129MHz
Internal Feedback 1/(t
No Feedback 1/(t
)142907158MHz
P
)125866258MHz
SF+tCF
Asynchronous Reset Width5101520ns
Asynchronous Reset
31015 20 ns
Recovery Time
Asynchronous Reset to
812 1525ns
Registered Output Reset
t
SP
Setup Time, Synchronous Preset47815ns
Note:1. See ordering information for valid part numbers.
0301I–08/01
5
AC Waveforms, Input Pin Clock
(1)
Note:1. Timing measurement reference is 1.5V. Input AC driving levels are 0.0V and 3.0V, unless otherwise specified.
AC Characteristics, Input Pin Clock
SymbolParameter
Input or Feedback to
t
PD
t
EA
t
ER
t
COS
t
CFS
t
SS
t
SFS
t
HS
t
PS
t
WS
f
MAXS
Non-Registered Output
Input to Output Enable7.5101525ns
Input to Output Disable7.5101525ns
Clock to Output06.507010012ns
Clock to Feedback03.50505.507ns
Input Setup Time46.58/12.59/15ns
Feedback Setup Time4579ns
Hold Time0000ns
Clock Period7101216ns
Clock Width3.5568ns
External Feedback 1/(tSS+t
Internal Feedback 1/(t
No Feedback 1/(tPS)1421008362MHz
t
t
AW
ARS
Asynchronous Reset Width5101520ns
Asynchronous Reset
Recovery Time
COS
SFS+tCFS
-7-10
B/BL
-15
B/BL
-25
UnitsMinMaxMinMaxMinMaxMinMax
7.5101525ns
)957455/4448/37MHz
)1331008062MHz
510 1525 ns
t
AP
Asynchronous Reset to
81015 25ns
Registered Output Reset
t
SPS
6
Setup Time, Synchronous Preset55/91115ns
ATV750B(L)
0301I–08/01
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