Rainbow Electronics ATV2500BQL User Manual
Features
• High-performance, High-density Programmable Logic Device
– Typical 7 ns Pin-to-pin Delay
– Fully Connected Logic Array with 416 Product Terms
• Flexible Output Macrocell
– 48 Flip-flops – Two per Macrocell
–72 Sum Terms
– All Flip-flops, I/O Pins Feed in Independently
– Achieves Over 80% Gate Utilization
• Enhanced Macrocell Configuration Selections
– D- or T-type Flip-flops
– Product Term or Direct Input Pin Clocking
– Registered or Combinatorial Internal Feedback
• Several Power Saving Options
Device ICC, Standby
High-speed
High-density
UV-erasable
ATV2500B 110 mA
ATV2500BQ 30 mA
ATV2500BL 2 mA
ATV2500BQL 2 mA
• Backward Compatible with ATV2500H/L Software
• Proven and Reliable High-speed UV EPROM Process
• Reprogrammable – Tested 100% for Programmability
• 40-lead Dual-in-line and 44-lead Surface Mount Packages
Block Diagram
Pin Configurations
Pin Name Function
IN Logic Inputs
CLK/IN Pin Clock and
Input
I/O Bi-directional
Buffers
I/O 0,2,4.. “Even” I/O Buffers
I/O 1,3,5.. “Odd” I/O Buffers
GND Ground
VCC +5V Supply
Note: For ATV2500BQ and
ATV2500BQL (PLCC/LCC
package only) pin 4 and
pin 26 connections are not
required.
I/O2
I/O3
I/O4
I/O5
VCC
VCC
I/O17
I/O16
I/O15
I/O14
I/O13
LCC/PLCC
I/O1
I/O0
GNDININ
65432
7
8
9
10
11
12
13
14
15
16
17
1819202122232425262728
I/O12
CLK/INININININ
1
4443424140
INININININININ
GND
I/O18
I/O06
39
38
37
36
35
34
33
32
31
30
29
I/O19
I/O7
I/O8
I/O9
I/O10
I/O11
GND
GND
I/O23
I/O22
I/O21
I/O20
CLK/IN
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
VCC
I/O17
I/O16
I/O15
I/O14
I/O13
I/O12
Programmable
Logic Device
ATV2500B
ATV2500BQ
ATV2500BQL
DIP
1
40
2
IN
3
IN
4
5
6
7
8
9
10
11
12
13
14
15
16
17
IN
18
IN
19
IN
20
IN
IN
39
IN
38
IN
37
IN
36
I/O6
35
I/O7
34
I/O8
33
I/O9
32
I/O10
31
I/O11
30
GND
29
I/O23
28
I/O22
27
I/O21
26
I/O20
25
I/O19
24
I/O18
23
IN
22
IN
21
IN
Rev. 0249J–05/00
1
Functional Logic Diagram ATV2500B
Note: 1. Not required for PLCC versions of ATV2500BQ or ATV2500BQL, making them compatible with ATV2500H and ATV2500L
pinout.
2
ATV2500B(Q)(L)
ATV2500B(Q)(L)
Description
The ATV2500Bs are the highest density PLDs available in
a 40- or 44-lead package. With their fully connected logic
array and flexible macrocell structure, high-gate utilization
is easily obtainable.
The ATV2500Bs are organized around a single universal
and-or array. All pins and feedback terms are always available to every macrocell. Each of the 38 logic pins are array
inputs, as are the outputs of each flip-flop.
In the ATV2500Bs, four product terms are input to each
sum term. Furthermore, each macrocell’s three sum terms
can be combined to provide up to 12 product terms per
sum term with no performance penalty. Each flip-flop is
individually selectable to be either D- or T-type, providing
further logic compaction. Also, 24 of the flip-flops may be
bypassed to provide internal combinatorial feedback to the
logic array.
Product terms provide individual clocks and asynchronous
resets for each flip-flop. The flip-flops may also be individually configured to have direct input pin clocking. Each
output has its own enable product term. Eight synchronous
preset product terms serve local groups of either four or
eight flip-flops. Register preload functions are provided to
simplify testing. All registers automatically reset upon
power-up.
Several low-power device options allow selection of the
optimum solution for many power-sensitive applications.
Each of the options significantly reduces total system
power and enhances system reliability.
Functional Logic Diagram Description
The ATV2500B functional logic diagram describes the
interconnections between the input, feedback pins and
logic cells. All interconnections are routed through the
single global bus.
The ATV2500Bs are straightforward and uniform PLDs.
The 24 macrocells are numbered 0 through 23. Each macrocell contains 17 AND gates. All AND gates have 172
inputs. The five lower product terms provide AR1, CK1,
CK2, AR2, and OE. These are: one asynchronous reset
and clock per flip-flop, and an output enable. The top 12
product terms are grouped into three sum terms, which are
used as shown in the macrocell diagrams.
Eight synchronous preset terms are distributed in a 2/4 pattern. The first four macrocells share Preset 0, the next two
share Preset 1, and so on, ending with the last two macrocells sharing Preset 7.
The 14 dedicated inputs and their complements use the
numbered positions in the global bus as shown. Each macrocell provides six inputs to the global bus: (left to right)
feedback F2
and the pin true and false. The positions occupied by these
signals in the global bus are the six numbers in the bus diagram next to each macrocell.
Note: 1. Either the flip-flop input (D/T2) or output (Q2) may be
(1)
true and false, flip-flop Q1 true and false,
3
Absolute Maximum Ratings*
Temperature Under Bias................................ -55°C to +125°C
Storage Temperature..................................... -65°C to +150°C
Voltage on Any Pin with
Respect to Ground .........................................-2.0V to +7.0V
Voltage on Input Pins
with Respect to Ground
During Programming.....................................-2.0V to +14.0V
Programming Voltage with
Respect to Ground .......................................-2.0V to +14.0V
Integrated UV Erase Dose..............................7258 W•sec/cm
(1)
(1)
(1)
2
*NOTICE: Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
Note: 1. Minimum voltage is -0.6V DC which may under-
shoot to -2.0V for pulses of less than 20 ns.
Maximum output pin voltage is V
CC
which may overshoot to +7.0V for pulses of less
than 20 ns.
DC and AC Operating Conditions
Commercial Industrial Military
Operating Temperature
0°C - 70°C
(Ambient)
VCC Power Supply 5V ± 5% 5V ± 10% 5V ± 10%
-40°C - 85°C
(Ambient)
-55°C - 125°C
(Case)
+ 0.75V DC
Pin Capacitance
f = 1 MHz, T = 25°C
C
IN
C
OUT
Note: 1. Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested.
(1)
Typ Max Units Conditions
46pFV
812pFV
= 0V
IN
OUT
= 0V
4
ATV2500B(Q)(L)
ATV2500B(Q)(L)
Output Logic, Registered
(1)
S2 = 0 Terms in
Output ConfigurationS1 S0 D/T1 D/T2
0084Registered (Q1); Q2 FB
(1)
10124
1184Registered (Q1); D/T2 FB
Output
S3
Configuration S6 Q1 CLOCK
0 Active Low 0 CK1
1 Active High 1 CK1 • PIN1
S4 Register 1 Type S7 Q2 CLOCK
0D 0CK2
1T 1CK2 • PIN1
S5 Register 2 Type
0D
1T
Registered (Q1); Q2 FB
Output Logic, Combinatiorial
(1)
Note: 1. These diagrams show equivalent logic functions, not
necessarily the actual circuit implementation.
S2 = 1 Terms in
Output ConfigurationS5 S1 S0 D/T1 D/T2
X004
X0144
X104
1114
01144
(1)
(1)
(1)
Combinatorial (8 Terms);
4
Q2 FB
Combinatorial (4 Terms);
Q2 FB
Combinatorial (12 Terms);
(1)
4
Q2 FB
Combinatorial (8 Terms);
4
D/T2 FB
Combinatorial (4 Terms);
D/T2 FB
Note: 1. These four terms are shared with D/T1.
Clock Option
5
DC Characteristics
Symbol Parameter Condition Min Typ Max Units
I
IL
I
LO
Input Load Current VIN = -0.1V to VCC + 1V 10 µA
Output Leakage
Current
= -0.1V to VCC + 0.1V 10 µA
V
OUT
Com. 110 190 mA
ATV2500B
Ind., Mil. 110 210 mA
= MAX,
V
Power Supply
I
CC
Current,
Standby
CC
V
= GND or
IN
f = 0 MHz,
V
CC
Outputs Open
ATV2500BQ
ATV2500BL
ATV2500BQL
I
OS
V
IL
V
IH
V
OL
V
OH
Output Short
Circuit Current
V
= 0.5V -120 mA
OUT
Input Low Voltage MIN ≤ VCC ≤ MAX -0.6 0.8 V
Input High Voltage 2.0
Output Low
Voltage
Output High
Voltage
VIN = VIH or VIL,
= 4.5V
V
CC
= MIN
V
CC
IOL = 8 mA Com., Ind. 0.5 V
I
= 6 mA Mil. 0.5 V
OL
I
= -100 µA VCC - 0.3 V
OH
I
= -4.0 mA 2.4
OH
Note: 1. See ICC versus frequency characterization curves.
Com. 30 70 mA
Ind., Mil. 30 85 mA
Com. 2 5 mA
Ind., Mil. 2 10 mA
Com. 2 4 mA
Ind., Mil. 2 5 mA
VCC +
0.75
V
6
ATV2500B(Q)(L)
ATV2500B(Q)(L)
AC Waveforms
AC Waveforms
(1)
Input Pin Clock
(1)
Product Term Clock
Note: 1. Timing measurement reference is 1.5V. Input AC driving levels are 0.0V and 3.0V, unless otherwise specified.
7
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