Rainbow Electronics ATtiny43U User Manual

Features

• High Performance, Low Power AVR

• Advanced RISC Architecture

– 120 Powe rful Instructions – Most Single Clock Cycle Execution – 32 x 8 General Purpose Working Registers – Fully Static Operation

• Non-Volatile Program and Data Memories

– 4K Bytes of In-System Programmable Program Memory Flash – 64 Bytes of In-System Programmable EEPROM – 256 Bytes of Internal SRAM – Write/Erase Cycles: 10,000 Flash/ 100,000 EEPROM – Data retention: 20 years at 85°C/ 100 years at 25°C – Programming Lock for Software Security

• Peripheral Features

– Two 8-Bit Timer/Counters with two PWM Channels, Each – Programmable Watchdog Timer with Separate On-chip Oscillator – On-Chip Analog Comparator – 10-bit ADC

4 Single-Ended Channels – Universal Serial Interface –Boost Converter

• Special Microcontroller Features

– debugWIRE On-chip Debug System – In-System Programmab le via SPI Port – External and Internal Interrupt Sources – Pin Change Interrupt on 16 Pins – Low Power Idle, ADC Noise Reduction and Power-Down Modes – Enhanced Power-On Reset Circuit – Programmable Brown-Out Detection Circuit – Internal Calibrated Oscillator – Temperature Sensor On Chip

• I/O and Pac kages

– Available in 20-Pin SOIC and 20-Pin QFN/MLF – 16 Programmable I/O Lines

• Operating Voltage:

– 0.7 – 1.8V (via On-Chip Boost Converter) – 1.8 – 5.5V (Boost Converter Bypassed)

• Speed Grade

– Using On-Chip Boost Converter

0 – 4 MHz – External Power Supply

0 – 4 MHz @ 1.8 – 5.5V

0 – 8 MHz @ 2.7 – 5.5V

• Low Power Consumption

– Active Mode, 1 MHz System Clock (Without Boost Converter)

400 µA @ 3V – Power-Down Mode (Without Boost Converter)

150 nA @ 3V

Note: 1. See “Data Retention” on page 6 for details.

8-Bit Microcontroller

(1)

8-bit

Microcontroller with 4K Bytes In-System Programmable Flash and Boost Converter

ATtiny43U

Preliminary

Rev. 8048B–AVR–03/09

ATtiny43U

1. Pin Configurations

Figure 1-1. Pinout of ATtiny43U

SOIC

(T0/PCINT8) PB0

(OC0A/PCINT9) PB1

(OC0B/PCINT10) PB2

(T1/CLKO/PCINT11) PB3

(DI/OC1A/PCINT12) PB4

(DO/OC1B/PCINT13) PB5

(USCK/SCL/PCINT14) PB6

(INT0/PCINT15) PB7

QFN/MLF Top View

(OC0B/PCINT9) PB2

(T1/CLKO/PCINT11) PB3 (DI/OC1A/PCINT12) PB4

(DO/OC1B/PCINT13) PB5

(USCK/SCL/PCINT14) PB6

VCC

GND

1 2 3 4 5 6 7 8 9 10

1 2 3 4 5

20 19 18 17 16 15 14 13 12 11

(T0/PCINT8)

PB0

PB1 (OC0A/PCINT9)

PA7 (RESET/dW/PCINT7)

PA6 (CLKI)

PA5 (AIN1/PCINT5)

2019181716

PA7 (RESET/dW/PCINT7) PA6 (CLKI/PCINT6) PA5 (AIN1/PCINT5) PA4 (AIN0/PCINT4) PA3 (ADC3/PCINT3) PA2 (ADC2/PCINT2) PA1 (ADC1/PCINT1) PA0 (ADC0/PCINT0) VBAT LSW

15 14 13 12 11

PA4 (AIN0/ PA3 (ADC3/ PA2 (ADC2/ PA1 (ADC1/ PA0 (ADC0/

PCINT4)

PCINT3) PCINT2) PCINT1) PCINT0)

1.1 Pin Descriptions

1.1.1 V

1.1.2 GND

1.1.3 Port A (PA7:PA0)

Supply voltage.

Ground.

Port A is a 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port A output buffers have symmetrical drive characteristics with both high sink and source

NOTE: Bottom pad should be Soldered to ground.

678910

VCC

LSW

GND

VBAT

(INT0/PCINT15) PB7

8048B–AVR–03/09

capability except PA7 which has the RESET capability. To use pin PA7 as an I/O pin, instead of RESET pin, program (‘0’) RSTDISBL fuse. As inputs, Port A pins that are externally pulled low will source current if the pull-up resistors are activated. The Port A pins are tri-stated when a reset condition becomes active, even if the cloc k is not ru nn in g.

Port A has an alternate functions as analog inputs for the ADC, analog comparator, timer/counter, SPI and pin change interrupt as described in “Alternate Port Functions” on page 67.

1.1.4

RESET

Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not running. The minimum pulse length is given in Table 20-4 on page

158. Shorter pulses are not guaranteed to gener at e a re se t.

1.1.5 Port B (PB7:PB0)

Port B is a 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset co ndition becomes active, even if the clock is not running.

Port B also serves the functions of various special features as listed in Section 11.3 “Alternate

Port Functions” on page 67.

1.1.6 LSW

Boost converter external inductor connection. Connect to ground when boost converter is disabled permanently.

1.1.7 V

BAT

Battery supply voltage. Connect to ground when boost converter is disabled permanently.

8048B–AVR–03/09

ATtiny43U

2. Overview

STACK

POINTER

SRAM

PROGRAM

COUNTER

BOOST

CONVERTER

PROGRAMMING

LOGIC

ISP

INTERFACE

INTERNAL

OSCILLATOR

WATCHDOG

TIMER

MCU CONTROL

MCU STATUS

TIMER/

COUNTER0

TIMER/

COUNTER1

CALIBRATED OSCILLATOR

TIMING AND

CONTROL

INTERRUPT

UNIT

EEPROM

ANALOG

COMPARATOR

ADC

POWER

SUPERVISION

POR

BOD

RESET

ON-CHIP

DEBUG

VOLTAGE

REFERENCE

GENERAL PURPOSE

REGISTERS

X Y Z

ALU

STATUS

PROGRAM

FLASH

INSTRUCTION

DECODER

CONTROL

LINES

DATA REGISTER

PORT A

DIRECTION REG.

PORT A

DRIVERS

PORT A

VBAT

LSW

RESET

DATA REGISTER

PORT B

DIRECTION REG.

PORT B

DRIVERS

PORT B

GND

USI

PA7:0 PB7:0

The ATtiny43U is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATtiny43U achieves throughputs approaching 1 MIPS pe r MHz allow ing the sy stem de signer to optimize power c onsumption versus processing speed.

Figure 2-1. Block Diagram

The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting

8048B–AVR–03/09

architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers.

The ATtiny43U provides the following features: 4K by te of In-System Programmab le Flash, 64 bytes EEPROM, 256 bytes SRAM, 16 general purpose I/O lines, 32 general purpose working registers, two 8-bit Timer/Counters with two PWM channels, Internal and External Interrupts, a 4-channel 10-bit ADC, Universal Serial Interface, a programmable Watchdog Timer with internal Oscillator, internal calibrated oscillator, and three software selectable power saving modes. The Idle mode stops the CPU while allowing the SRAM, Timer/Counter, ADC, Analog Comparator, and Interrupt system to continue functioning. The Power-down mode saves the register contents, disabling all chip functions until the next Interrupt or Hardware Reset. The ADC Noise Reduction mode stops the CPU and all I/O modules except ADC, to minimize switching noise during ADC conversions.

A special feature of ATtiny43U is the built-in boost voltage converter, which provides 3V supply voltage from an external, low voltage.

The device is manufactured using Atmel’s high density non-volatile memory technology. The On-chip ISP Flash allows the Program memory to be re-programmed In-System through an SPI serial interface, by a conventional non-volatile memory programmer or by an On-chip boot code running on the AVR core.

The ATtiny43U AVR is supported by a full suite of program and system development tools including: C Compilers, Macro Assemblers, Program Debugger/Simulators, In-Circuit Emulators, and Evaluation kits.

8048B–AVR–03/09

ATtiny43U

3. About

3.1 Resources

A comprehensive set of development tools, drivers and application notes, and datasheets are available for download on http://www.atmel.com/avr.

3.2 Code Examples

This documentation contains simple code examples t hat brief ly show h ow to us e various parts of the device. These code examples assume that the part specific header file is included b efore compilation. Be aware that not all C compiler vendors include bit definitions in the header files and interrupt handling in C is compiler dependent . Please con firm wit h the C com piler d ocume ntation for more details.

For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI” instructions must be replaced with instructions that allow access to extended I/O. Typically “LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”.

3.3 Data Retention

Reliability Qualification results show that the projected data retention failure rate is much less than 1 PPM over 20 years at 85°C or 100 years at 25°C.

3.4 Disclaimer

Typical values contained in this data sheet are based on simulations and characterization of other AVR microcontrollers manufactured on the same process technology. Min and Max values will be available after the device is characterized.

8048B–AVR–03/09

4. AVR CPU Core

Flash

Program

Memory

Instruction

Decoder

Program

Counter

Control Lines

32 x 8

General

Purpose

Registrers

ALU

Status

and Control

I/O Lines

EEPROM

Data Bus 8-bit

Data

SRAM

Direct Addressing

Indirect Addressing

Interrupt

Unit

Watchdog

Timer

Analog

Comparator

Timer/Counter 0

Timer/Counter 1

Universal

Serial Interface

4.1 Introduction

This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control peripherals, and handle interrupts.

4.2 Architectural Overview

Figure 4-1. Block Diagram of the AVR Architecture

In order to maximize performance and parallelism, the AVR uses a Harvard architecture – with separate memories and buses for program and data. Instructions in the Program memory are executed with a single level pipelining. While one instruction is being executed, the next instruction is pre-fetched from the Program memo ry. This concept enables instructions to be executed in every clock cycle. The Program memory is In-System Reprogrammable Flash memory.

8048B–AVR–03/09

ATtiny43U

The fast-access Register File contains 32 x 8-bit general purpose working registers with a single clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typical ALU operation, two operands are output from the Register File, the operation is executed, and the result is stored back in the Register File – in one clock cycle.

Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data Space addressing – enabling efficient address calculations. One of the these address pointe rs can also be used as an address pointer for look up tables in Flash Program memory. These added function registers are the 16-bit X-, Y-, and Z-register, described later in this section.

The ALU supports arithmetic and logic operations between registers or between a constant and a register. Single register operations can also be executed in the AL U. After an arith metic operation, the Status Register is updated to reflect informat ion about the result of the operation.

Program flow is provided by conditional and unconditional jump and call instructions, able to directly address the whole address space. Most AVR instructions have a single 16-bit word format. Every Program memory address contains a 16- or 32-bit instruction.

During interrupts and subroutine calls, the return address Prog ram Counter (PC) is stored on the Stack. The Stack is effectively allocated in the general data SRAM, and consequently the Stack size is only limited by the total SRAM size and the usage of the SRAM. All user programs must initialize the SP in the Reset routine (before subroutines or interrupts are executed). The Stack Pointer (SP) is read/write accessible in the I/O space. The data SRAM can easily be accessed through the five different addressing modes supported in the AVR architecture.

The memory spaces in the AVR architecture are all linear and regular memory maps. A flexible interrupt module has its control registers in the I/O space with an additional Global

Interrupt Enable bit in the Status Register. All interrupts have a separate Interrupt Vector in the Interrupt Vector table. The interrupts have priority in accordance with their Interrupt Vector position. The lower the Interrupt Vector address, the higher the priority.

The I/O memory space contains 64 addresses for CPU peripheral functions as Control Registers, SPI, and other I/O functions. The I/O memory can be acces sed directly, or as the Data Space locations following those of the Register File, 0x20 - 0x5F.

4.3 ALU – Arithmetic Logic Unit

The high-performance AVR ALU operates in direct connection with all the 32 general purpose working registers. Within a single clock cycle, arithmetic operations between general purpose registers or between a register and an immediate are execut ed . The ALU ope ra tio ns are divided into three main categories – arithmetic, logical, and bit-functions. Some implementations of the architecture also provide a powerful multiplier supporting both signed/unsigned multiplication and fractional format. See the “Instruction Set” section for a detailed description.

4.4 Status Register

The Status Register contains information abou t th e result o f th e most r ecently exe cuted arith metic instruction. This information can be used for altering program flow in order to perform conditional operations. Note that the Status Register is updated after all ALU operations, as specified in the Instruction Set Refe rence. This wil l in many cases remove the n eed for using the dedicated compare instructions, resulting in faster and more compact code.

The Status Register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt. This must be hand le d by so ftware.

8048B–AVR–03/09

4.4.1 SREG - AVR Status Register

Bit 76543210 0x3F (0x5F) I T H S V N Z C SREG Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value00000000

• Bit 7 – I: Global Interrupt Enable

The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individual interrupt enable control is then performed in separate control registers. If the Global Interrupt Enable Register is cleared, none of the interrupts are enabled independent of the individual interrupt enable settings. The I-bit is cleared by hardware after an interrupt has occurred, and is set by the RETI instruction to enable subsequent interrupts. The I-bit can also be set and cleared by the application with the SEI and CLI instructions, as described in the instruction set reference.

• Bit 6 – T: Bit Copy Storage

The Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source or destination for the operated bit. A bit from a register in the Register File can be copied into T by the BST instruction, and a bit in T can be copied into a bit in a register in the Register File by the BLD instruction.

• Bit 5 – H: Half Carry Flag

The Half Carry Flag H indicates a Half Carry in some arithmetic operations. Half Carry is useful in BCD arithmetic. See the “Instruction Set Description” for detailed information.

• Bit 4 – S: Sign Bit, S = N

⊕ V

The S-bit is always an exclusive or between the Negative Flag N and the Two’s Complement Overflow Flag V. See the “Instruction Set Description” for detailed information.

• Bit 3 – V: Two’s Complement Overflow Flag

The Two’s Complement Overflow Flag V supports two’s complement arithmetics. See the “Instruction Set Description” for detailed information.

• Bit 2 – N: Negative Flag

The Negative Flag N indicates a negative result in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information.

• Bit 1 – Z: Zero Flag

The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information.

• Bit 0 – C: Carry Flag

The Carry Flag C indicates a carry in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information.

8048B–AVR–03/09

ATtiny43U

4.5 General Purpose Register File

The Register File is optimized for the AVR Enhanced RISC instruction set. In order t o achieve the required performance and flexibility, the following input/output schemes are supported by the Register File:

• One 8-bit output operand and one 8-bit result input

• Two 8-bit output operands and one 8-bit result input

• Two 8-bit output operands and one 16-bit result input

• One 16-bit output operand and one 16-bit result input

Figure 4-2 on page 10 shows the structure of the 32 general purpose working registers in the

CPU.

Figure 4-2. AVR CPU General Purpose Working Registers

General R14 0x0E Purpose R15 0x0F Working R16 0x10

Registers R17 0x11

7 0 Addr.

R0 0x00 R1 0x01 R2 0x02

…

R13 0x0D

… R26 0x1A X-register Low Byte R27 0x1B X-register High Byte R28 0x1C Y-register Low Byte R29 0x1D Y-register High Byte R30 0x1E Z-register Low Byte R31 0x1F Z-register High Byte

4.5.1 The X-register, Y-register, and Z-register

Most of the instructions operating on the Register File have direct access to all registers, and most of them are single cycle instructions.

As shown in Figure 4-2, each register is also assigned a Data memory address, mapping them directly into the first 32 locations of the user Data Space. Although not being physically implemented as SRAM locations, this memory organization provides great flexibility in access of the registers, as the X-, Y- and Z-pointer registers can be set to index any register in the file.

The registers R26..R31 have some added functions to their general purpose usage. These registers are 16-bit address pointers for indirect addressing of the data space. The three indirect address registers X, Y, and Z are defined as described in Figure 4-3 on page 11.

8048B–AVR–03/09

4.6 Stack Pointer

Figure 4-3. The X-, Y-, and Z-registers

15 XH XL 0

X-register 707 0

R27 (0x1B) R26 (0x1A)

15 YH YL 0

Y-register 707 0

R29 (0x1D) R28 (0x1C)

15 ZH ZL 0

Z-register 7070

R31 (0x1F) R30 (0x1E)

In the different addressing modes these addr ess regist er s have fun cti ons a s fi xed d isp lacement , automatic increment, and automatic decrement (see the instruction set reference for details).

The Stack is mainly used for storing temporary data, for storing local variables and for storing return addresses after interrupts and subroutine calls. Note that the Stack is implemented as growing from higher to lower memory locations. The Stack Pointer Register always points to the top of the Stack. The Stack Pointer points to the data SRAM Stack area wh ere the Subroutine and Interrupt Stacks are located. A Stack PUSH command will decrease the Stack Pointer.

The Stack in the data SRAM must be defined by the program before any subroutine calls ar e executed or interrupts are enabled. Initial Stack Pointer value equa ls the last address of the internal SRAM and the Stack Pointer must be set to point above start of the SRAM, see Figure

5-2 on page 16.

See Table 4-1 for Stack Pointer details.

Table 4-1. Stack Pointer instructions

Instruction Stack pointer Description

PUSH Decremented by 1 Data is pushed onto the stack CALL

ICALL RCALL

POP Incremented by 1 Data is popped from the stack RET

RETI

Decremented by 2

Incremented by 2 Return address is popped from the stack with return from

Return address is pushed onto the stack with a subroutine call or interrupt

subroutine or return from interrupt

The AVR Stack Pointer is implemented as two 8-bit registers in the I/O space. The number of bits actually used is implementation dependent. Note that the data space in some implementations of the AVR architecture is so small that only SPL is needed. In this case, the SPH Register will not be present.

8048B–AVR–03/09

ATtiny43U

4.6.1 SPH and SPL — Stack Pointer Register

clk

1st Instruction Fetch

1st Instruction Execute

2nd Instruction Fetch

2nd Instruction Execute

3rd Instruction Fetch

3rd Instruction Execute

4th Instruction Fetch

T1 T2 T3 T4

CPU

Total Execution Time

ALU Operation Execute

Result Write Back

T1 T2 T3 T4

clk

CPU

Bit 151413121110 9 8 0x3E (0x5E) SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 SPH 0x3D (0x5D) SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 SPL

76543210 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value Initial Value

RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND

4.7 Instruction Execution Timing

This section describes the general access timing concepts for instruction execution. The AVR CPU is driven by the CPU clock clk chip. No internal clock division is used.

Figure 4-4 on page 12 shows the parallel instruction fetches and instruction executions enabled

by the Harvard architecture and the fast access Register File concept. This is the basic pipelining concept to obtain up to 1 MIPS per MH z with the correspo nding unique results for function s per cost, functions per clocks, and functions per power-unit.

Figure 4-4. The Parallel Instruction Fetches and Instruction Executions

, directly generated from the selected clock source for the

CPU

Figure 4-5 on page 12 shows the internal timing concept for the Register File. In a single clock

cycle an ALU operation using two register operands is executed, and the result is stored back to the destination register.

Figure 4-5. Single Cycle ALU Operation

8048B–AVR–03/09

4.8 Reset and Interrupt Handling

The AVR provides several different interrupt sources. These interrupts and the separate Reset Vector each have a separate Program Vector in the Program memory space. All interrupts are assigned individual enable bits which must be written logic one toge ther with the Glo bal Interru pt Enable bit in the Status Register in order to enable the int errupt.

The lowest addresses in the Program memory space are by default defined as the Reset and Interrupt Vectors. The complete list of vectors is shown in “Interrupts” on page 57. The list also determines the priority levels of the different interrupts. The lower the address the higher is the priority level. RESET has the highest priority, and next is INT0 – the External Interrupt Request

0. When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are dis-

abled. The user software can write logic one to the I-bit to enable nested interrupts. All enabled interrupts can then interrupt the current interrupt routine. The I-bit is automatically set when a Return from Interrupt instruction – RETI – is executed.

There are basically two types of interrupts. The first type is triggered by an event that sets the Interrupt Flag. For these interrupts, the Program Counter is vectored to the actual Interrupt Vector in order to execute the interrupt handling routine, and hardware clears the corresponding Interrupt Flag. Interrupt Flags can also be cleared by writing a logic one to the fl ag bit position(s) to be cleared. If an interrupt condition occurs while the corresponding interrupt enable bit is cleared, the Interrupt Flag will be set and remembered until the interrupt is enabled, or the flag is cleared by software. Similarly, if one or more interrupt conditions occur while the Global Interrupt Enable bit is cleared, the corresponding Interrupt Flag(s) will be set and remembered until the Global Interrupt Enable bit is set, and will then be executed by order of priority.

The second type of interrupts will trigger as long as the interrupt condition is present. These interrupts do not necessarily have Int errupt Flags. If the interrup t condition disappears before t he interrupt is enabled, the interrupt will not be triggered.

When the AVR exits from an interrupt, it will always return to the main program and execute one more instruction before any pending interrupt is served.

Note that the Status Register is not automatically stored when entering an interrupt routine, nor restored when returning from an interrupt rou tine. This must be handled by software.

When using the CLI instruction to disable interrupts, the interrupts will be immediately disabled. No interrupt will be executed after the CLI instruction, even if it occurs simultaneously with the CLI instruction. The following example shows how this can be used to avoid interrupts during the timed EEPROM write sequence.

8048B–AVR–03/09

ATtiny43U

Assembly Code Example

in r16, SREG ; store SREG value

cli ; disable interrupts during timed sequence

sbi EECR, EEMPE ; start EEPROM write

sbi EECR, EEPE

out SREG, r16 ; restore SREG value (I-bit)

C Code Example

char cSREG;

cSREG = SREG; /* store SREG value */

/* disable interrupts during timed sequence */

_CLI();

EECR |= (1<<EEMPE); /* start EEPROM write */

EECR |= (1<<EEPE);

SREG = cSREG; /* restore SREG value (I-bit) */

When using the SEI instruction to enable interrupts, the instruction following SEI will be executed before any pending interrupts, as shown in this example.

Assembly Code Example

sei ; set Global Interrupt Enable

sleep; enter sleep, waiting for interrupt

; note: will enter sleep before any pending

; interrupt(s)

C Code Example

_SEI(); /* set Global Interrupt Enable */

_SLEEP(); /* enter sleep, waiting for interrupt */

/* note: will enter sleep before any pending interrupt(s) */

4.8.1 Interrupt Response Time

The interrupt execution response for all the enabled AVR interrupts is four clock cycles minimum. After four clock cycles the Program Vector address for the a ctual interru pt handling routine is executed. During this four clock cycle period, the Program Counter is pushed onto the Stack. The vector is normally a jump to the interrupt routine, and this jump takes three clock cycles. If an interrupt occurs during execution of a multi-cycle instruction, this instruction is completed before the interrupt is served. If an interrupt occurs when the MCU is in sleep mode, the interrupt execution response time is increased by four clock cycles. This increase comes in ad dition to the start-up time from the selected sleep mode.

A return from an interrupt handling routine takes four clock cycles. During these four clock cycles, the Program Counter (two bytes) is popped back from the Stack, the Stack Pointer is incremented by two, and the I-bit in SREG is set.

8048B–AVR–03/09

5. Memories

5.1 Overview

This section describes the different memories in ATt iny43U. The AVR architect ure ha s t wo main memory spaces, the Data memory and the Program memory space. In addition, the ATtiny43U features an EEPROM Memory for data storage. All three memory spaces are linear and regular.

5.2 In-System Re-programmable Flash Program Memory

The ATtiny43U contains 4K byte On-chip In-System Reprogrammable Flash memory for program storage. Since all AVR instructions are 16 or 32 bits wide, the Flash is or ganized as 204 8 x

16. The Flash memory has an endurance of at least 10,000 write/erase cycles. The ATtiny43U Pro-

gram Counter (PC) is 11 bits wide, thus addressing the 2048 Program memory locations.

“Memory Programming” on page 139 contains a detailed description on Flash data downloading.

Constant tables can be allocated within the entire Prog ram memory address space (se e the LPM – Load Program memory instruction description).

Timing diagrams for instruction fetch and execution are presented in “Instruction Execution Tim-

ing” on page 12.

Figure 5-1. Program Memory Map

5.3 SRAM Data Memory

Figure 5-2 on page 16 shows how the ATtiny43U SRAM Memory is organized.

The low Data memory locations address both the Register File, the I/O memory and the internal data SRAM, as follows:

• The first 32 locations address the Register File

• The next 64 locations address the standard I/O memory

• The last 256 locations address the internal data SRAM

Program Memory

0x0000

0x07FF

8048B–AVR–03/09

The five different addressing modes for the Data memory cover: Dire ct, Indirect with Displacement, Indirect, Indirect with Pre-decrement, and Indirect with Post-increment. In the Register File, registers R26 to R31 feature the indirect addressing pointer registers.

ATtiny43U

The direct addressing reaches the entire data space.

clk

Data

Address

Address valid

T1 T2 T3

Compute Address

Read

Write

CPU

Memory Access Instruction

Next Instruction

The Indirect with Displacement mode reaches 63 address locations f rom the base address given by the Y- or Z-register.

When using register indirect addressing modes with automatic pre-decrement and post-increment, the address registers X, Y, and Z are decremented or incremented.

The 32 general purpose working registers, 64 I/O Registers, and the 256 bytes of internal data SRAM in ATtiny43U are all accessible through all these addressing modes. The Register File is described in “General Purpose Register File” on page 10.

Figure 5-2. Data Memory Map

Data Memory

5.3.1 Data Memory Access Times

This section describes the general access timing concepts for internal memory access. The internal data SRAM access is performed in tw o clk

16.

Figure 5-3. On-chip Data SRAM Access Cycles

32 Registers

64 I/O Registers

Internal SRAM

(256 x 8)

0x0000 - 0x001F 0x0020 - 0x005F 0x0060

0x15F

cycles as described in Figure 5-3 on page

CPU

5.4 EEPROM Data Memory

The ATtiny43U contains 64 bytes of data EEPROM memory. It is organized as a separate data space, in which single bytes can be read and written. The EEPROM has an endurance of at least 100,000 write/erase cycles. The access between the EEPROM and the CPU is described in the following, specifying the EEPROM Address Registers, the EEPROM Data Register, and

8048B–AVR–03/09

the EEPROM Control Register. For a detailed description of Serial data downloading to the EEPROM, see “Serial Programming” on page 151.

5.4.1 EEPROM Read/Write Access

The EEPROM Access Registers are accessible in the I/O space. The write access times for the EEPROM are given in Table 5-1 on page 21. A self-timing func-

tion, however, lets the user software detect when the next byte can be written. If the user code contains instructions that write the EEPROM, some precautions must be taken. In heavily filtered power supplies, V device for some period of time to run at a voltage lower than specified as minimum for the clock frequency used. See “Preventing EEPROM Corruption” on page 19 for details on how to avoid problems in these situations.

In order to prevent unintentional EEPROM writes, a specific write procedure must be followed. See “Atomic Byte Programming” on page 17 and “Split Byte Programming” on page 17 for details on this.

When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is executed. When the EEPROM is written, the CPU is halted for two clock cycles before the next instruction is executed.

5.4.2 Atomic Byte Programming

Using Atomic Byte Programming is the simplest mode. When writing a byte to the EEPROM, the user must write the address into the EEAR Register and data into EEDR Register. If the EEPMn bits are zero, writing EEPE (within four cycles after EEMPE is written) will trigger the erase/write operation. Both the erase and write cycle are done in one operation and the total programming time is given in Table 1. The EEPE bit remains set until the erase and write operations are completed. While the device is busy with programming, it is not possible to do any other EEPROM operations.

is likely to rise or fall slowly on Power-up/down. This causes the

5.4.3 Split Byte Programming

It is possible to split the erase and write cycle in two different operations. This may be useful if the system requires short access time for some limited period of time (typically if the power supply voltage falls). In order to take advantage of this method, it is required that the locations to be written have been erased before the write operation. But since the erase and write operations are split, it is possible to do the erase operations whe n the system allows doing time-critical operations (typically after Power-up).

5.4.4 Erase

To erase a byte, the address must be written to EEAR. If the EEPMn bits are 0b01, writing the EEPE (within four cycles after EEMPE is written) will trigger the erase operation only (programming time is given in Table 1). The EEPE bit remains set until the erase operation completes. While the device is busy programming, it is not possible to do any other EEPROM operations.

5.4.5 Write

To write a location, the user must write the address into EEAR and the data into EEDR. If the EEPMn bits are 0b10, writing the EEPE (within four cycles after EEMPE is written) will trigger the write operation only (programming time is given in Table 1). The EEPE bit remains set until the write operation completes. If the location to be written has not been erased before write, the

8048B–AVR–03/09

ATtiny43U

data that is stored must be considered as lost. While the device is busy with programming, it is not possible to do any other EEPROM operations.

The calibrated Oscillator is used to time the EEPROM accesses. Make sure the Oscillator frequency is within the requirements described in “OSCCAL – Oscillator Calibration Register” on

page 28.

The following code examples show one assembly and one C function for erase, write, or atomic write of the EEPROM. The examples assume that interrupts are controlled (e.g., by disabling interrupts globally) so that no interrupts will occur during execution of these functions.

Assembly Code Example

EEPROM_write:

; Wait for completion of previous write

sbic EECR,EEPE

rjmp EEPROM_write

; Set Programming mode

ldi r16, (0<<EEPM1)|(0<<EEPM0)

out EECR, r16

; Set up address (r17) in address register

out EEAR, r17

; Write data (r19) to data register

out EEDR,r19

; Write logical one to EEMPE

sbi EECR,EEMPE

; Start eeprom write by setting EEPE

sbi EECR,EEPE

ret

C Code Example

void EEPROM_write(unsigned char ucAddress, unsigned char ucData)

{

/* Wait for completion of previous write */

while(EECR & (1<<EEPE))

;

/* Set Programming mode */

EECR = (0<<EEPM1)|(0<<EEPM0)

/* Set up address and data registers */

EEAR = ucAddress;

EEDR = ucData;

/* Write logical one to EEMPE */

EECR |= (1<<EEMPE);

/* Start eeprom write by setting EEPE */

EECR |= (1<<EEPE);

}

8048B–AVR–03/09

The next code examples show assembly and C functions for reading the EEPROM. The examples assume that interrupts are controlled so that no interrupts will occur during execution of these functions.

Assembly Code Example

EEPROM_read:

; Wait for completion of previous write

sbic EECR,EEPE

rjmp EEPROM_read

; Set up address (r17) in address register

out EEAR, r17

; Start eeprom read by writing EERE

sbi EECR,EERE

; Read data from data register

in r16,EEDR

ret

C Code Example

unsigned char EEPROM_read(unsigned char ucAddress)

{

/* Wait for completion of previous write */

while(EECR & (1<<EEPE))

;

/* Set up address register */

EEAR = ucAddress;

/* Start eeprom read by writing EERE */

EECR |= (1<<EERE);

/* Return data from data register */

return EEDR;

}

5.4.6 Preventing EEPROM Corruption

During periods of low V too low for the CPU and the EEPROM to operate properly. These issues a re the same as for board level systems using EEPROM, and the same design solutions should be applied.

An EEPROM data corruption can be caused by two situations when the voltage is too low. First, a regular write sequence to the EEPROM requires a minimum voltage to operate correctly. Secondly, the CPU itself can execute instructions incorrectly, if the supply voltage is too low.

EEPROM data corruption can easily be avoided by following this design recommendation: Keep the AVR RESET active (low) during periods of insufficient power supply voltage. This can

be done by enabling the internal Brown-out Detector (BOD). If the detection level of the internal BOD does not match the needed detection level, an external low V be used. If a reset occurs while a write operation is in progress, the write operation will be completed provided that the power supply voltage is sufficient.

8048B–AVR–03/09

, the EEPROM data can be corrupted because the supply voltage is

reset protection circuit can

ATtiny43U

5.5 I/O Memory

The I/O space definition of the ATtiny43U is shown in “Register Summary” on page 167. All I/Os and peripherals are placed in the I/O space. All I/O locations may be accessed by the

LD/LDS/LDD and ST/STS/STD instructions, transferring data between the 32 general purpose working registers and the I/O space. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the value of single bits can be checked by using the SBIS and SBIC instruct ion s. See th e instr uc tion se t section for more details. When using the I/O sp ecific commands IN and O UT, the I/O addresses 0x00 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these addresses.

For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written.

Some of the Status Flags are cleared by writing a logical one to them. Note that, unlike most other AVRs, the CBI and SBI instructions will only operate on the specified bit, and can therefore be used on registers containing such Status Flags. The CBI and SBI instructions work with registers 0x00 to 0x1F only.

The I/O and Peripherals Control Registers are explained in later sections.

5.5.1 General Purpose I/O Registers

ATtiny43U contains three General Purpose I/O Registers. These registers can be used for storing any information, and they are particularly useful for storing global variables and status flags. General Purpose I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI, CBI, SBIS, and SBIC instructions.

5.6 Register Description

5.6.1 EEAR – EEPROM Address Register

Bit 76543210 0x1E (0x3E) - - EEAR5 EEAR4 EEAR3 EEAR2 EEAR1 EEAR0 EEAR Read/Write R R R/W R/W R/W R/W R/W R/W Initial Value 0 0 X X X X X X

• Bits 7:6 – Res: Reserved Bit

These bits are reserved and will always read zero.

• Bits 5:0 – EEAR[5:0]: EEPROM Address

The EEPROM Address Register – EEAR – specifies the EEPROM address. The EEPROM data bytes are addressed linearly in the range 0...(64-1). The initial value of EEAR is undefined. A proper value must be written before the EEPROM may be accessed.

8048B–AVR–03/09

5.6.2 EEDR – EEPROM Data Register

Bit 76543210 0x1D (0x3D) EEDR7 EEDR6 EEDR5 EEDR4 EEDR3 EEDR2 EEDR1 EEDR0 EEDR Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0

• Bits 7:0 – EEDR[7:0]: EEPROM Data

For the EEPROM write operation the EEDR Register contains the data to be written to the EEPROM in the address given by the EEAR Register. For the EEPROM read operation, the EEDR contains the data read out from the EEPROM at the address given by EEAR.

5.6.3 EECR – EEPROM Control Register

Bit 76543210 0x1C (0x3C) – – EEPM1 EEPM0 EERIE EEMPE EEPE EERE EECR Read/Write R R R/W R/W R/W R/W R/W R/W Initial Value 0 0 X X 0 0 X 0

• Bit 7 – Res: Reserved Bit

These bits are reserved and will always read zero. For compatibility with future AVR devic es, always write this bit to zero. After reading, mask out this bit.

• Bit 6 – Res: Reserved Bit

These bits are reserved and will always read zero.

• Bits 5, 4 – EEPM1 and EEPM0: EEPROM Mode Bits

The EEPROM Programming mode bits setting defines which programming action that will be triggered when writing EEPE. It is possible to program data in on e atomic operation (e rase the old value and program the new value) or to split the Erase and Write operations in two different operations. The Programming t imes fo r the d ifferen t modes ar e shown in Table 5- 1. While EEPE is set, any write to EEPMn will be ignored. During reset, the EEPMn bits will be reset to 0b00 unless the EEPROM is busy programming.

Table 5-1. EEPROM Mode Bits

Programming

EEPM1 EEPM0

0 0 3.4 ms Erase and Write in one operation (Atomic Operation) 0 1 1.8 ms Erase Only 1 0 1.8 ms Write Only 1 1 – Reserved for future use

Time Operation

• Bit 3 – EERIE: EEPROM Ready Interrupt Enable

Writing EERIE to one enables the EEPROM Ready Interrupt if the I-bit in SREG is set. Writing EERIE to zero disables the interrupt. The EEPROM Ready Interrupt generates a constant interrupt when Non-volatile memory is ready for programming.

• Bit 2 – EEMPE: EEPROM Master Program Enable

The EEMPE bit determines whether writing EEPE to one will have effect or not.

8048B–AVR–03/09

ATtiny43U

When EEMPE is set, setting EEPE within four clock cycles will program the EEPROM at the selected address. If EEMPE is zero, setting EEPE will have no effect. When EEMPE has been written to one by software, hardware clears the bit to zero after four clock cycles.

• Bit 1 – EEPE: EEPROM Program Enable

The EEPROM Program Enable Signal EEPE is the programming enable signal to the EEPROM. When EEPE is written, the EEPROM will be programmed according to the EEPMn bits setting. The EEMPE bit must be written to one before a logical one is written to EEPE, otherwise no EEPROM write takes place. When the write access time has elapsed, the EEPE bit is cleared by hardware. When EEPE has been set, the CPU is halted for two cycles before the next instruction is executed.

• Bit 0 – EERE: EEPROM Read Enable

The EEPROM Read Enable Signal – EERE – is the read strobe to the EEPROM. When the correct address is set up in the EEAR Register, the EERE bit must be written to one to trigger the EEPROM read. The EEPROM read access takes one instruction, and the requested data is available immediately. When the EEPROM is read, the CPU is halted for four cycles before the next instruction is executed. The user should poll the EEPE bit before starting the read operation. If a write operation is in progress, it is neither possible to read the EEPROM, nor to change the EEAR Register.

5.6.4 GPIOR2 – General Purpose I/O Regist er 2

Bit 76543210 0x15 (0x35) MSB LSB GPIOR2 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0

5.6.5 GPIOR1 – General Purpose I/O Regist er 1

Bit 76543210 0x14 (0x34) MSB LSB GPIOR1 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0

5.6.6 GPIOR0 – General Purpose I/O Regist er 0

Bit 76543210 0x13 (0x33) MSB LSB GPIOR0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0

8048B–AVR–03/09

6. System Clock and Clock Options

6.1 Clock Systems and their Distribution

Figure 6-1 presents the principal clock systems in the AVR and their distribution. All of the clocks

need not be active at a given time. In order to reduce power consump tion, th e cloc ks to modules not being used can be halted by using different sleep modes, as described in “Power Manage-

ment and Sleep Modes” on page 31. The clock systems are detailed below.

Figure 6-1. Clock Distribution

General I/O

Modules

clk

I/O

External Clock

ADC

clk

AVR Clock

Control Unit

System Clock

Prescaler

Source clock

Clock

Multiplexer

ADC

CPU Core RAM

clk

CPU

clk

FLASH

Reset Logic

Watchdog Timer

Watchdog clock

Watchdog

Oscillator

Flash and EEPROM

Calibrated RC

Oscillator

6.1.1 CPU Clock – clk

The CPU clock is routed to parts of the system concerned with operation of the AVR core. Examples of such modules are the General Purpose Register File, the Status Register and the data memory holding the Stack Pointer. Halting the CPU clock inhibits the core from performing general operations and calculations.

6.1.2 I/O Clock – clk

I/O

The I/O clock is used by the majority of the I/O modules, like Timer/Counters. The I/O clock is also used by the External Interrupt module, but note that some external interrupts are detected by asynchronous logic, allowing such interrupts to b e detected even if the I/O clock is halted. Also note that start condition detection in the USI module is carried out asynchronously when clk

6.1.3 Flash Clock – clk

The Flash clock controls operation of the Flash inte rface. The Fla sh clock is usually active simultaneously with the CPU clock.

8048B–AVR–03/09

CPU

is halted.

I/O

FLASH

ATtiny43U

6.1.4 ADC Clock – clk

EXTERNAL

CLOCK

SIGNAL

CLKI

GND

6.2 Clock Sources

ADC

The ADC is provided with a dedicated clock domain. This allows halting the CPU and I/O clocks in order to reduce noise generated by digital cir cuit ry. Th is gives mo re accurat e ADC conversion results.

The device has the following clock source options, selec table by Flash Fuse bits as shown below. The clock from the selected so ur ce is i npu t to th e AVR clo c k gene ra to r, and r ou te d to t he appropriate modules.

6.2.1 External Clock

Table 6-1. Device Clocking Options Select

Device Clocking Option CKSEL3..0

External Clock (see page 24) 0000 Calibrated Internal 8 MHz Oscillator (see page 25) 0010 Internal 128 kHz Oscillator (see page 26) 0011 Reserved 0001, 0100-1111

Note: 1. For all fuses “1” means unprogrammed while “0” means programmed.

To drive the device from an external clock source, CLKI should be driven as shown in Figure 6-2

on page 24. To run the device on an external clock, the CKSEL Fuses must be programmed to

“0000” (see Table 6-2).

Table 6-2. Crystal Oscillator Clock Frequency

CKSEL3..0 Frequency

0000 0 - 8 MHz

Figure 6-2. External Clock Drive Configuration

(1)

8048B–AVR–03/09

When this clock source is selected, start-up times are determined by SUT Fuses as shown in

Table 6-3.

Table 6-3. Start-up Times for the External Clock Selection

SUT1..0

00 6 CK 14CK BOD enabled 01 6 CK 14CK + 4 ms Fast rising power 10 6 CK 14CK + 64 ms Slowly rising power 11 Reserved

from Power-down

When applying an external clock, it is required to avoid sudden changes in the applied clock frequency to ensure stable operation of the MCU. A variation in frequency of more than 2% from one clock cycle to the next can lead to unpredictable behavior. If changes of more than 2% is required, ensure that the MCU is kept in Reset during the changes.

Note that the System Clock Prescaler can be used to implement run-ti me changes of the int ernal clock frequency while still ensuring stable operation. Refer to “Power Management and Sleep

Modes” on page 31 for details.

6.2.2 Calibrated Internal 8 MHz Oscillator

By default, the Internal RC Oscillator provides an approximate 8.0 MHz clock. Though voltage and temperature dependent, this clock can be very accurately calibrated by the user. See Table

20-2 on page 157 for more details. The device is shipped with the CKDIV8 Fuse programmed.

See “System Clock Prescaler” on page 27 for more details.

Start-up Time

Additional Delay

from Reset Recommended Usage

This clock may be selected as the system cloc k by p rogr am m in g th e CKS E L Fus es a s sh own in

Table 6-4. If selected, it will operate with no external components. During reset, hardware loads

the pre-programmed calibration value into th e OSCCAL Re giste r a nd the reby aut omat ica lly calibrates the RC Oscillator. The accuracy of this calibration is shown as Factory calibration in

Table 20-2 on page 157.

By changing the OSCCAL register from SW, see “OSCCAL – Oscillator Calibration Register” on

page 28, it is possible to get a higher calibration accuracy than by using the factory calibration.

The accuracy of this calibration is shown as User calibration in Table 20-2 on page 157. When this Oscillator is used as the chip clock, the Watchdog Oscillator will still be used for the

Watchdog Timer and for the Reset Time-out. For more information on the pre-programmed calibration value, see the section “Calibration Byte” on page 142.

Table 6-4. Internal Calibrated RC Oscillator Operating Modes

CKSEL3..0 Nominal Frequency (MHz)

(1)

0010

Notes: 1. The device is shipped with this option selected.

8.0

8048B–AVR–03/09

ATtiny43U

When this Oscillator is selected, start-up times are determined by the SUT Fuses as shown in

Table 6-5 below.

Table 6-5. Start-up times for Internal Calibrated RC Oscillator Clock Selection

SUT1..0

00 6 CK 14CK 01 6 CK 14CK + 4 ms Fast rising power

(2)

11 Reserved

Note: 1. If the RSTDISBL fuse is programmed, this start-up time will be increased to

2. The device is shipped with this option selected.

6.2.3 Internal 128 kHz Oscillator

The 128 kHz internal oscillator is a low power oscillator providing a clock of 128 kHz. The frequency is nominal at 3V and 25°C. This clock may be select as the system clock by programming the CKSEL Fuses to “11” as shown in Table 6-6 below.

Table 6-6. 128 kHz Internal Oscillator Operating Modes

When this clock source is selected, start-up times are determined by the SUT Fuses as shown in

Table 6-7 below.

Start-up Time

from Power-down

6 CK 14CK + 64 ms Slowly rising power

14CK + 4 ms to ensure programming mode can be entered.

CKSEL3..0 Nominal Frequency

0011 128 kHz

Additional Delay from

Reset (VCC = 5.0V) Recommended Usage

(1)

BOD enabled

Table 6-7. Start-up Times for the 128 kHz Internal Oscillator

SUT1..0

00 6 CK 14CK 01 6 CK 14CK + 4 ms Fast rising power 10 6 CK 14CK + 64 ms Slowly rising power 11 Reserved

Note: 1. If the RSTDISBL fuse is programmed, this start-up time will be increased to 14CK + 4 ms to

6.2.4 Default Clock Source

The device is shipped with CKSEL = "0010", SUT = "10", and CKDIV8 programmed. The default clock source is therefore the internal RC oscillator running at 8.0 MHz with the longest start-up time and an initial system clock prescale setting of 8, resulting in a 1 MHz system clock. The default setting ensures every user can make the desired clock sou rce setting using any available programming interface.

Start-up Time

from Power-down

ensure programming mode can be entered.

Additional Delay

from Reset Recommended Usage

(1)

BOD enabled

8048B–AVR–03/09

6.2.5 Clock Startup Sequence

Any clock source needs a sufficient V cycles before it can be considered stable.

to start oscillating and a minimum number of oscillating

To ensure sufficient V

, the device issues an internal reset with a time-out delay (t

TOUT

) after the device reset is released by all other reset sources. The section “System Control and Reset”

on page 48 describes the start conditions for the internal reset. T he delay (t

) is timed from

TOUT

the Watchdog Oscillator and the number of cycles in the delay is set by the SUTn and CKSELn fuse bits. The available delays are shown in Table 6-8.

Table 6-8. Number of Watchdog Oscillator Cycles

Typ Time-out (VCC = 5.0V) Typ Time-out (VCC = 3.0V) Number of Cycles

0 ms 0 ms 0

4.1 ms 4.3 ms 512 65 ms 69 ms 8K (8,192)

Note: The frequency of the Watchdog Oscillator is voltage dependent as shown in TBD.

The main purpose of the delay is to keep the AVR in reset until VCC has risen to a sufficient level. The delay will not monitor the actual voltage and, hence, the user must make sure the delay time is longer than the V tion circuit should be used. A BOD circuit ensures there is sufficie nt V

rise time. If this is not possible, an internal or external Brown-Out Detec-

before it releases the

reset line, and the time-out delay can then be disabled. It is not recommended to disable the time-out delay without implementing a Brown-Out Detection circuit.

The oscillator is required to oscillate for a minimum number of cycles before the clock is considered stable. An internal ripple counter monitors the oscillator output clock, and keeps the internal reset active for a given number of clock cycles. The reset is then released and the device will start to execute.

The start-up sequence for the clock includes both the time-out delay and the start-up time when the device starts up from reset. When star ting up from Power- down mode , V at a sufficient level and only the start-up time is included.

6.3 System Clock Prescaler

The ATtiny43U has a system clock prescaler, which means the system clock can be divided as described in section “CLKPR – Clock Prescale Register” on page 28. This feature can be used to lower system clock frequency and decrease the power consumption at times when requirements for processing power is low. This can be used with all clock source options, and it will affect the clock frequency of the CPU and all synchronous peripherals. Clock signals clk clk

, clk

ADC

6.3.1 Switching Time

When changing prescaler settings, the System Clock Prescaler ensures that no glitches occurs in the clock system. It also ensures that no inter mediate fr equency is hi gher th an eit her the clock frequency corresponding to the previous setting or the clock frequency corresponding to the new setting. The ripple counter of the prescaler runs at the same frequency as the undivided clock, which may be higher than the CPU's clock frequency. Hence, even if it was readable, it is not possible to determine the state of the prescaler, and it is not possible to predict the exact time it takes to switch from one clock division to the other. From the time the CLKPS values are written,

8048B–AVR–03/09

CPU

, and clk

are divided by a factor as shown in Table 20-4 on page 158.

FLASH

is assumed to be

I/O

ATtiny43U

it takes between T1 + T2 and T1 + 2 * T2 before the new clock frequency is active. In this interval, two active clock edges are produced. Here, T1 is the previous clock period, and T2 is the period corresponding to the new prescaler setting.

6.4 Clock Output Buffer

The device can output the system clock on the CLKO pin. To enable the output, the CKOUT Fuse has to be programmed. This mode is suit able when the chip clock is u sed to drive other circuits on the system. The clock also will be output during reset, and the normal operation of I/O pin will be overridden when the fuse is programmed. Any clock source, including the internal RC Oscillator, can be selected when the clock is output on CLKO. If the System Clock Prescaler is used, it is the divided system clock that is output.

6.5 Register Description

6.5.1 OSCCAL – Oscillator Calibration Register

Bit 76543210

CAL7 CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 OSCCAL

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value Device Specific Calibration Value

• Bits 7:0 – CAL[7:0]: Oscillator Calibration Value

The Oscillator Calibration Register is used to trim the Calibrated Internal RC Oscillator to remove process variations from the oscillator frequency. A pre-programmed calibration value is automatically written to this register during chip reset, giving the Factory calibrated frequency as specified in Table 20-2 on page 157. The application software can write this register to change the oscillator frequency. The oscillator can be calibrated to frequencies as specified in Table 20-

2 on page 157. Calibration outside that range is not guaranteed.

Note that this oscillator is used to time EEPROM and Flash write accesses, and these write times will be affected accordingly. If the EEPROM or Flash are written, do not calibrate to more than 8.8 MHz. Otherwise, the EEPROM or Flash write may fail.

The CAL7 bit determines the range of operation for the oscillator. Setting this bit to 0 gives the lowest frequency range, setting this bit to 1 gives the highest frequency range. The two frequency ranges are overlapping, in other words a setting of OSCCAL = 0x7F gives a higher frequency than OSCCAL = 0x80.

The CAL6..0 bits are used to tune the frequency within the selected range. A setting of 0x00 gives the lowest frequency in that r ange, and a setting of 0x7F g ives the high est freq uency in the range.

6.5.2 CLKPR – Clock Prescale Register

Bit 76543210

CLKPCE – – – CLKPS3 CLKPS2 CLKPS1 CLKPS0 CLKPR

Read/Write R/W R R R R/W R/W R/W R/W Initial Value 0 0 0 0 See Bit Description

• Bit 7 – CLKPCE: Clock Prescaler Change Enable

The CLKPCE bit must be written to logic one to enable change of the CLKPS bits. The CLKPCE bit is only updated when the other bits in CLKPR are simultaneously written to zero. CLKPCE is

8048B–AVR–03/09

cleared by hardware four cycles after it is written or when CLKPS bits are written. Rewriting the CLKPCE bit within this time-out period does neither extend the time-out period, nor clear the CLKPCE bit.

• Bits 3:0 – CLKPS[3:0]: Clock Prescaler Select Bits 3 - 0

These bits define the division factor between the selected clock source and the internal system clock. These bits can be written run-time to vary the clock frequency to suit the application requirements. As the divider divides the master clock input to t he MCU, the speed o f all synchronous peripherals is affected. The division factors are given in Table 6-9.

The CKDIV8 Fuse determines the initial value of the CLKPS bits. If CKDIV8 is unprogrammed, the CLKPS bits will be reset to “0000”. If CKDIV8 is programmed, CLKPS bits are reset to “0011”, giving a division factor of 8 at start up. This feature should be used if the selected clock source has a higher frequency than the maximum frequency of the device at the present operating conditions. Note that any value can be written to the CLKPS bits regardless of the CKDIV8 Fuse setting. The Application software must ensure that a sufficient division factor is chosen if the selected clock source has a higher frequency than the maximum frequency of the device at

the present operating conditions. The device is shipped with the CKDIV8 Fuse programmed.

Table 6-9. Clock Prescaler Select

CLKPS3 CLKPS2 CLKPS1 CLKPS0 Clock Division Factor

0000 1 0001 2 0010 4 0011 8 0100 16 0101 32 0110 64 0111 128 1000 256 1001 Reserved 1010 Reserved 1011 Reserved 1100 Reserved 1101 Reserved 1110 Reserved 1111 Reserved

To avoid unintentional changes of clock frequency, a special write procedure must be followed to change the CLKPS bits:

1. Write the Clock Prescaler Change Enable (CLKPCE) bit to one and all other bitsin CLKPR to zero.

2. Within four cycles, write the desired value to CLKPS while writing a zero to CLKPCE.

8048B–AVR–03/09

ATtiny43U

Interrupts must be disabled when changing prescaler setting to make sure t he write procedur e is not interrupted.

8048B–AVR–03/09

+ 152 hidden pages