Rainbow Electronics ATtiny26L User Manual
Features
• High-performance, Low-power AVR
• RISC Architecture
– 118 Powerful Instructions – Most Single Clock Cycle Execution
– 32 x 8 General Purpose Working Registers
– Fully Static Operation
– Up to 16 MIPS Throughput at 16 MHz
• Data and Non-volatile Program Memory
– 2K Bytes of In-System Programmable Program Memory Flash
Endurance: 1,000 Write/Erase Cycles
– 128 Bytes of In-System Programmable EEPROM
Endurance: 100,000 Write/Erase Cycles
– 128 Bytes Internal SRAM
– Programming Lock for Flash Program and EEPROM Data Security
• Peripheral Features
– 8-bit Timer/Counter with Separate Prescaler
– 8-bit High-speed Timer with Separate Prescaler
2 High Frequency PWM Outputs with Separate Output Compare Registers
Non-overlapping Inverted PWM Output Pins
– Universal Serial Interface with Start Condition Detector
– 10-bit ADC
11 Single Ended Channels
8 Differential ADC Channels
7 Differential ADC Channel Pairs with Programmable Gain (1x, 20x)
– On-chip Analog Comparator
– External Interrupt
– Pin Change Interrupt on 11 Pins
– Programmable Watchdog Timer with Separate On-chip Oscillator
• Special Microcontroller Features
– Low Power Idle, Noise Reduction, and Power-down Modes
– Power-on Reset and Programmable Brown-out Detection
– External and Internal Interrupt Sources
– In-System Programmable via SPI Port
– Internal Calibrated RC Oscillator
• I/O and Packages
– 20-lead PDIP/SOIC: 16 Programmable I/O Lines
• Operating Voltages
– 2.7V - 5.5V for ATtiny26L
– 4.5V - 5.5V for ATtiny26
• Speed Grades
– 0 - 8 MHz for ATtiny26L
– 0 - 16 MHz for ATtiny26
®
8-bit Microcontroller
8-bit
Microcontroller
with 2K Bytes
Flash
ATtiny26
ATtiny26L
Preliminary
Rev. 1477B–AVR–04/02
1
Pin Configuration
PDIP/SOIC/SSOP
(MOSI/DI/SDA/OC1A) PB0
(MISO/DO/OC1A) PB1
(SCK/SCL/OC1B) PB2
(OC1B) PB3
VCC
GND
(ADC7/XTAL1) PB4
(ADC8/XTAL2) PB5
(ADC9/INT0/T0) PB6
(ADC10/RESET) PB7
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
MLF Top View
PB2 (SCK/SCL/OC1B)
PB1 (MISO/DO/OC1A)
PB0 (MOSI/DI/SDA/OC1A)
NCNCNC
PA0 (ADC0)
PA0 (ADC0)
PA1 (ADC1)
PA2 (ADC2)
PA3 (AREF)
GND
AVCC
PA4 (ADC3)
PA5 (ADC4)
PA6 (ADC5/AIN0)
PA7 (ADC6/AIN1)
PA1 (ADC1)
NC
(OC1B) PB3
NC
VCC
GND
NC
(ADC7/XTAL1) PB4
(ADC8/XTAL2) PB5
32313029282726
1
2
3
4
5
6
7
8
9
10111213141516
NC
(ADC9/INT0/T0) PB6
NC
(ADC6/AIN1) PA7
(ADC10/RESET) PB7
25
NC
24
PA2 (ADC2)
23
PA3 (AREF)
22
GND
21
NC
20
NC
19
AVCC
18
PA4 (ADC3)
17
NC
(ADC4) PA5
(ADC5/AIN0) PA6
Disclaimer Typical values contained in this data sheet are based on simulations and characteriza-
tion of other AVR microcontrollers manufactured on the same process technology. Min
and Max values will be available after the device is characterized.
2
ATtiny26(L)
1477B–AVR–04/02
ATtiny26(L)
Description The ATtiny26/L is a low-power CMOS 8-bit microcontroller based on the AVR enhanced
RISC architecture. By executing powerful instructions in a single clock cycle, the
ATtiny26/L achieves throughputs approaching 1 MIPS per MHz allowing the system
designer to optimize power consumption versus processing speed.
The AVR core combines a rich instruction set with 32 general purpose working registers.
All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing
two independent registers to be accessed in one single instruction executed in one clock
cycle. The resulting architecture is more code efficient while achieving throughputs up to
ten times faster than conventional CISC microcontrollers. The ATtiny26/L has a high
precision ADC with up to 11 single ended channels and 8 differential channels. Seven
differential channels have an optional gain of 20x. Four out of the seven differential
channels, which have the optional gain, can be used at the same time. The ATtiny26/L
also has a high frequency 8-bit PWM module with two independent outputs. Two of the
PWM outputs have inverted non-overlapping output pins ideal for synchronous rectification. The Universal Serial Interface of the ATtiny26/L allows efficient software
implementation of TWI (Two-wire Serial Interface) or SM-bus interface. These features
allow for highly integrated battery charger and lighting ballast applications, low-end thermostats, and firedetectors, among other applications.
The ATtiny26/L provides 2K bytes of Flash, 128 bytes EEPROM, 128 bytes SRAM, up
to 16 general purpose I/O lines, 32 general purpose working registers, two 8-bit
Timer/Counters, one with PWM outputs, internal and external Oscillators, internal and
external interrupts, programmable Watchdog Timer, 11-channel, 10-bit Analog to Digital
Converter with two differential voltage input gain stages, and four software selectable
power saving modes. The Idle mode stops the CPU while allowing the Timer/Counters
and interrupt system to continue functioning. The ATtiny26/L also has a dedicated ADC
Noise Reduction mode for reducing the noise in ADC conversion. In this sleep mode,
only the ADC is functioning. The Power-down mode saves the register contents but
freezes the oscillators, disabling all other chip functions until the next interrupt or hardware reset. The Standby mode is the same as the Power-down mode, but external
oscillators are enabled. The wakeup or interrupt on pin change features enable the
ATtiny26/L to be highly responsive to external events, still featuring the lowest power
consumption while in the Power-down mode.
1477B–AVR–04/02
The device is manufactured using Atmel’s high density non-volatile memory technology.
By combining an enhanced RISC 8-bit CPU with Flash on a monolithic chip, the
ATtiny26/L is a powerful microcontroller that provides a highly flexible and cost effective
solution to many embedded control applications.
The ATtiny26/L AVR is supported with a full suite of program and system development
tools including: Macro assemblers, program debugger/simulators, In-circuit emulators,
and evaluation kits.
3
Block Diagram Figure 1. The ATtiny26/L Block Diagram
VCC
GND
AVCC
PROGRAM
COUNTER
PROGRAM
FLASH
INSTRUCTION
REGISTER
INSTRUCTION
DECODER
CONTROL
LINES
PROGRAMMING
LOGIC
STACK
POINTER
SRAM
GENERAL
PURPOSE
REGISTERS
X
Y
Z
ALU
STATUS
REGISTER
ISP INTERFACE
8-BIT DATA BUS
INTERNAL
OSCILLATOR
WATCHDOG
TIMER
MCU CONTROL
REGISTER
MCU STATUS
REGISTER
TIMER/
COUNTER0
TIMER/
COUNTER1
UNIVERSAL
SERIAL
INTERFACE
INTERRUPT
UNIT
EEPROM
INTERNAL
CALIBRATED
OSCILLATOR
TIMING AND
CONTROL
OSCILLATORS
+
-
DATA REGISTER
PORT A
ANALOG
COMPARATOR
DATA DIR.
REG.PORT A
PORT A DRIVERS
PA0-PA7
ADC
DATA REGISTER
PORT B
PORT B DRIVERS
PB0-PB7
DATA DIR.
REG.PORT B
4
ATtiny26(L)
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ATtiny26(L)
Pin Descriptions
VCC Digital supply voltage pin.
GND Digital ground pin.
AVCC AVCC is the supply voltage pin for Port A and the A/D Converter (ADC). It should be
externally connected to V
connected to V
ADC.
Port A (PA7..PA0) Port A is an 8-bit general purpose I/O port. PA7..PA0 are all I/O pins that can provide
internal pull-ups (selected for each bit). Port A has alternate functions as analog inputs
for the ADC and analog comparator and pin change interrupt as described in “Alternate
Port Functions” on page 95.
Port B (PB7..PB0) Port B is an 8-bit general purpose I/O port. PB6..0 are all I/O pins that can provide inter-
nal pull-ups (selected for each bit). PB7 is an I/O pin if not used as the reset. To use pin
PB7 as an I/O pin, instead of RESET pin, program (“0”) RSTDISBL Fuse. Port B has
alternate functions for the ADC, clocking, timer counters, USI, SPI programming, and
pin change interrupt as described in “Alternate Port Functions” on page 95.
through a low-pass filter. See page 77 for details on operating of the
CC
, even if the ADC is not used. If the ADC is used, it should be
CC
An External Reset is generated by a low level on the PB7/RESET
longer than 50 ns will generate a reset, even if the clock is not running. Shorter pulses
are not guaranteed to generate a reset.
XTAL1 Input to the inverting oscillator amplifier and input to the internal clock operating circuit.
XTAL2 Output from the inverting oscillator amplifier.
pin. Reset pulses
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5
Architectural Overview
The fast-access Register File concept contains 32 x 8-bit general purpose working registers with a single clock cycle access time. This means that during one single clock
cycle, one ALU (Arithmetic Logic Unit) operation is executed. Two operands are output
from the Register File, the operation is executed, and the result is stored back in the
Register File – in one clock cycle.
Six of the 32 registers can be used as 16-bit pointers for indirect memory access. These
pointers are called the X-, Y-, and Z-pointers, and they can address the Register File
and the Flash program memory.
Figure 2. The ATtiny26/L AVR Enhanced RISC Architecture
8-bit Data Bus
Control
Registers
Interrupt
Unit
1024 x 16
Program
FLASH
Program
Counter
Status
and Test
Instruction
Register
Instruction
Decoder
Control Lines
Direct Addressing
Indirect Addressing
32 x 8
General
Purpose
Registers
ALU
128 x 8
SRAM
128 byte
EEPROM
Universal
Serial Interface
ISP Unit
2 x 8-bit
Timer/Counter
Watchdog
Timer
ADC
Analog
Comparator
I/O Lines
The ALU supports arithmetic and logic functions between registers or between a constant and a register. Single register operations are also executed in the ALU. Figure 2
shows the ATtiny26/L AVR Enhanced RISC microcontroller architecture. In addition to
the register operation, the conventional memory addressing modes can be used on the
Register File as well. This is enabled by the fact that the Register File is assigned the 32
lowermost Data Space addresses ($00 - $1F), allowing them to be accessed as though
they were ordinary memory locations.
The I/O memory space contains 64 addresses for CPU peripheral functions as Control
Registers, Timer/Counters, A/D Converters, and other I/O functions. The I/O Memory
can be accessed directly, or as the Data Space locations following those of the Register
File, $20 - $5F.
The AVR uses a Harvard architecture concept with separate memories and buses for
program and data memories. The program memory is accessed with a two stage
6
ATtiny26(L)
1477B–AVR–04/02
ATtiny26(L)
pipelining. While one instruction is being executed, the next instruction is pre-fetched
from the program memory. This concept enables instructions to be executed in every
clock cycle. The program memory is In-System programmable Flash memory.
With the relative jump and relative call instructions, the whole address space is directly
accessed. All AVR instructions have a single 16-bit word format, meaning that every
program memory address contains a single 16-bit instruction.
During interrupts and subroutine calls, the return address program counter (PC) is
stored on the Stack. The Stack is effectively allocated in the general data SRAM, and
consequently the stack size is only limited by the total SRAM size and the usage of the
SRAM. All user programs must initialize the SP in the reset routine (before subroutines
or interrupts are executed). The 8-bit Stack Pointer SP is read/write accessible in the I/O
space. For programs written in C, the stack size must be declared in the linker file. Refer
to the C user guide for more information.
The 128 bytes data SRAM can be easily accessed through the five different addressing
modes supported in the AVR architecture.
The memory spaces in the AVR architecture are all linear and regular memory maps.
The I/O memory space contains 64 addresses for CPU peripheral functions as Control
Registers, Timer/Counters, and other I/O functions. The memory spaces in the AVR
architecture are all linear and regular memory maps.
General Purpose Register File
A flexible interrupt module has its control registers in the I/O space with an additional
Global Interrupt Enable bit in the Status Register. All the different interrupts have a separate Interrupt Vector in the Interrupt Vector table at the beginning of the program
memory. The different interrupts have priority in accordance with their Interrupt Vector
position. The lower the Interrupt Vector address, the higher the priority.
Figure 3 shows the structure of the 32 general purpose working registers in the CPU.
Figure 3. AVR CPU General Purpose Working Registers
7 0 Addr.
R0 $00
R1 $01
R2 $02
…
R13 $0D
General R14 $0E
Purpose R15 $0F
Working R16 $10
Registers R17 $11
…
R26 $1A X-register Low Byte
R27 $1B X-register High Byte
R28 $1C Y-register Low Byte
R29 $1D Y-register High Byte
R30 $1E Z-register Low Byte
R31 $1F Z-register High Byte
1477B–AVR–04/02
7
All of the register operating instructions in the instruction set have direct and single cycle
access to all registers. The only exceptions are the five constant arithmetic and logic
instructions SBCI, SUBI, CPI, ANDI, and ORI between a constant and a register, and
the LDI instruction for load immediate constant data. These instructions apply to the
second half of the registers in the Register File – R16..R31. The general SBC, SUB, CP,
AND, and OR, and all other operations between two registers or on a single register
apply to the entire Register File.
As shown in Figure 3, each register is also assigned a data memory address, mapping
them directly into the first 32 locations of the user Data Space. Although not being physically implemented as SRAM locations, this memory organization provides flexibility in
access of the registers, as the X-, Y-, and Z-registers can be set to index any register in
the file.
X-register, Y-register, and Zregister
ALU – Arithmetic Logic Unit
The registers R26..R31 have some added functions to their general purpose usage.
These registers are address pointers for indirect addressing of the Data Space. The
three indirect address registers X, Y, and Z are defined as:
Figure 4. X-, Y-, and Z-register
15 0
X-register 7 0 7 0
R27 ($1B) R26 ($1A)
15 0
Y-register 7 0 7 0
R29 ($1D) R28 ($1C)
15 0
Z-register 7 0 7 0
R31 ($1F) R30 ($1E)
In the different addressing modes, these address registers have functions as fixed displacement, automatic increment and decrement (see the descriptions for the different
instructions).
The high-performance AVR ALU operates in direct connection with all 32 general purpose working registers. Within a single clock cycle, ALU operations between registers in
the Register File are executed. The ALU operations are divided into three main categories – Arithmetic, Logical, and Bit-functions.
8
ATtiny26(L)
1477B–AVR–04/02
ATtiny26(L)
In-System Programmable Flash Program Memory
The ATtiny26/L contains 2K bytes On-chip In-System Programmable Flash memory for
program storage. Since all instructions are 16- or 32-bit words, the Flash is organized as
1K x 16. The Flash memory has an endurance of at least 1,000 write/erase cycles. The
ATtiny26/L Program Counter – PC – is 10 bits wide, thus addressing the 1024 program
memory addresses, see “Memory Programming” on page 106 for a detailed description
on Flash data downloading. See “Program and Data Addressing Modes” on page 10 for
the different program memory addressing modes.
Figure 5. SRAM Organization
Register File Data Address Space
R0 $0000
R1 $0001
R2 $0002
... ...
R29 $001D
R30 $001E
R31 $001F
I/O Registers
$00 $0020
$01 $0021
$02 $0022
… …
$3D $005D
$3E $005E
$3F $005F
Internal SRAM
SRAM Data Memory Figure 5 above shows how the ATtiny26/L SRAM Memory is organized.
The lower 224 Data Memory locations address the Register File, the I/O Memory and
the internal data SRAM. The first 96 locations address the Register File and I/O Memory, and the next 128 locations address the internal data SRAM.
The five different addressing modes for the data memory cover: Direct, Indirect with Displacement, Indirect, Indirect with Pre-decrement, and Indirect with Post-increment. In
the Register File, registers R26 to R31 feature the indirect addressing pointer registers.
The direct addressing reaches the entire data space. The Indirect with Displacement
mode features a 63 address locations reach from the base address given by the Y- or Zregister.
When using register indirect addressing modes with automatic pre-decrement and postincrement, the address registers X, Y, and Z are decremented and incremented.
$0060
$0061
...
$00DE
$00DF
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The 32 general purpose working registers, 64 I/O Registers and the 128 bytes of internal data SRAM in the ATtiny26/L are all accessible through all these addressing modes.
See the next section for a detailed description of the different addressing modes.
9
Program and Data Addressing Modes
The ATtiny26/L AVR Enhanced RISC microcontroller supports powerful and efficient
addressing modes for access to the Flash program memory, SRAM, Register File, and
I/O Data memory. This section describes the different addressing modes supported by
the AVR architecture. In the figures, OP means the operation code part of the instruction
word. To simplify, not all figures show the exact location of the addressing bits.
Register Direct, Single Register Rd
Register Direct, Two Registers Rd and Rr
Figure 6. Direct Single Register Addressing
The operand is contained in register d (Rd).
Figure 7. Direct Register Addressing, Two Registers
10
Operands are contained in register r (Rr) and d (Rd). The result is stored in register d
(Rd).
ATtiny26(L)
1477B–AVR–04/02
I/O Direct Figure 8. I/O Direct Addressing
Operand address is contained in 6 bits of the instruction word. n is the destination or
source register address.
Data Direct Figure 9. Direct Data Addressing
31
OP Rr/Rd
15 0
20 19
16 LSBs
16
ATtiny26(L)
Data Space
$0000
Data Indirect with Displacement
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$00DF
A 16-bit Data Address is contained in the 16 LSBs of a two-word instruction. Rd/Rr
specify the destination or source register.
Figure 10. Data Indirect with Displacement
15
Y OR Z - REGISTER
15
OP an
Data Space
0
05610
$0000
$00DF
11
Operand address is the result of the Y- or Z-register contents added to the address contained in 6 bits of the instruction word.
Data Indirect Figure 11. Data Indirect Addressing
X-, Y-, OR Z-REGISTER
Operand address is the contents of the X-, Y-, or the Z-register.
Data Space
$0000
015
$00DF
Data Indirect with Predecrement
Data Indirect with Postincrement
Figure 12. Data Indirect Addressing with Pre-decrement
Data Space
$0000
015
X-, Y-, OR Z-REGISTER
-1
$00DF
The X-, Y-, or Z-register is decremented before the operation. Operand address is the
decremented contents of the X-, Y-, or Z-register.
Figure 13. Data Indirect Addressing with Post-increment
Data Space
$0000
015
X-, Y-, OR Z-REGISTER
12
1
$00DF
ATtiny26(L)
1477B–AVR–04/02
ATtiny26(L)
The X-, Y-, or Z-register is incremented after the operation. Operand address is the content of the X-, Y-, or Z-register prior to incrementing.
Constant Addressing Using the LPM Instruction
Indirect Program Addressing, IJMP and ICALL
Figure 14. Code Memory Constant Addressing
PROGRAM MEMORY
$000
$3FF
Constant byte address is specified by the Z-register contents. The 15 MSBs select word
address (0 - 1K), the LSB selects low byte if cleared (LSB = 0) or high byte if set
(LSB = 1).
Figure 15. Indirect Program Memory Addressing
PROGRAM MEMORY
$000
1477B–AVR–04/02
$3FF
Program execution continues at address contained by the Z-register (i.e., the PC is
loaded with the contents of the Z-register).
13
Relative Program Addressing, RJMP and RCALL
Figure 16. Relative Program Memory Addressing
+1
PROGRAM MEMORY
$000
$3FF
Program execution continues at address PC + k + 1. The relative address k is from
-2048 to 2047.
EEPROM Data Memory The ATtiny26/L contains 128 bytes of data EEPROM memory. It is organized as a sepa-
rate data space, in which single bytes can be read and written. The EEPROM has an
endurance of at least 100,000 write/erase cycles per location. The access between the
EEPROM and the CPU is described on “EEPROM Read/Write Access” on page 60
specifying the EEPROM Address Registers, the EEPROM Data Register, and the
EEPROM Control Register.
For the programming of the EEPROM See “Memory Programming” on page 106.
14
ATtiny26(L)
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ATtiny26(L)
Memory Access Times and Instruction Execution Timing
This section describes the general access timing concepts for instruction execution and
internal memory access.
The AVR CPU is driven by the System Clock Ø, directly generated from the external
clock crystal for the chip. No internal clock division is used.
Figure 17 shows the parallel instruction fetches and instruction executions enabled by
the Harvard architecture and the fast-access Register File concept. This is the basic
pipelining concept to obtain up to 1 MIPS per MHz with the corresponding unique results
for functions per cost, functions per clocks, and functions per power-unit.
Figure 17. The Parallel Instruction Fetches and Instruction Executions
T1 T2 T3 T4
System Clock Ø
1st Instruction Fetch
1st Instruction Execute
2nd Instruction Fetch
2nd Instruction Execute
3rd Instruction Fetch
3rd Instruction Execute
4th Instruction Fetch
Figure 18 shows the internal timing concept for the Register File. In a single clock cycle
an ALU operation using two register operands is executed, and the result is stored back
to the destination register.
Figure 18. Single Cycle ALU Operation
T1 T2 T3 T4
System Clock Ø
Total Execution Time
Register Operands Fetch
ALU Operation Execute
Result Write Back
The internal data SRAM access is performed in two System Clock cycles as described
in Figure 19.
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15
Figure 19. On-chip Data SRAM Access Cycles
T1 T2 T3 T4
System Clock Ø
Address
Data
WR
Data
RD
Prev. Address
Address
Write
Read
16
ATtiny26(L)
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I/O Memory The I/O space definition of the ATtiny26/L is shown in Table 1
ATtiny26(L)
Table 1. ATtiny26/L I/O Space
Address Hex Name Function
$3F ($5F) SREG Status Register
$3D ($5D) SP Stack Pointer
$3B ($5B) GIMSK General Interrupt Mask Register
$3A ($5A) GIFR General Interrupt Flag Register
$39 ($59) TIMSK Timer/Counter Interrupt Mask Register
$38 ($58) TIFR Timer/Counter Interrupt Flag Register
$35 ($55) MCUCR MCU Control Register
$34 ($54) MCUSR MCU Status Register
$33 ($53) TCCR0 Timer/Counter0 Control Register
$32 ($52) TCNT0 Timer/Counter0 (8-bit)
$31 ($51) OSCCAL Oscillator Calibration Register
$30 ($50) TCCR1A Timer/Counter1 Control Register A
$2F ($4F) TCCR1B Timer/Counter1 Control Register B
$2E ($4E) TCNT1 Timer/Counter1 (8-bit)
$2D ($4D) OCR1A Timer/Counter1 Output Compare Register A
$2C ($4C) OCR1B Timer/Counter1 Output Compare Register B
(1)
$2B ($4B) OCR1C Timer/Counter1 Output Compare Register C
$29 ($29) PLLCSR PLL Control and Status Register
$21 ($41) WDTCR Watchdog Timer Control Register
$1E ($3E) EEAR EEPROM Address Register
$1D ($3D) EEDR EEPROM Data Register
$1C ($3C) EECR EEPROM Control Register
$1B ($3B) PORTA Data Register, Port A
$1A ($3A) DDRA Data Direction Register, Port A
$19 ($39) PINA Input Pins, Port A
$18 ($38) PORTB Data Register, Port B
$17 ($37) DDRB Data Direction Register, Port B
$16 ($36) PINB Input Pins, Port B
$0F ($2F) USIDR Universal Serial Interface Data Register
$0E ($2E) USISR Universal Serial Interface Status Register
$0D ($2D) USICR Universal Serial Interface Control Register
$08 ($28) ACSR Analog Comparator Control and Status Register
$07 ($27) ADMUX ADC Multiplexer Select Register
1477B–AVR–04/02
17
Table 1. ATtiny26/L I/O Space
Address Hex Name Function
$06($26) ADCSR ADC Control and Status Register
$05($25) ADCH ADC Data Register High
$04($24) ADCL ADC Data Register Low
Note: 1. Reserved and unused locations are not shown in the table.
(1)
(Continued)
All ATtiny26/L I/O and peripheral registers are placed in the I/O space. The I/O locations
are accessed by the IN and OUT instructions transferring data between the 32 general
purpose working registers and the I/O space. I/O Registers within the address range
$00 - $1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the value of single bits can be checked by using the SBIS and SBIC instructions.
Refer to the instruction set chapter for more details. For compatibility with future
devices, reserved bits should be written zero if accessed. Reserved I/O memory
addresses should never be written.
The I/O and peripheral control registers are explained in the following sections.
Status Register – SREG The AVR Status Register – SREG – at I/O space location $3F is defined as:
Bit 76543210
$3F ($5F) I T H S V N Z C SREG
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value00000000
• Bit 7 – I: Global Interrupt Enable
The Global Interrupt Enable bit must be set (one) for the interrupts to be enabled. The
individual interrupt enable control is then performed in the Interrupt Mask Registers –
GIMSK and TIMSK. If the Global Interrupt Enable Register is cleared (zero), none of the
interrupts are enabled independent of the GIMSK and TIMSK values. The I-bit is cleared
by hardware after an interrupt has occurred, and is set by the RETI instruction to enable
subsequent interrupts. The I-bit can also be set and cleared by the application with the
SEI and CLI instructions, as described in the instruction set reference.
• Bit 6 – T: Bit Copy Storage
The Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source
and destination for the operated bit. A bit from a register in the Register File can be copied into T by the BST instruction, and a bit in T can be copied into a bit in a register in the
Register File by the BLD instruction.
• Bit 5 – H: Half Carry Flag
The Half Carry Flag H indicates a Half Carry in some arithmetic operations. See the
Instruction Set Description for detailed information.
• Bit 4 – S: Sign Bit, S = N
⊕ V
The S-bit is always an exclusive or between the Negative Flag N and the Two’s Complement Overflow Flag V. See the Instruction Set Description for detailed information.
18
• Bit 3 – V: Two’s Complement Overflow Flag
The Two’s Complement Overflow Flag V supports two’s complement arithmetics. See
the Instruction Set Description for detailed information.
ATtiny26(L)
1477B–AVR–04/02
ATtiny26(L)
• Bit 2 – N: Negative Flag
The Negative Flag N indicates a negative result after the different arithmetic and logic
operations. See the Instruction Set Description for detailed information.
• Bit 1 – Z: Zero Flag
The Zero Flag Z indicates a zero result after the different arithmetic and logic operations. See the Instruction Set Description for detailed information.
• Bit 0 – C: Carry Flag
The Carry Flag C indicates a carry in an arithmetic or logic operation. See the Instruction
Set Description for detailed information.
Stack Pointer – SP The ATtiny26/L Stack Pointer is implemented as an 8-bit register in the I/O space loca-
tion $3D ($5D). As the ATtiny26/L data memory has 224 ($E0) locations, eight bits are
used.
Bit 76543210
$3D ($5D) SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 SP
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value00000000
The Stack Pointer points to the data SRAM stack area where the Subroutine and Interrupt Stacks are located. This Stack space in the data SRAM must be defined by the
program before any subroutine calls are executed or interrupts are enabled. The Stack
Pointer must be set to point above $60. The Stack Pointer is decremented by one when
data is pushed onto the Stack with the PUSH instruction, and it is decremented by two
when an address is pushed onto the Stack with subroutine calls and interrupts. The
Stack Pointer is incremented by one when data is popped from the Stack with the POP
instruction, and it is incremented by two when an address is popped from the Stack with
return from subroutine RET or return from interrupt RETI.
1477B–AVR–04/02
19
Reset and Interrupt Handling
The ATtiny26/L provides eleven interrupt sources. These interrupts and the separate
Reset Vector, each have a separate program vector in the program memory space. All
the interrupts are assigned individual enable bits which must be set (one) together with
the I-bit in the Status Register in order to enable the interrupt.
The lowest addresses in the program memory space are automatically defined as the
Reset and Interrupt vectors. The complete list of vectors is shown in Table 2. The list
also determines the priority levels of the different interrupts. The lower the address the
higher is the priority level. RESET has the highest priority, and next is INT0 – the External Interrupt Request 0 etc.
Table 2. Reset and Interrupt Vectors
Vector No Program Address Source Interrupt Definition
1 $000 RESET Hardware Pin and Watchdog Reset
2 $001 INT0 External Interrupt Request 0
3 $002 I/O Pins Pin Change Interrupt
4 $003 TIMER1, CMPA Timer/Counter1 Compare Match 1A
5 $004 TIMER1, CMPB Timer/Counter1 Compare Match 1B
6 $005 TIMER1, OVF1 Timer/Counter1 Overflow
7 $006 TIMER0, OVF0 Timer/Counter0 Overflow
8 $007 USI_STRT USI Start
9 $008 USI_OVF USI Overflow
A $009 EE_RDY EEPROM Ready
B $00A ANA_COMP Analog Comparator
C $00B ADC ADC Conversion Complete
The most typical and general program setup for the Reset and Interrupt Vector
Addresses are:
Address Labels Code Comments
$000 rjmp RESET ; Reset handler
$001 rjmp EXT_INT0 ; IRQ0 handler
$002 rjmp PIN_CHANGE ; Pin change handler
$003 rjmp TIM1_CMP1A ; Timer1 compare match 1A
$004 rjmp TIM1_CMP1B ; Timer1 compare match 1B
$005 rjmp TIM1_OVF ; Timer1 overflow handler
$006 rjmp TIM0_OVF ; Timer0 overflow handler
$007 rjmp USI_STRT ; USI Start handler
$008 rjmp USI_OVF ; USI Overflow handler
$009 rjmp EE_RDY ; EEPROM Ready handler
$00A rjmp ANA_COMP ; Analog Comparator handler
$00B rjmp ADC ; ADC Conversion Handler
;
$009 RESET: ldi r16, RAMEND ; Main program start
$00A out SP, r16
$00B sei
… … … …
20
ATtiny26(L)
1477B–AVR–04/02
Reset Sources The ATtiny26/L provides four sources of reset:
• Power-on Reset. The MCU is reset when the supply voltage is below the Power-on
Reset threshold (V
POT
).
• External Reset. To use the PB7/RESET pin as an External Reset, instead of I/O pin,
unprogram (“1”) the RSTDISBL Fuse. The MCU is reset when a low level is present
on the RESET
pin for more than 50 ns.
• Watchdog Reset. The MCU is reset when the Watchdog timer period expires and
the Watchdog is enabled.
• Brown-out Reset. The MCU is reset when the supply voltage V
Brown-out Reset threshold (V
BOT
).
During reset, all I/O Registers are then set to their initial values, and the program starts
execution from address $000. The instruction placed in address $000 must be an RJMP
– Relative Jump – instruction to the reset handling routine. If the program never enables
an interrupt source, the interrupt vectors are not used, and regular program code can be
placed at these locations. Figure 20 shows the reset logic for the ATtiny26/L. Table 3
shows the timing and electrical parameters of the reset circuitry for ATtiny26/L.
Figure 20. Reset Logic for the ATtiny26/L
DATA BU S
ATtiny26(L)
is below the
CC
BODEN
BODLEVEL
Brown-Out
Reset Circuit
Clock
Generator
CKSEL[3:0]
MCU Status
Register (MCUSR)
BORF
PORF
CK
WDRF
EXTRF
Delay Counters
TIMEOUT
1477B–AVR–04/02
21
0
Table 3. Reset Characteristics
Symbol Parameter Condition Min Typ Max Units
V
POT
Power-on Reset Threshold
Voltage (rising)
Power-on Reset Threshold
Voltage (falling)
(1)
1.4 2.3 V
1.3 2.3 V
V
RST
t
RST
V
BOT
t
BOD
V
HYST
Notes: 1. The Power-on Reset will not work unless the supply voltage has been below V
RESET Pin Threshold Voltage 0.1 0.9 V
Minimum pulse width on
RESET
Brown-out Reset Threshold
Vol ta ge
Pin
(2)
Minimum low voltage period for
Brown-out Detection
BODLEVEL = 1 2.5 2.7 3.2
BODLEVEL = 0 3.7 4.0 4.2
BODLEVEL = 1 2 µs
BODLEVEL = 0 2 µs
50 ns
CC
V
Brown-out Detector hysteresis 130 mV
POT
(falling)
2. V
may be below nominal minimum operating voltage for some devices. For
BOT
devices where this is the case, the device is tested down to V
CC
= V
during the
BOT
production test. This guarantees that a Brown-out Reset will occur before V
CC
drops
to a voltage where correct operation of the microcontroller is no longer guaranteed.
The test is performed using BODLEVEL=1 for ATtiny26L and BODLEVEL=0 for
ATtiny26. BODLEVEL=1 is not applicable for ATtiny26.
See start-up times from reset from “System Clock and Clock Options” on page 25.
When the CPU wakes up from Power-down, only the clock counting part of the start-up
time is used. The Watchdog Oscillator is used for timing the real-time part of the start-up
time.
Power-on Reset A Power-on Reset (POR) pulse is generated by an On-chip Detection circuit. The detec-
tion level is defined in Table 3 The POR is activated whenever V
is below the
CC
detection level. The POR circuit can be used to trigger the Start-up Reset, as well as
detect a failure in supply voltage.
22
ATtiny26(L)
The Power-on Reset (POR) circuit ensures that the device is reset from Power-on.
Reaching the Power-on Reset threshold voltage invokes a delay counter, which determines the delay, for which the device is kept in RESET after V
rise. The time-out
CC
period of the delay counter can be defined by the user through the CKSEL Fuses. The
different selections for the delay period are presented in “System Clock and Clock
Options” on page 25. The RESET signal is activated again, without any delay, when the
decreases below detection level.
V
CC
1477B–AVR–04/02
Figure 21. MCU Start-up, RESET Tied to VCC
V
VCC
RESET
TIME-OUT
INTERNAL
RESET
POT
V
RST
t
TOUT
Figure 22. MCU Start-up, RESET Controlled Externally
V
VCC
RESET
POT
V
RST
ATtiny26(L)
t
TIME-OUT
INTERNAL
RESET
TOUT
External Reset An External Reset is generated by a low level on the RESET
than 500 ns will generate a reset, even if the clock is not running. Shorter pulses are not
guaranteed to generate a reset. When the applied signal reaches the Reset Threshold
Voltage – V
period t
TOUT
– on its positive edge, the delay timer starts the MCU after the Time-out
RST
has expired.
Figure 23. External Reset During Operation
VCC
RESET
TIME-OUT
V
RST
t
TOUT
pin. Reset pulses longer
1477B–AVR–04/02
INTERNAL
RESET
23
Brown-out Detection ATtiny26/L has an On-chip Brown-out Detection (BOD) circuit for monitoring the V
level during the operation. The BOD circuit can be enabled/disabled by the fuse
BODEN. When the BOD is enabled (BODEN programmed), and V
the trigger level, the Brown-out Reset is immediately activated. When V
decreases below
CC
increases
CC
above the trigger level, the Brown-out Reset is deactivated after a delay. The delay is
defined by the user in the same way as the delay of POR signal, in Table 2. The trigger
level for the BOD can be selected by the fuse BODLEVEL to be 2.7V (BODLEVEL
unprogrammed), or 4.0V (BODLEVEL programmed). The trigger level has a hysteresis
of 50 mV to ensure spike free Brown-out Detection.
CC
The BOD circuit will only detect a drop in V
for longer than t
given in Table 3.
BOD
if the voltage stays below the trigger level
CC
Figure 24. Brown-out Reset During Operation
V
CC
V
BOT-
V
BOT+
RESET
t
TIME-OUT
TOUT
INTERNAL
RESET
Watchdog Reset When the Watchdog times out, it will generate a short reset pulse of one CK cycle dura-
tion. On the falling edge of this pulse, the delay timer starts counting the Time-out period
. Refer to page 58 for details on operation of the Watchdog.
t
TOUT
24
Figure 25. Watchdog Time-out
1 CK Cycle
ATtiny26(L)
1477B–AVR–04/02
System Clock and Clock Options
ATtiny26(L)
Clock Systems and their Distribution
Figure 26 presents the principal clock systems in the AVR and their distribution. All of
the clocks need not be active at a given time. In order to reduce power consumption, the
clocks to modules not being used can be halted by using different sleep modes, as
described in “Power Management and Sleep Modes” on page 41. The clock systems
are detailed below.
Figure 26. Clock Distribution
Timer/Counter1
General I/O
modules
clk
I/O
ADC CPU Core RAM
clk
ADC
AVR Clock
Control Unit
Clock
Multiplexer
Source clock
clk
CPU
clk
FLASH
Reset Logic
Watchdog Timer
Watchdog clock
Watchdog
Oscillator
Flash and
EEPROM
CPU Clock – clk
I/O Clock – clk
I/O
Flash Clock – clk
ADC Clock – clk
CPU
FLASH
ADC
clk
clk
PCK
PLL
PLL
External RC
Oscillator
External clock
Crystal
Oscillator
Low-Frequency
Crystal Oscillator
Calibrated RC
Oscillator
The CPU clock is routed to parts of the system concerned with operation of the AVR
core. Examples of such modules are the General Purpose Register File, the Status Register and the data memory holding the Stack Pointer. Halting the CPU clock inhibits the
core from performing general operations and calculations.
The I/O clock is used by the majority of the I/O modules, like Timer/Counters, and USI.
The I/O clock is also used by the External Interrupt module, but note that some external
interrupts are detected by asynchronous logic, allowing such interrupts to be detected
even if the I/O clock is halted.
The Flash clock controls operation of the Flash interface. The Flash clock is usually
active simultaneously with the CPU clock.
The ADC is provided with a dedicated clock domain. This allows halting the CPU and
I/O clocks in order to reduce noise generated by digital circuitry. This gives more accurate ADC conversion results.
1477B–AVR–04/02
25
Internal PLL for Fast
Peripheral Clock Generation –
clk
PCK
The internal PLL in ATtiny26/L generates a clock frequency that is 64x multiplied from
nominally 1 MHz input. The source of the 1 MHz PLL input clock is the output of the
internal RC Oscillator which is automatically divided down to 1 MHz, if needed. See the
Figure 27 on page 26. When the PLL reference frequency is the nominal 1 MHz, the fast
peripheral clock is 64 MHz. The fast peripheral clock, or a clock prescaled from that, can
be selected as the clock source for Timer/Counter1.
The PLL is locked on the RC Oscillator and adjusting the RC Oscillator via OSCCAL
Register will adjust the fast peripheral clock at the same time. However, even if the possibly divided RC Oscillator is taken to a higher frequency than 1 MHz, the fast peripheral
clock frequency saturates at 70 MHz (worst case) and remains oscillating at the maximum frequency. It should be noted that the PLL in this case is not locked any more with
the RC Oscillator clock.
Therefore it is recommended not to take the OSCCAL adjustments to a higher frequency than 1 MHz in order to keep the PLL in the correct operating range. The internal
PLL is enabled only when the PLLE bit in the register PLLCSR is set or the PLLCK Fuse
is programmed (“0”). The bit PLOCK from the register PLLCSR is set when PLL is
locked.
Both internal 1 MHz RC Oscillator and PLL are switched off in Power-down and Standby
sleep modes.
Figure 27. PCK Clocking System
PLLE
RC OSCILLATOR
XTAL1
XTAL2
OSCCAL
1
2
4
8 MHz
OSCILLATORS
PLLCK &
CKSEL
FUSES
DIVIDE
TO 1 MHz
PLL
64x
Lock
Detector
PLOCK
PCK
DIVIDE
BY 4
CK
26
ATtiny26(L)
1477B–AVR–04/02
ATtiny26(L)
Clock Sources The device has the following clock source options, selectable by Flash Fuse bits as
shown below on Table 4. The clock from the selected source is input to the AVR clock
generator, and routed to the appropriate modules.The use of pins PB5 (XTAL2), and
PB4 (XTAL1) as I/O pins is limited depending on clock settings, as shown below in
Table 5.
Table 4. Device Clocking Options Select
Device Clocking Option PLLCK CKSEL3..0
External Crystal/Ceramic Resonator 1 1111 - 1010
External Low-frequency Crystal 1 1001
External RC Oscillator 1 1000 - 0101
Calibrated Internal RC Oscillator 1 0100 - 0001
External Clock 1 0000
PLL Clock 0 0001
Table 5. PB5, and PB4 Functionality vs. Device Clocking Options
Device Clocking Option PLLCK CKSEL [3:0] PB4 PB5
External Clock 1 0000 XTAL1 I/O
Internal RC Oscillator 1 0001 I/O I/O
Internal RC Oscillator 1 0010 I/O I/O
Internal RC Oscillator 1 0011 I/O I/O
Internal RC Oscillator 1 0100 I/O I/O
External RC Oscillator 1 0101 XTAL1 I/O
External RC Oscillator 1 0110 XTAL1 I/O
External RC Oscillator 1 0111 XTAL1 I/O
External RC Oscillator 1 1000 XTAL1 I/O
External Low-frequency Oscillator 1 1001 XTAL1 XTAL2
External Crystal/Resonator Oscillator 1 1010 XTAL1 XTAL2
External Crystal/Resonator Oscillator 1 1011 XTAL1 XTAL2
External Crystal/Resonator Oscillator 1 1100 XTAL1 XTAL2
External Crystal/Resonator Oscillator 1 1101 XTAL1 XTAL2
External Crystal/Resonator Oscillator 1 1110 XTAL1 XTAL2
(1)
1477B–AVR–04/02
External Crystal/Resonator Oscillator 1 1111 XTAL1 XTAL2
PLL 0 0001 I/O I/O
Note: 1. For all fuses “1” means unprogrammed while “0” means programmed.
The various choices for each clocking option is given in the following sections. When the
CPU wakes up from Power-down, the selected clock source is used to time the start-up,
ensuring stable oscillator operation before instruction execution starts. When the CPU
starts from Reset, there is as an additional delay allowing the power to reach a stable
level before commencing normal operation. The Watchdog Oscillator is used for timing
this real-time part of the start-up time. The number of WDT Oscillator cycles used for
27
each time-out is shown in Table 6. The frequency of the Watchdog Oscillator is voltage
dependent as shown in the Electrical Characteristics section. The device is shipped with
PLLCK = “1”, CKSEL = “0001”, and SUT = “10” (1 MHz Internal RC Oscillator, slowly rising power).
Table 6. Number of Watchdog Oscillator Cycles
Typ Time-out (VCC = 5.0V) Typ Time-out (VCC = 3.0V) Number of Cycles
4.1 ms 4.3 ms 4K (4,096)
65 ms 69 ms 64K (65,536)
Crystal Oscillator XTAL1 and XTAL2 are input and output, respectively, of an inverting amplifier which can
be configured for use as an On-chip Oscillator, as shown in Figure 28. Either a quartz
crystal or a ceramic resonator may be used. The maximum frequency for resonators is
12 MHz. The CKOPT Fuse should always be unprogrammed when using this clock
option. C1 and C2 should always be equal. The optimal value of the capacitors depends
on the crystal or resonator in use, the amount of stray capacitance, and the electromagnetic noise of the environment. Some initial guidelines for choosing capacitors for use
with crystals are given in Table 7. For ceramic resonators, the capacitor values given by
the manufacturer should be used.
Figure 28. Crystal Oscillator Connections
C2
C1
XTAL2
XTAL1
GND
The Oscillator can operate in three different modes, each optimized for a specific frequency range. The operating mode is selected by the fuses CKSEL3..1 as shown in
Table 7.
Table 7. Crystal Oscillator Operating Modes
Frequency
CKSEL3..1
(2)
101
110 0.9 - 3.0 12 - 22
111
Notes: 1. The frequency ranges are preliminary values. Actual values are TBD.
2. This option should not be used with crystals, only with ceramic resonators.
(1)
Range
(MHz)
0.4 - 0.9 –
3.0 - 16 12 - 22
16 - 12 - 15
Recommended Range for Capacitors C1 and
C2 for Use with Crystals (pF)
28
ATtiny26(L)
1477B–AVR–04/02
ATtiny26(L)
The CKSEL0 Fuse together with the SUT1..0 Fuses select the start-up times as shown
in Table 8.
Table 8. Start-up Times for the Crystal Oscillator Clock Selection
Start-up Time
CKSEL0 SUT1..0
0 00 258 CK
0 01 258 CK
010 1K CK
011 1K CK
100 1K CK
1 01 16K CK – Crystal Oscillator,
1 10 16K CK 4.1 ms Crystal Oscillator, fast
1 11 16K CK 65 ms Crystal Oscillator,
Notes: 1. These options should only be used when not operating close to the maximum fre-
quency of the device, and only if frequency stability at start-up is not important for the
application.
2. These options are intended for use with ceramic resonators and will ensure frequency stability at start-up. They can also be used with crystals when not operating
close to the maximum frequency of the device, and if frequency stability at start-up is
not important for the application.
from Power-down
(1)
(1)
(2)
(2)
(2)
Additional Delay from
Reset (VCC = 5.0V)
4.1 ms Ceramic resonator,
65 ms Ceramic resonator,
– Ceramic resonator,
4.1 ms Ceramic resonator,
65 ms Ceramic resonator,
Recommended
Usage
fast rising power
slowly rising power
BOD enabled
fast rising power
slowly rising power
BOD enabled
rising power
slowly rising power
Low-frequency Crystal Oscillator
1477B–AVR–04/02
To use a 32.768 kHz watch crystal as the clock source for the device, the Low-frequency Crystal Oscillator must be selected by setting the PLLCK to “1” and CKSEL
Fuses to “1001”. The crystal should be connected as shown in Figure 28. By programming the CKOPT Fuse, the user can enable internal capacitors on XTAL1 and XTAL2,
thereby removing the need for external capacitors. The internal capacitors have a nominal value of 36 pF.
When this oscillator is selected, start-up times are determined by the SUT Fuses as
shown in Table 9.
Table 9. Start-up Times for the Low-frequency Crystal Oscillator Clock Selection
Start-up Time
SUT1..0
00 1K CK
01 1K CK
10 32K CK 65 ms Stable frequency at start-up
11 Reserved
Note: 1. These options should only be used if frequency stability at start-up is not important for
from Power-down
(1)
(1)
the application.
Additional Delay from
Reset (VCC = 5.0V) Recommended Usage
4.1 ms Fast rising power or BOD enabled
65 ms Slowly rising power
29
External RC Oscillator For timing insensitive applications, the external RC configuration shown in Figure 29
can be used. The frequency is roughly estimated by the equation f = 1/(3RC). C should
be at least 22 pF. By programming the CKOPT Fuse, the user can enable an internal
36 pF capacitor between XTAL1 and GND, thereby removing the need for an external
capacitor.
Figure 29. External RC Configuration
V
CC
PB5 (XTAL2)
R
XTAL1
C
GND
The oscillator can operate in four different modes, each optimized for a specific frequency range. The operating mode is selected by the fuses CKSEL3..0 as shown in
Table 10.
Table 10. External RC Oscillator Operating Modes
CKSEL3..0 Frequency Range (MHz)
0101 - 0.9
0110 0.9 - 3.0
0111 3.0 - 8.0
1000 8.0 - 12.0
When this oscillator is selected, start-up times are determined by the SUT Fuses as
shown in Table 11.
Table 11. Start-up Times for the External RC Oscillator Clock Selection
30
ATtiny26(L)
Start-up Time
SUT1..0
00 18 CK – BOD enabled
01 18 CK 4.1 ms Fast rising power
10 18 CK 65 ms Slowly rising power
11 6 CK
Notes: 1. This option should not be used when operating close to the maximum frequency of
from Power-down
(1)
the device.
Additional Delay from
Reset (VCC = 5.0V) Recommended Usage
4.1 ms Fast rising power or BOD enabled
1477B–AVR–04/02
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