Rainbow Electronics ATR0630P1 User Manual
Features
• 16-channel GPS Correlator
– 8192 Search Bins with GPS Acquisition Accelerator
– Accuracy: 2.5m CEP (2D, Stand Alone)
– Time to First Fix: 34s (Cold Start)
– Acquisition Sensitivity: –140 dBm (With External LNA)
– Tracking Sensitivity: –150 dBm (With External LNA)
• Utilizes the ARM7TDMI
– High-performance 32-bit RISC Architecture
– EmbeddedICE
• 128 Kbytes Internal RAM
• 384 Kbytes Internal ROM with u-blox GPS Firmware
• 1.5-bit ADC On-chip
• Single IF Architecture
• 2 External Interrupts
• 24 User-programmable I/O Lines
• 1 USB Device Port
– Universal Serial Bus (USB) 2.0 Full-speed Device
– Embedded USB V2.0 Full-speed Transceiver
• 2 USARTs
• Master/Slave SPI Interface
– 4 External Slave Chip Selects
• Programmable Watchdog Timer
• Advanced Power Management Controller (APMC)
– Geared Master Clock to Reduce Power Consumption
– Sleep State with Disabled Master Clock
– Hibernate State with 32.768 kHz Master Clock
• Real Time Clock (RTC)
• 1.8V to 3.3V User-definable IO Voltage for Several GPIOs with 5V Tolerance
• 4 KBytes of Battery Backup Memory
• 7 mm × 10 mm 96 Pin BGA Package, 0.8 mm Pitch, Pb-free, RoHS-compliant
®
ARM® Thumb® Processor Core
™
(In-Circuit Emulation)
ANTARIS4
Single-chip GPS
Receiver
ATR0630P1
Automotive
Summary
Benefits
• Fully Integrated Design With Low BOM
• No External Flash Memory Required
• Requires Only a GPS XTAL, No TCXO
• Supports NMEA
• Supports SBAS (WAAS, EGNOS, MSAS)
• Up to 4Hz Update Rate
• Supports A-GPS (Aiding)
• Excellent Noise Performance
®
, UBX Binary and RTCM Protocol for DGPS
NOTE: This is a summary document.
The complete document is available.
For more information, please contact
your local Atmel sales office.
4978AS–GPS–12/07
1. Description
The ATR0630P1 is a low-power, single-chip GPS receiver, especially designed to meet the
requirements of mobile applications. It is based on Atmel
grates an RF front-end, filtering, and a baseband processor in a single, tiny 7 mm × 10 mm
96 pin BGA package. Providing excellent RF performance with low noise figure and low power
consumption.
Due to the fully integrated design, just an RF SAW filter, a GPS XTAL (no TCXO) and blocking
capacitors are required to realize a stand-alone GPS functionality.
The ATR0630P1 includes a complete GPS firmware, licensed from u-blox AG, which performs
the GPS operation, including tracking, acquisition, navigation and position data output. For normal PVT (Position/Velocity/Time) applications, there is no need for external Flash- or
ROM-memory.
The firmware supports e.g. the NMEA protocol (2.1 and 2.3), a binary protocol for PVT data,
configuration and debugging, the RTCM protocol for DGPS, SBAS (WAAS, EGNOS and MSAS)
and A-GPS (aiding). It is also possible to store the configuration settings in an optional external
EEPROM.
Due to the integrated ARM7TDMI processor and an intelligent radio architecture, the
ATR0630P1 operates in a complete autonomous mode, utilizing on chip AGC in closed loop
operation.
For maximum performance, we recommend to use the ATR0630P1 together with a low noise
amplifier (e.g. ATR0610).
®
’s ANTARIS®4 technology and inte-
The ATR0630P1 supports assisted GPS.
2
ATR0630P1
4978AS–GPS–12/07
2. Architectural Overview
2.1 Block Diagram
Figure 2-1. ATR0630P1 Block Diagram
PUXTO
PURF
VDD18
VDDIO
VDD_USB
VDIG
VCC1
VCC2
VBP
TEST
Power Supply Manager/
PMSS/Logic
ATR0630P1
VBAT18
VBAT
LDOBAT_IN
LDO_OUT
LDO_IN
LDO_EN
AGCO
EGC
SDI
NRF
XTO
NXTO
RF_ON
NSHDN
NSLEEP
XT_IN
XT_OUT
P20/TIMEPULSE
P29/GPSMODE12
P27/GPSMODE11
P26/GPSMODE10
P24/GPSMODE8
P23/GPSMODE7
P19/GPSMODE6
P17/GPSMODE5
P13/GPSMODE3
P12/GPSMODE2
P1/GPSMODE0
P14/NAADET1
P25/NAADET0
P15/ANTON
P0/NANTSHORT
P9/EXTINT0
P16/NEEPROM
MO
RF
VCO
PLL
PIO2
XTO
Power
Manage-
Advanced
RTC
SMD
PIO2
Special
Interrupt
Advanced
Watchdog
ment
Controller
SRAM
Generator
Controller
Function
Controller
B
RID
E
G
X
NX
A
A
GPS
GPS
Timer
D
D
Accelerator
Correlators
Counter
SPIUSB
USART1 USART2
1
SIGHI
SIGLO
CLK23
P21/TXD2
PIO2
USB
Transceiver
P22/RXD2
P18/TXD1
P31/RXD1
USB_DP
USB_DM
4978AS–GPS–12/07
P8/STATUSLED
P30/AGCOUT0
P2/BOOT_MODE
DBG_EN
NTRST
TDO
TCK
TMS
ROM
SRAM
Reset
PDC2
384K
128K
NRESET
Controller
(EBI)
Memory
Off-Chip
Interface to
ASB APB
ICE
Embedded
ARM7TDMI
TDI
JTAG
3
2.2 General Description
The ATR0630P1 has been designed especially for mobile applications. It provides high isolation
between GPS and cellular bands, as well as very low power consumption.
ATR0630P1 is based on the successful ANTARIS4 technology which includes the ANTARIS
ROM software, developed by u-blox AG, Switzerland. ANTARIS provides a proven navigation
engine which is used in high-end car navigation systems, automatic vehicle location (AVL),
security and surveying systems, traffic control, road pricing, and speed camera detectors, and
provides location-based services (LBS) worldwide.
The ANTARIS4 chipset has a very low power consumption and comes with a very low BoM for
the passive components. Especially, due to its fast search engine and GPS accelerator, the
ATR0630P1 only needs a GPS crystal (XTAL) as a resonator for the integrated crystal oscillator
of the ATR0630P1. This saves the considerable higher cost of a TCXO which is required for
competitor’s systems. Also, as the powerful standard software is available in ROM, no external
flash memory is needed.
2.3 PMSS Logic
2.4 XTO
2.5 VCO/PLL
The L1 input signal (f
quency of 1575.42 MHz. The digital modulation scheme is Bi-Phase-Shift-Keying (BPSK) with a
chip rate of 1.023 Mbps.
The power management, startup and shutdown (PMSS) logic ensures reliable operation within
the recommended operating conditions. The external power control signals PUrf and PUxto are
passed through Schmitt trigger inputs to eliminate voltage ripple and prevent undesired behavior
during start-up and shut-down. Digital and analog supply voltages are analyzed by a monitoring
circuit, enabling the startup of the IC only when it is within a safe operating range.
The XTO is designed for minimum phase noise and frequency perturbations. The balanced
topology gives maximum isolation from external and ground coupled noise. The built-in jump
start circuitry ensures reliable start-up behavior of any specified crystal. For use with an external
TCXO, the XTO circuitry can be used as a single-ended or balanced input buffer.
The recommended reference frequency is: f
The frequency synthesizer features a balanced VCO and a fully integrated loop filter, thus no
external components are required. The VCO combines very good phase noise behavior and
excellent spurious suppression. The relation between the reference frequency (f
VCO center frequency (f
) is a Direct Sequence Spread Spectrum (DSSS) signal with a center fre-
RF
= 23.104 MHz.
XTO
) and the
XTO
) is given by: f
VCO
VCO=fXTO
× 64 = 23.104 MHz × 64 = 1478.656 MHz.
2.6 RF Mixer/Image Filter
Combined with the antenna, an external LNA provides a first band-path filtering of the signal.
Atmel’s ATR0610 is recommended for the LNA due to its low noise figure, high linearity and low
power consumption. The output of the LNA drives a SAW filter, which provides image rejection
for the mixer and the required isolation to all GSM bands. The output of the SAW filter is fed into
a highly linear mixer with high conversion gain and excellent noise performance.
4
ATR0630P1
4978AS–GPS–12/07
2.7 VGA/AGC
The on-chip automatic gain control (AGC) stage sets the gain of the VGA in order to optimally
load the input of the following analog-to-digital converter. The AGC control loop can be selected
for on-chip closed-loop operation or for baseband controlled gain mode.
2.8 Analog-to-digital Converter
The analog-to-digital converter stage has a total resolution of 1.5 bits. It comprises balanced
comparators and a sub-sampling unit, clocked by the reference frequency (f
spectrum of the digital output signal (f
4.348 MHz.
2.9 Baseband
The GPS baseband core includes a 16-channel correlator and is based on an ARM7TDMI ARM
processor core with very low power consumption. It has a high-performance 32 bit RISC architecture, uses a high-density 16-bit instruction set, The ARM standard In-Circuit Emulation debug
interface is supported via the JTAG/ICE port of the ATR0630P1.
The ATR0630P1 architecture consists of two main buses, the Advanced System Bus (ASB) and
the Advanced Peripheral Bus (APB). The ASB is designed for maximum performance. It interfaces the processor with the on-chip 32-bit memories and the external memories and devices by
means of the External Bus Interface (EBI). The APB is designed for accesses to on-chip peripherals and is optimized for low power consumption. The AMBA
between the ASB and the APB.
ATR0630P1
). The frequency
XTO
), present at the data outputs SIGLO and SIGH1, is
OUT
™
Bridge provides an interface
An on-chip Peripheral Data Controller (PDC2) transfers data between the on-chip USARTs/SPI
and the on- and off-chip memories without processor intervention. Most importantly, the PDC2
removes the processor interrupt handling overhead and significantly reduces the number of
clock cycles required for a data transfer. It can transfer up to 64K contiguous bytes without
reprogramming the starting address. As a result, the performance of the microcontroller is
increased and the power consumption reduced.
All of the external signals of the on-chip peripherals are under the control of the Parallel I/O Controller (PIO2). The PIO2 Controller can be programmed to insert an input filter on each pin or
generate an interrupt on a signal change. After reset, the user must carefully program the PIO2
Controller in order to define which peripheral signals are connected with off-chip logic.
The ATR0630P1 features a Programmable Watchdog Timer.
An Advanced Power Management Controller (APMC) allows for the peripherals to be deactivated individually. Automatic master clock gearing reduces power consumption. A Sleep Mode
is available with disabled 23.104 MHz master clock, as well as a Back-up Mode operating
32.768 kHz master clock.
A 32.768 kHz Real Time Clock (RTC), together with a buit-in battery back-up SRAM, allows for
storage of Almanac, Ephemeris, software configurations to make quick hot- and warm starts.
The ATR0630P1 includes full GPS firmware, licensed from u-blox AG, Switzerland. Features of
the ROM firmware are described in software documentation available from u-blox AG,
Switzerland.
4978AS–GPS–12/07
5
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