Rainbow Electronics ATR0630 User Manual

Page 1

Features

•

16-channel GPS Correlator

– 8192 Search Bins with GPS Acquisition Accelerator – Accuracy: 2.5m CEP (2D, Stand Alone) – Time to First Fix: 34s (Cold Start) – Acquisition Sensitivity: –139 dBm (With External LNA) – Tracking Sensitivity: –149 dBm (With External LNA)

•

Utilizes the ARM7TDMI® ARM® Thumb® Processor Core

– High-performance 32-bit RISC Architecture – Embedded ICE (In-Circuit Emulation)

•

128 Kbytes Internal RAM

•

384 Kbytes Internal ROM with u-blox GPS Firmware

•

1.5-bit ADC On-chip

•

Single IF Architecture

•

2 External Interrupts

•

24 User-programmable I/O Lines

•

1 USB Device Port

– Universal Serial Bus (USB) 2.0 Full-speed Device – Embedded USB V2.0 Full-speed Transceiver

•

2 USARTs

•

Master/Slave SPI Interface

– 4 External Slave Chip Selects

•

Programmable Watchdog Timer

•

Advanced Power Management Controller (APMC)

– Geared Master Clock to Reduce Power Consumption – Sleep State with Disabled Master Clock – Hibernate State with 32.768 kHz Master Clock

•

Real Time Clock (RTC)

•

1.8V to 3.3V User-definable IO Voltage for Several GPIOs with 5V Tolerance

•

4 KBytes of Battery Backup Memory

•

7 mm × 10 mm 96 Pin BGA Package, 0.8 mm Pitch, Pb-free, RoHS-compliant

ANTARIS4 Single-chip GPS Receiver

ATR0630

Preliminary

Benefits

•

Fully Integrated Design With Low BOM

•

No External Flash Memory Required

•

Requires Only a GPS XTAL, No TCXO

•

Supports NMEA, UBX Binary and RTCM Protocol

•

Supports SBAS (WAAS, EGNOS, MSAS)

•

Up to 4Hz Update Rate

•

Supports A-GPS (Aiding)

•

Excellent Noise Performance

Rev. 4920A–GPS–01/06

Page 2

1. Description

The ATR0630 is a low-power, single-chip GPS receiver, especially designed to meet the requirements of mobile applications. It is based on Atmel’s ANTARIS grates an RF front-end, filtering, and a baseband processor in a single, tiny 7 mm × 10 mm 96 pin BGA package. Providing excellent RF performance with low noise figure and low power consumption.

Due to the fully integrated design, just an RF SAW filter, a GPS XTAL (no TCXO) and blocking capacitors are required to realize a stand-alone GPS functionality.

The ATR0630 includes a complete GPS firmware, licensed from u-blox AG, which performs the GPS operation, including tracking, acquisition, navigation and position data output. For normal PVT (Position/Velocity/Time) applications, there is no need for external Flash- or ROM-memory. The firmware supports the possibility to store the configuration settings in an optional external EEPROM.

Due to the integrated ARM7TDMI processor and an intelligent radio architecture, the ATR0630 operates in a complete autonomous mode, utilizing on chip AGC in closed loop operation.

For maximum performance, we recommend to use the ATR0630 together with a low noise amplifier (e.g. ATR0610).

The ATR0630 supports assisted GPS.

™

4 technology and inte-

ATR0630 [Preliminary]

4920A–GPS–01/06

Page 3

2. Architectural Overview

2.1 Block Diagram

Figure 2-1. ATR0630 Block Diagram

PUXTO

PURF VDD18 VDDIO

VDD_USB

VDIG VCC1 VCC2

VBP

TEST

Power Supply Manager/

PMSS/Logic

ATR0630 [Preliminary]

VBAT18 VBAT LDOBAT_IN

LDO_OUT LDO_IN LDO_EN

AGCO EGC

SDI

NRF

XTO

NXTO

RF_ON

NSHDN

NSLEEP

XT_IN

XT_OUT

P20/TIMEPULSE

P29/GPSMODE12 P27/GPSMODE11

P26/GPSMODE10

P24/GPSMODE8 P23/GPSMODE7 P19/GPSMODE6 P17/GPSMODE5 P13/GPSMODE3 P12/GPSMODE2

P1/GPSMODE0

P14/NAADET1 P25/NAADET0

P15/ANTON

P0/NANTSHORT

P9/EXTINT0

P16/NEEPROM

VCO

PLL

PIO2

XTO

Power

Manage-

Advanced

RTC

SMD

PIO2

Special

Interrupt

Advanced

Watchdog

ment

Controller

SRAM

Generator

Controller

Function

Controller

RID

GPS

Timer

Accelerator

Correlators

Counter

SPIUSB

USART1 USART2

SIGHI

SIGLO

CLK23

P21/TXD2

PIO2

USB

Transceiver

P22/RXD2

P18/TXD1 P31/RXD1

USB_DP USB_DM

4920A–GPS–01/06

P8/STATUSLED

P30/AGCOUT0

P2/BOOT_MODE

DBG_EN

NTRST

TDO TCK TMS

ROM

SRAM

Reset

PDC2

384K

128K

NRESET

Controller

(EBI)

Memory

Off-Chip

Interface to

ASB APB

ICE

Embedded

ARM7TDMI

TDI

JTAG

Page 4

2.2 General Description

The ATR0630 has been designed especially for mobile applications. It provides high isolation between GPS and cellular bands, as well as very low power consumption.

ATR0630 is based on the successful ANTARIS4 technology which includes the ANTARIS ROM software, developed by u-blox AG, Switzerland. ANTARIS provides a proven navigation engine which is used in high-end car navigation systems, automatic vehicle location (AVL), security and surveying systems, traffic control, road pricing, and speed camera detectors, and provides location-based services (LBS) worldwide.

The ANTARIS4 chipset has a very low power consumption and comes with a very low BoM for the passive components. Especially, due to its fast search engine and GPS accelerator, the ATR0630 only needs a GPS crystal (XTAL) as a resonator for the integrated crystal oscillator of the ATR0630. This saves the considerable higher cost of a TCXO which is required for competitor’s systems. Also, as the powerful standard software is available in ROM, no external flash memory is needed.

2.3 PMSS Logic

2.4 XTO

2.5 VCO/PLL

The L input signal (f

) is a Direct Sequence Spread Spectrum (DSSS) signal with a center fre-

quency of 1575.42 MHz. The digital modulation scheme is Bi-Phase-Shift-Keying (BPSK) with a chip rate of 1.023 Mbps.

The power management, startup and shutdown (PMSS) logic ensures reliable operation within the recommended operating conditions. The external power control signals PUrf and PUxto are passed through Schmitt trigger inputs to eliminate voltage ripple and prevent undesired behavior during start-up and shut-down. Digital and analog supply voltages are analyzed by a monitoring circuit, enabling the startup of the IC only when it is within a safe operating range.

The XTO is designed for minimum phase noise and frequency perturbations. The balanced topology gives maximum isolation from external and ground coupled noise. The built-in jump start circuitry ensures reliable start-up behavior of any specified crystal. For use with an external TCXO, the XTO circuitry can be used as a single-ended or balanced input buffer.

The recommended reference frequency is: f

= 23.104 MHz.

XTO

The frequency synthesizer features a balanced VCO and a fully integrated loop filter, thus no external components are required. The VCO combines very good phase noise behavior and excellent spurious suppression. The relation between the reference frequency (f VCO center frequency (f

) is given by: f

VCO

= f

× 64 = 23.104 MHz × 64 = 1478.656 MHz.

XTO

) and the

XTO

2.6 RF Mixer/Image Filter

Combined with the antenna, an external LNA provides a first band-path filtering of the signal. Atmel’s ATR0610 is recommended for the LNA due to its low noise figure, high linearity and low power consumption. The output of the LNA drives a SAW filter, which provides image rejection for the mixer and the required isolation to all GSM bands. The output of the SAW filter is fed into a highly linear mixer with high conversion gain and excellent noise performance.

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4920A–GPS–01/06

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2.7 VGA/AGC

The on-chip automatic gain control (AGC) stage sets the gain of the VGA in order to optimally load the input of the following analog-to-digital converter. The AGC control loop can be selected for on-chip closed-loop operation or for baseband controlled gain mode.

2.8 Analog-to-digital Converter

The analog-to-digital converter stage has a total resolution of 1.5 bits. It comprises balanced comparators and a sub-sampling unit, clocked by the reference frequency (f spectrum of the digital output signal (f

4.348 MHz.

2.9 Baseband

The GPS baseband core includes a 16-channel correlator and is based on an ARM7TDMI ARM processor core with very low power consumption. It has a high-performance 32 bit RISC architecture, uses a high-density 16-bit instruction set, The ARM standard In-Circuit Emulation debug interface is supported via the JTAG/ICE port of the ATR0630.

The ATR0630 architecture consists of two main buses, the Advanced System Bus (ASB) and the Advanced Peripheral Bus (APB). The ASB is designed for maximum performance. It interfaces the processor with the on-chip 32-bit memories and the external memories and devices by means of the External Bus Interface (EBI). The APB is designed for accesses to on-chip peripherals and is optimized for low power consumption. The AMBA Bridge provides an interface between the ASB and the APB.

ATR0630 [Preliminary]

). The frequency

XTO

), present at the data outputs SIGLO and SIGH1, is

OUT

An on-chip Peripheral Data Controller (PDC2) transfers data between the on-chip USARTs/SPI and the on- and off-chip memories without processor intervention. Most importantly, the PDC2 removes the processor interrupt handling overhead and significantly reduces the number of clock cycles required for a data transfer. It can transfer up to 64K contiguous bytes without reprogramming the starting address. As a result, the performance of the microcontroller is increased and the power consumption reduced.

All of the external signals of the on-chip peripherals are under the control of the Parallel I/O Controller (PIO2). The PIO2 Controller can be programmed to insert an input filter on each pin or generate an interrupt on a signal change. After reset, the user must carefully program the PIO2 Controller in order to define which peripheral signals are connected with off-chip logic.

The ATR0630 features a Programmable Watchdog Timer.

An Advanced Power Management Controller (APMC) allows for the peripherals to be deactivated individually. Automatic master clock gearing reduces power consumption. A Sleep Mode is available with disabled 23.104 MHz master clock, as well as a Back-up Mode operating

32.768 kHz master clock.

A 32.768 kHz Real Time Clock (RTC), together with a buit-in battery back-up SRAM, allows for storage of Almanac, Ephemeris, software configurations to make quick hot- and warm starts.

The ATR0630 includes full GPS firmware, licensed from u-blox AG, Switzerland. Features of the ROM firmware are described in software documentation available from u-blox AG, Switzerland.

4920A–GPS–01/06

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3. Pin Configuration

3.1 Pinout

Figure 3-1. Pinning BGA96 (Top View)

123456789101112

ATR0630

Table 3-1. ATR0630 Pinout

Pull Resistor

Pin Name BGA 96 Pin Type

AGCO A4 Analog I/O CLK23 A8 Digital IN

DBG_EN E8 Digital IN PD

EGC D4 Digital IN

GDIG C5 Supply

GND A6 Supply GND A9 Supply GND B11 Supply GND F5 Supply GND H8 Supply

GND H12 Supply GNDA A3 Supply GNDA B1 Supply

Notes: 1. PD = internal pull-down resistor, PU = internal pull-up resistor, OH = switched to Output High at reset

2. VBAT18 represent the internal power supply of the backup power domain, see section “Power Supply” on page 20.

3. VDD_USB is the supply voltage for following the USB pins: USB_DM and USB_DP, see section “Power Supply” on page

20. For operation of the USB interface, supply of 3.0V to 3.6V is required.

4. VDDIO is the supply voltage for the following GPIO pins: P1, P2, P8, P12, P14, P16, P17, P18, P19, P20, P21, P23, P24, P25, P26, P27 and P29, see section “Power Supply” on page 20.

(Reset Value)

(1)

Firmware Label

PIO Bank A

ATR0630 [Preliminary]

4920A–GPS–01/06

Page 7

ATR0630 [Preliminary]

Table 3-1. ATR0630 Pinout (Continued)

Pull Resistor

Pin Name BGA 96 Pin Type

GNDA B4 Supply GNDA D2 Supply GNDA E1 Supply GNDA E2 Supply GNDA E3 Supply GNDA F1 Supply GNDA F2 Supply GNDA F3 Supply GNDA G1 Supply GNDA H1 Supply

LDOBAT_IN D11 Supply

LDO_EN C11 Digital IN

LDO_IN E11 Supply

LDO_OUT E12 Supply

MO C3 Analog OUT

NRESET A7 Digital I/O Open Drain PU

NRF C1 Analog IN

NSHDN E9 Digital OUT

NSLEEP E10 Digital OUT

NTRST H11 Digital IN PD

NX B2 Analog OUT

NXTO B3 Analog IN

P0 C8 Digital I/O PD NANTSHORT P1 D8 Digital I/O Configurable (PD) GPSMODE0 P2 C6 Digital I/O Configurable (PD) BOOT_MODE ‘0’ P8 D7 Digital I/O Configurable (PD) STATUSLED ‘0’

P9 A11 Digital I/O PU EXTINT0 EXTINT0 P12 D6 Digital I/O Configurable (PU) GPSMODE2 NPCS2 P13 B10 Digital I/O PU GPSMODE3 EXTINT1 P14 G6 Digital I/O Configurable (PD) NAADET1 ‘0’ P15 F11 Digital I/O PD ANTON P16 G8 Digital I/O Configurable (PU) NEEPROM P17 H6 Digital I/O Configurable (PD) GPSMODE5 SCK1 SCK1 P18 C7 Digital I/O Configurable (PU) TXD1 TXD1 P19 F6 Digital I/O Configurable (PU) GPSMODE6

Notes: 1. PD = internal pull-down resistor, PU = internal pull-up resistor, OH = switched to Output High at reset

2. VBAT18 represent the internal power supply of the backup power domain, see section “Power Supply” on page 20.

3. VDD_USB is the supply voltage for following the USB pins: USB_DM and USB_DP, see section “Power Supply” on page

20. For operation of the USB interface, supply of 3.0V to 3.6V is required.

4. VDDIO is the supply voltage for the following GPIO pins: P1, P2, P8, P12, P14, P16, P17, P18, P19, P20, P21, P23, P24, P25, P26, P27 and P29, see section “Power Supply” on page 20.

(Reset Value)

(1)

Firmware Label

PIO Bank A

4920A–GPS–01/06

Page 8

Table 3-1. ATR0630 Pinout (Continued)

Pull Resistor

Pin Name BGA 96 Pin Type

P20 G7 Digital I/O Configurable (PD) TIMEPULSE SCK2 SCK2 P21 E6 Digital I/O Configurable (PU) TXD2 TXD2 P22 D10 Digital I/O PU RXD2 RXD2 P23 F8 Digital I/O Configurable (PU) GPSMODE7 SCK SCK P24 H7 Digital I/O Configurable (PU) GPSMODE8 MOSI MOSI P25 G5 Digital I/O Configurable (PD) NAADET0 MISO MISO P26 B6 Digital I/O Configurable (PU) GPSMODE10 NSS NPCS0 P27 F7 Digital I/O Configurable (PU) GPSMODE11 NPCS1 P28 E7 Digital I/O OH P29 D5 Digital I/O Configurable (PU) GPSMODE12 NPCS3 P30 G12 Digital I/O PD AGCOUT0 AGCOUT0

P31 C10 Digital I/O PU RXD1 RXD1 PURF G4 Digital IN PURF H4 Digital IN

PUXTO F4 Digital IN

RF D1 Analog IN

RF_ON F10 Digital OUT PD

SDI C4 Digital IN

SIGHI0 B8 Digital OUT

SIGLO0 B7 Digital OUT

TCK G9 Digital IN PU

TDI H10 Digital IN PU

TDO F9 Digital OUT

TEST D3 Analog IN

TMS G10 Digital IN PU USB_DM D9 Digital I/O USB_DP C9 Digital I/O

VBAT D12 Supply

(2)

VBAT18

VBP G2 Supply

VBP G3 Supply

VBP H2 Supply

VBP H3 Supply

VCC1 C2 Supply VCC2 E4 Supply

Notes: 1. PD = internal pull-down resistor, PU = internal pull-up resistor, OH = switched to Output High at reset

C12 Supply

2. VBAT18 represent the internal power supply of the backup power domain, see section “Power Supply” on page 20.

3. VDD_USB is the supply voltage for following the USB pins: USB_DM and USB_DP, see section “Power Supply” on page

20. For operation of the USB interface, supply of 3.0V to 3.6V is required.

4. VDDIO is the supply voltage for the following GPIO pins: P1, P2, P8, P12, P14, P16, P17, P18, P19, P20, P21, P23, P24, P25, P26, P27 and P29, see section “Power Supply” on page 20.

(Reset Value)

(1)

Firmware Label

PIO Bank A

ATR0630 [Preliminary]

4920A–GPS–01/06

Page 9

ATR0630 [Preliminary]

Table 3-1. ATR0630 Pinout (Continued)

Pull Resistor

Pin Name BGA 96 Pin Type

VDD_USB

VDD18 H9 Supply VDD18 G11 Supply VDD18 F12 Supply VDD18 B9 Supply VDD18 E5 Supply

VDDIO

VDDIO H5 Supply

XT_IN A12 Analog IN

XT_OUT B12 Analog OUT

Notes: 1. PD = internal pull-down resistor, PU = internal pull-up resistor, OH = switched to Output High at reset

(3)

A10 Supply

(4)

VDIG A5 Supply

X A2 Analog OUT

XTO A1 Analog Input

2. VBAT18 represent the internal power supply of the backup power domain, see section “Power Supply” on page 20.

3. VDD_USB is the supply voltage for following the USB pins: USB_DM and USB_DP, see section “Power Supply” on page

4. VDDIO is the supply voltage for the following GPIO pins: P1, P2, P8, P12, P14, P16, P17, P18, P19, P20, P21, P23, P24,

B5 Supply

20. For operation of the USB interface, supply of 3.0V to 3.6V is required.

P25, P26, P27 and P29, see section “Power Supply” on page 20.

(Reset Value)

(1)

Firmware Label

PIO Bank A

3.2 Signal Description

Table 3-2. Signal Description

Pin Number Pin Name Type Active Level Pin Description/Comment

RF Section

D1 RF ANALOG IN - Input from SAW filter C1 NRF ANALOG IN - Inverted input from SAW filter

GPS XTAL Section

A1 XTO ANALOG IN - XTO input (23.104 MHz)/optional TCXO input B3 NXTO ANALOG IN - Inverted XTO input (23.104 MHz)/optional TCXO input A2 X ANALOG OUT - XTO interface (capacitor) B2 NX ANALOG OUT - Inverted XTO interface (capacitor)

RTC Section

A12 XT_IN ANALOG IN - Oscillator input (32.768 kHz) B12 XT_OUT ANALOG OUT - Oscillator output (32.768 kHz)

Automatic Gain Control, bandwidth setting

A4 AGCO ANALOG IO - Automatic gain control analog voltage, connect shunt capacitor to GND

D4 EGC DIGITAL IN -

G12 AGCOUT0 DIGITAL OUT - Software gain control, connect to SDI (C4)

C4 SDI DIGITAL IN - Software gain control, connect to AGCOUT0 (G12)

Enable external gain control (high = software gain control, low = automatic gain control)

4920A–GPS–01/06

Page 10

Table 3-2. Signal Description (Continued)

Pin Number Pin Name Type Active Level Pin Description/Comment

Boot Section

C6 BOOT_MODE DIGITAL IN - Leave open, internal pull down

Reset

A7 NRESET DIGITAL IN Low Reset input; open drain with internal pull-up resistor

APMC/Power Management

E9 NSHDN DIGITAL OUT Low Shutdown output, connect to LDO_EN (C11) C11 LDO_EN DIGITAL IN - Enable LDO18 E10 NSLEEP DIGITAL OUT Low Power-up output for GPS XTAL, connect to PUXTO (F4)

F4 PUXTO DIGITAL IN - Power-up input for GPS XTAL

G4, H4 PURF DIGITAL IN - Power-up input for GPS radio

F10 RF_ON DIGITAL OUT - Power-up output for GPS radio, connect to PURF (G4, H4)

Advanced Interrupt Controller (AIC)

A11, B10 EXTINT0-1 DIGITAL IN

USART

C10, D10 RXD1/RXD2 DIGITAL OUT - USART receive data output

C7, E6 TXD1/TXD2 DIGITAL IN - USART transmit data input H6, G7 SCK1/SCK2 DIGITAL I/O - External synchronous serial clock

USB

C9 USB_DP DIGITAL I/O - USB data (D+)

D9 USB_DM DIGITAL I/O - USB data (D-)

SPI Interface

F8 SCK DIGITAL I/O - SPI clock

H7 MOSI DIGITAL I/O - Master out slave in

G5 MISO DIGITAL I/O - Master in slave out

B6 NSS/NPCS0 DIGITAL I/O Low Slave select

F7, D6, D5

PIO

A11, B[6,10],

C[6-8,10], D[5-8,10],

E[6,7], F[6-

8], G[5-8],

H[6,7]

Configuration

B[6,10],

D[5,6,8], F[6-

8], H[6,7]

G8 NEEPROM DIGITAL IN Low Enable EEPROM support

GPS

D7 STATUSLED DIGITAL OUT - Status LED

G7 TIMEPULSE DIGITAL OUT - GPS synchronized time pulse

NPCS1/NPCS2

/NPCS3

P0 to P31 DIGITAL I/O - Programmable I/O ports

GPSMODE0-

DIGITAL OUT Low Slave select

DIGITAL IN - GPS mode pins

High/Low/

Edge

External interrupt request

ATR0630 [Preliminary]

4920A–GPS–01/06

Page 11

ATR0630 [Preliminary]

Table 3-2. Signal Description (Continued)

Pin Number Pin Name Type Active Level Pin Description/Comment

Active Antenna Supervision

C8 NANTSHORT DIGITAL IN Low Active antenna short detection Input

G5, G6

F11 ANTON DIGITAL OUT - Active antenna power-on Output

JTAG Interface

E8 DBG_EN DIGITAL IN - Debug enable

F9 TDO DIGITAL OUT - Test data out

G9 TCK DIGITAL IN - Test clock

G10 TMS DIGITAL IN - Test mode select

H10 TDI DIGITAL IN - Test data in H11 NTRST DIGITAL IN Low Test reset input

Debug/Test

C3 MO ANALOG OUT - IF output buffer

D3 TEST ANALOG IN - Enable IF output buffer

B7 SIGLO DIGITAL OUT - Digital IF (data output “Low”)

B8 SIGHI DIGITAL OUT - Digital IF (data output “High”)

A8 CLK23 DIGITAL OUT - Digital IF (sample clock)

Power Analog Part

C2 VCC1 SUPPLY - Analog supply 3V

E4 VCC2 SUPPLY - Analog supply 3V

G2, G3, H2,

A3, B1, B4,

D2, E[1-3], F[1-3], G1,

Power Digital Part

A5 VDIG SUPPLY - Digital supply (radio) 1.8V

B9, E5, F12,

G11,H9

A10 VDD_USB SUPPLY -

B5, H5 VDDIO SUPPLY - Variable I/O voltage 1.65V to 3.6V

C5 GDIG SUPPLY - Digital ground (radio)

A6, A9, B11,

F5, H8, H12

LDO18

E11 LDO_IN SUPPLY - 2.3V to 3.6V E12 LDO_OUT SUPPLY - 1.8V LDO18 output, max. 80 mA

LDOBAT

D11 LDOBAT_IN SUPPLY - 2.3V to 3.6V D12 VBAT SUPPLY - 1.5V to 3.6V C12 VBAT18 SUPPLY - 1.8V LDOBAT Output

NAADET0/NAA

DET1

VBP SUPPLY - Analog supply 3V

GNDA SUPPLY - Analog Ground

VDD18 SUPPLY - Core voltage 1.8V

GND SUPPLY - Digital ground

DIGITAL IN Low Active antenna detection Input

USB transceiver supply voltage (3.0V to 3.6V (USB enabled) or 0 to

2.0V (USB disabled))

4920A–GPS–01/06

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3.3 Setting GPSMODE0 to GPSMODE12

The start-up configuration of this ROM-based system without external non-volatile memory is defined by the status of the GPSMODE pins after system reset. Alternatively, the system can be configured through message commands passed through the serial interface after start-up. This configuration of the ATR0630 can be stored in an external non-volatile memory like EEPROM. Default designates settings used by ROM firmware if GPSMODE configuration is disabled (GPSMODE0 = 0).

Table 3-3. GPSMODE Functions

Pin Function

GPSMODE0 (P1) Enable configuration with GPSMODE pins

GPSMODE1 (P9)

GPSMODE2 (P12) GPSMODE3 (P13)

GPSMODE4 (P14)

GPSMODE5 (P17) GPSMODE6 (P19) GPSMODE7 (P23) USB power mode GPSMODE8 (P24) General I/O configuration

GPSMODE9 (P25)

GPSMODE10 (P26) GPSMODE11 (P27) GPSMODE12 (P29) Serial I/O configuration

This pin (EXTINT0) is used for FixNOW functionality and not used for GPSMODE configuration.

GPS sensitivity settings

This pin (NAADET1) is used as active antenna supervisor input and not used for GPSMODE configuration. This is the default selection if GPSMODE configuration is disabled.

Serial I/O configuration

This pin (NAADET0) is used as an active Antenna Supervisor input and not used for GPSMODE configuration

General I/O configuration

3.3.1 Enable GPSMODE Pin Configuration

Table 3-4. Enable Configuration With GPSMODE Pins

GPSMODE0

(Reset = PD) Description

0 Ignore all GPSMODE pins. The default settings as indicated below are used. 1 Use settings as specified with GPSMODE[2, 3, 5 to 8, 10 to 12]

If the GPSMODE configuration is enabled (GPSMODE0 = 1) and the other GPSMODE pins are not connected externally, the reset default values of the internal pull-down and pull-up resistors will be used.

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3.3.2 Sensitivity Settings

Table 3-5. GPS Sensitivity Settings

GPSMODE3

(Fixed PU)

0 0 Auto mode 0 1 Fast mode 1 0 Normal mode (Default ROM value) 1 1 High sensitivity

3.4 Serial I/O Configuration

The ATR0630 features a two-stage I/O-message and protocol-selection procedure for the two available serial ports. At the first stage, a certain protocol can be enabled or disabled for a given USART port or the USB port. Selectable protocols are RTCM, NMEA and UBX. At the second stage, messages can be enabled or disabled for each enabled protocol on each port. In all configurations described below, all protocols are enabled on all ports, but output messages are enabled in a way that ports appear to communicate at only one protocol. However, each port will accept any input message in any of the three implemented protocols

ATR0630 [Preliminary]

GPSMODE2

(Reset = PU) Description

Table 3-6. Serial I/O Configuration

USART1/USB

GPSMODE12

(Reset = PU)

0 0 0 UBX/57.6 NMEA/19.2 High User, Notice, Warning, Error 0 0 1 UBX/38.4 NMEA/9.6 Medium User, Notice, Warning, Error 0 1 0 UBX/19.2 NMEA/4.8 Low User, Notice, Warning, Error 0 1 1 –/Auto –/Auto Off None 1 0 0 NMEA/19.2 UBX/57.6 High User, Notice, Warning, Error 1 0 1 NMEA/4.8 UBX/19.2 Low User, Notice, Warning, Error 1 1 0 NMEA/9.6 UBX/38.4 Medium User, Notice, Warning, Error 1 1 1 UBX/115.2 NMEA/19.2 Debug All

GPSMODE6

(Reset = PU)

GPSMODE5

(Reset = PD)

(Output Protocol/ Baud Rate (kBaud))

USART2 (Output Protocol/ Baud Rate (kBaud)) Messages Information Messages

Both USART ports accept input messages in all three supported protocols (NMEA, RTCM and UBX) at the configured baud rate. Input messages of all three protocols can be arbitrarily mixed. Response to a query input message will always use the same protocol as the query input message. The USB port does only accept NMEA and UBX as input protocol by default. RTCM can be enabled via protocol messages on demand.

In Auto mode, no output message is sent out by default, but all input messages are accepted at any supported baud rate. Again, USB is restricted to only NMEA and UBX protocols. Response to query input commands will be given by the same protocol and baud rate as it was used for the query command. Using the respective configuration commands, periodic output messages can be enabled.

4920A–GPS–01/06

Page 14

The following message settings are used in the tables below:

Table 3-7. Supported Messages at Setting Low

NMEA Port Standard GGA, RMC

UBX Port

NAV SOL, SVINFO MON EXCEPT

Table 3-8. Supported Messages at Setting Medium

NMEA Port Standard GGA, RMC, GSA, GSV, GLL, VTG, ZDA

UBX Port NAV

SOL, SVINFO, POSECEF, POSLLH, STATUS, DOP, VELECEF, VELNED, TIMEGPS, TIMEUTC, CLOCK

Table 3-9. Supported Messages at Setting High

NMEA Port

UBX Port

Standard GGA, RMC, GSA, GSV, GLL, VTG, ZDA, GRS, GST Proprietary PUBX00, PUBX03, PUBX04

NAV

MON SCHD, IO, IPC, EXCEPT

SOL, SVINFO, POSECEF, POSLLH, STATUS, DOP, VELECEF, VELNED, TIMEGPS, TIMEUTC, CLOCK

Table 3-10. Supported Messages at Setting Debug (Additional Undocumented Message May

be Part of Output Data)

NMEA Port

UBX Port

Standard GGA, RMC, GSA, GSV, GLL, VTG, ZDA, GRS, GST Proprietary PUBX00, PUBX03, PUBX04

NAV

MON SCHD, IO, IPC, EXCEPT RXM RAW (RAW message support requires an additional license)

SOL, SVINFO, POSECEF, POSLLH, STATUS, DOP, VELECEF, VELNED, TIMEGPS, TIMEUTC, CLOCK

The following settings apply if GPSMODE configuration is not enabled, that is, GPSMODE = 0 (ROM defaults):

Table 3-11. Serial I/O Default Setting if GPSMODE Configuration is Deselected

(GPSMODE0 = 0)

USART1/USB

Setting

Baud rate (kBaud) 57.6, Auto enabled 57.6, Auto enabled Input protocol UBX, NMEA, RTCM UBX, NMEA, RTCM Output protocol NMEA UBX

Messages GGA, RMC, GSA, GSV

Information messages (UBX INF or NMEA TXT)

NMEA

User, Notice, Warning, Error User, Notice, Warning, Error

USART2 UBX

NAV: SOL, SVINFO MON: EXCEPT

ATR0630 [Preliminary]

4920A–GPS–01/06

Page 15

3.4.1 USB Power Mode

For correct response to the USB host queries, the device has to know its power mode. This is configured via GPSMODE7. If set to bus powered, an upper current limit of 100 mA is reported to the USB host; that is, the device classifies itself as a “low-power bus-powered function” with no more than one USB power unit load.

Table 3-12. USB Power Modes

GPSMODE7 (Reset = PU) Description

3.4.2 Active Antenna Supervisor

The two pins P0/NANTSHORT and P15/ANTON plus one pin of P25/NAADET0/MISO or P14/NAADET1 are always initialized as general purpose I/Os and used as follows:

• P15/ANTON is an output which can be used to switch on and off antenna power supply.

• Input P0/NANTSHORT will indicate an antenna short circuit, i.e. zero DC voltage at the antenna, to the firmware. If the antenna is switched off by output P15/ANTON, it is assumed that also input P0/NANTSHORT will signal zero DC voltage, i.e. switch to its active low state.

• Input P25/NAADET0/MISO or P14/NAADET1 will indicate a DC current into the antenna. In case of short circuit, both P0 and P25/P14 will be active, i.e. at low level. If the antenna is switched off by output P15/ANTON, it is assumed that also input P25/NAADET0/MISO will signal zero DC current, i.e. switch to its active low state. Which pin is used as NAADET (P14 or P25) depends on the settings of GPSMODE11 and GPSMODE10 (see Table 3-14 on

page 16).

ATR0630 [Preliminary]

0 USB device is bus-powered (maximum current limit 100 mA) 1 USB device is self-powered (default ROM value)

Table 3-13. Pin Usage of Active Antenna Supervisor

Pin Usage Meaning

Active antenna short circuit detection

P0/NANTSHORT NANTSHORT

P25/NAADET0/ MISO or P14/NAADET1

P15/ANTON ANTON

NAADET

High = No antenna DC short circuit present Low = Antenna DC short circuit present

Active antenna detection input High = No active antenna present Low = Active antenna is present

Active antenna power on output High = Power supply to active antenna is switched on Low = Power supply to active antenna is switched off

4920A–GPS–01/06

Page 16

Table 3-14. Antenna Detection I/O Settings

GPSMODE11

(Reset = PU)

0 0 0 P25/NAADET0/MISO 0 0 1 P25/NAADET0/MISO

0 1 0 P14/NAADET1

011

1 0 0 P14/NAADET1

1 0 1 P14/NAADET1

1 1 0 P25/NAADET0/MISO 1 1 1 P25/NAADET0/MISO

GPSMODE10

(Reset = PU)

GPSMODE8

(Reset = PU) Location of NAADET Comment

Reserved for further use. Do not use this setting.

P14/NAADET1 (Default ROM value)

Reserved for further use. Do not use this setting.

The Antenna Supervisor Software will be configured as follows:

1. Enable Control Signal

2. Enable Short Circuit Detection (power down antenna via ANTON if short is detected via

NANTSHORT)

3. Enable Open Circuit Detection via NAADET

The antenna supervisor function may not be disabled by GPSMODE pin selection.

ATR0630 [Preliminary]

4920A–GPS–01/06

Page 17

3.4.3 External Connections for a Working GPS System

Figure 3-2. Example of an External Connection (ATR0630)

ATR0630 [Preliminary]

ATR0630

LNA

(optional)

ATR0610

SAW

see Table 3-15 see Table 3-15 see Table 3-15 see Table 3-15 see Table 3-15 see Table 3-15 P29 - 30

GND analog

NC NC CLK23

NC NC NC NC NC NC NC

NC NC

SIGHI SIGLO

RF NRF

RF_ON PURF NSLEEP PUXTO

NRESET TMS TCK TDI NTRST TDO DBG_EN

P0 - 2 P9 P12 - 17 P19 P23 - 27

P30/AGCOUT0 SDI

MO TEST EGC

XT_IN

XT_OUT

XTO

NXTO

P20

USB_DM

USB_DP

P31 P18

P22 P21

32.768 kHz (see RTC)

23.104 MHz (see GPS crystal)

STATUS LED TIMEPULSE

Optional

USB

Optional

USART 1

Optional

USART 2

+3V (see Power Supply)

4920A–GPS–01/06

GND

(see Power Supply)

NC: Not connected

GND digital GND analog

+3V

AGCO

GNDD GNDA

NSHDN LDO_EN

LDO_OUT VDD18 VDIG

LDO_IN LDOBAT_IN

VBAT18

VBAT

VDDIO

VDD_USB

VCC1 VCC2

VBP

+3V (see Power Supply)

Page 18

Table 3-15. Recommended Pin Connections

Pin Name Recommended External Circuit

P0/NANTSHORT

P1/GPSMODE0

P2/BOOT_MODE Internal pull-down resistor; leave open.

P8/STATUSLED

P9/EXTINT0 Internal pull-up resistor; leave open if unused.

P12/GPSMODE2/NPCS2

P13/GPSMODE3/ EXTINT1

P14/NAADET1

P15/ANTON

P16/NEEPROM Internal pull-up resistor; leave open if no serial EEPROM is connected. Otherwise connect to GND.

P17/GPSMODE5/SCK1

P18/TXD1 Output in default ROM firmware: leave open if serial interface is not used.

P19/GPSMODE6/SIGLO1

P20/TIMEPULSE/SCK2 Output in default ROM firmware: leave open if time pulse feature is not used. P21/TXD2 Output in default ROM firmware: leave open if serial interface not used. P22/RXD2 Internal pull-up resistor; leave open if serial interface is not used.

P23/GPSMODE7/SCK

P24/GPSMODE8/MOSI

P25/NAADET0/MISO

P26/GPSMODE10/NSS/ NPCS0

P27/GPSMODE11/NPCS1

P29/GPSMODE12/NPCS3

P30/AGCOUT0 Internal pull-down resistor; leave open. P31/RXD1 Internal pull-up resistor; leave open if serial interface is not used.

Internal pull-down resistor; leave open if Antenna Supervision functionality is unused. Can be left open if configured as output by user application.

Internal pull-down resistor; leave open in order to disable the GPSMODE pin configuration feature. Connect to VDDIO to enable the GPSMODE pin configuration feature. Refer to GPSMODE definitions in “Setting

GPSMODE0 to GPSMODE12” on page 12. Can be left open if configured as output by user application.

Output in default ROM firmware: leave open, only needs pull-up resistor to VDDIO or pull-down resistor to GND if used as GPIO input by user application and if not always driven from external sources.

Internal pull-up resistor; can be left open if the GPSMODE feature is not used or if configured as output by user application. Refer to GPSMODE definitions in “Setting GPSMODE0 to GPSMODE12” on page 12.

Internal pull-down resistor; leave open if Antenna Supervision functionality is unused. Can be left open if configured as output by user application.

Internal pull-down resistor; can be left open if the GPSMODE feature is not used or if configured as output by user application. Refer to GPSMODE definitions in “Setting GPSMODE0 to GPSMODE12” on page 12.

Internal pull-down resistor; leave open if Antenna Supervision functionality is unused. Can be left open if configured as output by user application.

ATR0630 [Preliminary]

4920A–GPS–01/06

Page 19

3.5 Connecting an Optional Serial EEPROM

The ATR0630 offers the possibility of connecting an external serial EEPROM. The internal ROM firmware supports storing the configuration of the ATR0630 in serial EEPROM. The pin P16/NEEPROM signals the firmware that a serial EEPROM is connected to the ATR0630. The ATR0630’s 32-bit RISC processor accesses the external memory via SPI (serial peripheral interface). For best results, use a 32-Kbit 1.8V serial EEPROM such as Atmel’s AT25320AY1-1.8.

Figure 3-3 shows an example of the serial EEPROM connection.

Figure 3-3. Example of a Serial EEPROM Connection

ATR0630 [Preliminary]

AT25320AY1-1.8

NC: Not connected

SCK

CS_N

HOLD_N

WP_N

+3V (see Power Supply)

GND

P23/SCK P24/MOSI P25/MISO/NAADET0 P29/NPCS3

P16/NEEPROM P1/GPSMODE0

GND NSHDN LDO_EN LDO_OUT VDD18 VDDIO

LDO_IN LDOBAT_IN

ATR0630

Note: The GPSMODE pin configuration feature can be disabled, because the configuration can be

stored in the serial EEPROM. VDDIO is the supply voltage for the pins: P23, P24, P25 and P29.

4920A–GPS–01/06

Page 20

4. Power Supply

The ATR0630 is supplied with six distinct supply voltages:

• The power supplies for the RF part (VCC1, VCC2, VBP) within 2.7V to 3.3V.

• VDIG, the 1.8V supply of the digital pins of the RF part (SIGHI, SIGLO and CLK23). VDIG should be connected to VDD18.

• VDD18, the nominal 1.8V supply voltage for the core, the I/O pins, the memory interface and the test pins and all GPIO pins not mentioned in next item.

• VDDIO, the variable supply voltage within 1.8V to 3.6V for the following GPIO pins: P1, P2, P8, P12, P14, P16, P17, P18, P19, P20, P21, P23, P24, P25, P26, P27 and P29. In input mode, these pins are 5V input tolerant.

• VDD_USB, the power supply of the USB pins: USB_DM and USB_DP.

• VBAT18 to supply the backup domain: RTC, backup SRAM and the pins NSLEEP, NSHDN, LDO_EN, VBAT18, P9/EXTIN0, P13/EXTINT1, P22/RXD2 and P31/RXD1 and the 32kHz oscillator. In input mode, the four GPIO-pins are 5V input tolerant.

ATR0630 [Preliminary]

4920A–GPS–01/06

Page 21

ATR0630 [Preliminary]

Figure 4-1. Connecting Example: Separate Power Supplies for RF and Digital Part Using the Internal LDOs

ATR0630 internal

2.3V to 3.6V

1.5V to 3.6V

2.7V to 3.3V

1 µF (X7R)

VCC1

VCC2

VBP

VDIG

LDO_IN

LDO_ENNSHDN

LDO_OUT

VDD18

VDDIO

LDOBAT_IN

VBAT

ldoin

ldoen

ldoout

Core

1.8V to 3.3V

variable I/O domain

ldobat_in

vbat

LDOBAT

LDO18

VBAT18

1 µF (X7R)

VDDUSB0V or 3V to 3.6V

vbat18

VDD

RTC

backup memory

USB SM and

transceiver

The ATR0630 contains a built in low dropout voltage regulator LDO18. This regulator can be used if the host system does not provide the core voltage VDD18 of 1.8V nominal. In such case, LDO18 will provide a 1.8V supply voltage from any input voltage VDD between 2.3V and 3.6V. The LDO_EN input can be used to shut down VDD18 if the system is in standby mode.

If the host system does supply a 1.8V core voltage directly, this voltage has to be connected to the VDD18 supply pins of the Core. LDO_EN must be connected to GND. LDO_IN can be connected to GND. LDO_OUT must not be connected.

A second built in low dropout voltage regulator LDOBAT provides the supply voltage for the RTC and backup SRAM from any input voltage VBAT between 1.5V and 3.6V. The backup battery delivers the supply current if LDOBAT_IN is not powered.

4920A–GPS–01/06

Page 22

The RTC section will be initialized properly if VDD18 is supplied first to the ATR0630. If VBAT is applied first, the current consumption of the RTC and backup SRAM is undetermined.

Figure 4-2. Connecting Example: Common Power Supplies for RF and Digital Part Using the Internal LDOs

ATR0630 internal

VCC1

VCC2

VBP

VDIG

2.7V to 3.3V

NSHDN

1.5V to 3.6V

1 µF (X7R)

LDO_IN

LDO_EN

LDO_OUT

VDD18

VDDIO

LDOBAT_IN

VBAT

VBAT18

ldoin

ldoen

ldoout

Core

1.8V to 3.3V

variable IO domain

ldobat_in

vbat

vbat18

RTC

backup memory

LDO18

LDOBAT

VDD

The USB Transceiver is disabled if VDD_USB < 2.0V. In this case the pins USB_DM and USB_DP are connected to GND (internal pull-down resistors). The USB Transceiver is enabled if VDD_USB within 3.0V and 3.6V.

ATR0630 [Preliminary]

VDDUSB0V or 3V to 3.6V

USB SM and

transceiver

4920A–GPS–01/06

Page 23

ATR0630 [Preliminary]

Figure 4-3. Connecting Example: Separate Power Supplies for RF and Digital Part Using 1.8V from Host System

ATR0630 internal

1.65V to 1.95V

2.7V to 3.3V

2.3V to 3.6V

1.5V to 3.6V

1 µF (X7R)

VCC1

VCC2

VBP

VDIG

LDO_IN

LDO_EN

LDO_OUT

VDD18

VDDIO

LDOBAT_IN

VBAT

ldoin

ldoen

ldoout

Core

1.8V to 3.3V

variable I/O domain

ldobat_in

vbat

LDO18

LDOBAT

1 µF (X7R)

VBAT18

VDDUSB0V or 3V to 3.6V

vbat18

VDD

RTC

backup memory

USB SM and

transceiver

4920A–GPS–01/06

Page 24

Figure 4-4. Connecting Example: Power Supply from USB Using the Internal LDOs

VCC1

VCC2

VBP

VDIG

ATR0630 internal

NSHDN

1 µF (X7R)

1.5V to 3.6V

1 µF (X7R)

LDO_IN

LDO_EN

LDO_OUT

VDD18

VDDIO

LDOBAT_IN

VBAT

VBAT18

ldoin

ldoen

ldoout

Core

1.8V to 3.3V

variable I/O domain

ldobat_in

vbat

vbat18

RTC

backup memory

LDO18

LDOBAT

VDD

USB-VSB 5V

External LDO

2.7V to 3.3V

ATR0630 [Preliminary]

VDDUSB

USB SM and

transceiver

4920A–GPS–01/06

Page 25

5. Crystals

5.1 GPS XTAL

ATR0630 [Preliminary]

The ATR0630 only needs a GPS crystal (XTAL), but supports also TCXOs. The reference frequency is 23.104 MHz. By connecting an optional RTC crystal, different power modes are available. The reference frequency is 32.768 kHz.

Figure 5-1. Application Example Using a GPS Crystal with ESR Typically = 12Ω

(See Table 5-1 on page 27)

XTO

NXTO

47 pF

82 pF

47 pF

≠

Figure 5-2. Application Example Using a GPS Crystal With ESR Typically

12Ω

(See Table 5-2 on page 27)

XTO

NXTO

47 pF

82 pF

47 pF

Note: The external series resistor R1 has to be selected depending on the typical value of the crystal

ESR. Refer to the application note “ATR0601: Crystal and TXCO Selection”.

4920A–GPS–01/06

Page 26

Figure 5-3. Equivalent Application Examples Using a GPS TCXO (See Table 5-3 on page 27)

33 pF

XTO

NXTO

TCXO

10 pF

22 pF

Do not connect

XTO

NXTO

TCXO

10 pF

22 pF

Do not connect

33 pF

Figure 5-4. Application Example Using an External Reference Frequency and Balanced

Inputs (See Table 5-4 on page 27)

1:1

Do not connect

XTO

NXTO

ATR0630 [Preliminary]

4920A–GPS–01/06

Page 27

ATR0630 [Preliminary]

Table 5-1. Specification of GPS Crystals Appropriate for the Application Example Shown in

Figure 5-1 on page 25

Parameter Comment Min Typ Max Units Frequency Characteristics

Fundamental frequency

Calibration tolerance Frequency at 23°C ±2°C 7.0 ±ppm Frequency deviation Over operating temperature range 15.0 ±ppm Temperature range Operating temperature range –40.0 +85.0 °C

Electrical

Load capacitance (CL) 18.5 19.5 pF

Equivalent Series Resistance (ESR)

Fundamental Specification 7 12 23 Ω

Table 5-2. Specification of GPS Crystals Appropriate for the Application Example Shown in

Figure 5-2 on page 25

Parameter Comment Min Typ Max Units Equivalent Series Resistance (ESR)

Fundamental Specification 7 40 Ω

Nominal frequency referenced to 25°C

23.104 MHz

Note: All other parameters as specified in Table 5-1.

Table 5-3. Specification of GPS TCXOs Appropriate for the Application Example Shown in

Figure 5-3 on page 26

Parameter Comment Min Typ Max Units Frequency Characteristics

Nominal Frequency

Frequency deviation Over operating temperature range 2.0 ±ppm Temperature range Operating temperature range –40.0 +85.0 °C

Electrical

Output waveform DC coupled clipped sine wave Output voltage

(peak-to-peak) Output load capacitance Tolerable load capacitance 10 pF

Nominal frequency referenced to 25°C

At minimum supply voltage 0.8 V

23.104 MHz

Table 5-4. Specification of an External Reference Signal for the Application Example Shown

in Figure 5-4 on page 26

Parameter Comment Min Typ Max Units Signal Characteristics

Nominal Frequency 23.104 MHz Waveform Sine wave or clipped sine wave Amplitude Voltage peak-to-peak 0.6 0.8 1.0 V

4920A–GPS–01/06

Page 28

5.2 RTC Oscillator

Figure 5-5. Crystal Connection

32.768 kHz 50 ppm

XT_IN

XT_OUT

32 kHz Crystal

Oscillator

ATR0630 internal

32.768 kHz clock

RTC

C = 2 × C

load

, C

can be derived from the crystal datasheet

load

ATR0630 [Preliminary]

4920A–GPS–01/06

Page 29

ATR0630 [Preliminary]

6. Absolute Maximum Ratings

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Parameters Pins Symbol Min Max Unit

Operating temperature T Storage temperature T Analog supply voltage VCC1, VCC2, VBP V Digital supply voltage RF VDIG V DC supply voltage core VDD18 VDD18 –0.3 +1.95 V DC supply voltage VDDIO

domain DC supply voltage USB VDD_USB VDD_USB –0.3 +3.6 V DC supply voltage LDO18 LDO_IN LDO_IN –0.3 +3.6 V DC supply voltage LDOBAT LDOBAT_IN LDOBAT_IN –0.3 +3.6 V DC supply voltage VBAT VBAT VBAT –0.3 +3.6 V

Digital input voltage

Digital input voltage USB_DM, USB_DP –0.3 +3.6 V

Digital input voltage

Note: Minimum/maximum limits are at +25°C ambient temperature, unless otherwise specified.

VDDIO VDDIO –0.3 +3.6 V

P0, P15, P30, XT_IN, TMS, TCK, TDI, NTRST, DBG_EN, LDO_EN, NRESET

P1, P2, P8, P9, P12 to P14, P16 to P27, P29, P31

stg

DIG

–40 +85 °C

–55 +125 °C –0.3 +3.7 V –0.3 +3.7 V

–0.3 +1.95 V

–0.3 +5.0 V

7. Handling

The ATR0630 is an ESD-sensitive device. The current ESD values are to be defined. Observe proper precautions for handling.

4920A–GPS–01/06

Page 30

8. Operating Range

Parameters Pins Symbol Min Typ Max Unit

Analog supply voltage RF VCC1, VCC2, VBP V Digital supply voltage RF VDIG V

DIG

Digital supply voltage core VDD18 VDD18 1.65 1.8 1.95 V Digital supply voltage VDDIO

(1)

domain Digital supply voltage USB

(2)

VDDIO VDDIO 1.65 1.8/3.3 3.6 V

VDD_USB VDD_USB 3.0 3.3 3.6 V DC supply voltage LDO18 LDO_IN LDO_IN 2.3 3.6 V DC supply voltage LDOBAT LDOBAT_IN LDOBAT_IN 2.3 3.6 V DC Supply voltage VBAT VBAT VBAT 1.5 3.6 V Supply voltage difference

= VCC – V

∆

DIG

)

∆

Temperature range Temp –40 +85 °C Input frequency f Reference frequency GPS XTAL f Reference frequency RTC f

XTO

XTC

Notes: 1. VDDIO is the supply voltage for the following GPIO-pins: P1, P2, P8, P12, P14, P16, P17, P18, P19, P20, P21, P23, P24,

P25, P26, P27 and P29

2. Values defined for operating USB Interface. Otherwise VDD_USB may be connected to ground.

2.70 3.30 V

1.65 1.8 1.95 V

≥ 0.80 V

1575.42 MHz

23.104 MHz

32.768 KHz

9. Electrical Characteristics

If no additional information is given in column Test Conditions, the values apply to temperature range from –40°C to +85°C.

No. Parameters Test Conditions Pin Symbol Min Typ Max Unit

1 RF Front-end

1.1 Output frequency f Input impedance

1.2 (balanced)

1.3 Mixer conversion gain C3 G

1.4 Mixer noise figure (SSB) C3 NF

1.5 Maximum total gain V

1.6 Total noise figure (SSB) NF

= 23.104 MHz C3 f

XTO

= 1575.42 MHz D1, C1 Z

= 2.2V G

AGCO

MIX

max_tot

tot

2 VGA/AGC

2.1 Minimum gain V

2.2 Maximum gain V

2.3 Control-voltage sensitivity

= 1.0V G

AGCO

= 2.2V G

AGCO

= 2.2V N

AGCO

= 1.0V N

AGCO

VGA,min

VGA, max

VGA,min

VGA,max

Notes: 1. The LDO18 is a built in low dropout voltage regulator, which can be used if the host system does not provide the core volt-

age VDD18.

2. The LDOBAT is a built in low dropout voltage regulator, which provides the supply voltage VBAT18 for the RTC, backup SRAM, P9, P13, P22, P31, NSLEEP and NSHDN. The LDOBAT voltage regulator switches in battery mode if LDOBAT_IN falls below 1.5V.

3. Supply voltage VBAT18 for backup domain is generated internally by the LDOBAT.

4. If no current is caused by outputs (pad output current as well as current across internal pull-up resistors)

96.764 MHz

10 – j80 Ω

10 dB

6dB

90 dB

6.8 dB

0dB

70 dB

6.6 dB/V

150 dB/V

ATR0630 [Preliminary]

4920A–GPS–01/06

Page 31

ATR0630 [Preliminary]

9. Electrical Characteristics (Continued)

If no additional information is given in column Test Conditions, the values apply to temperature range from –40°C to +85°C.

No. Parameters Test Conditions Pin Symbol Min Typ Max Unit

2.4 AGC cut-off frequency C

2.5 AGC cut-off frequency C Gain-control output

2.6 voltage

3 Reference Oscillator

XTO phase noise at

3.1 100Hz

3.2 XTO phase noise at 1 kHz With specified crystal A8 Pn

4PMSS

4.1 Voltage level power-on F4, G4, H4 V

4.2 Voltage level power-off F4, G4, H4 V

5LDO18

(1)

5.1 Output voltage LDO_OUT 1.65 1.8 1.95 V

5.2 Output current LDO_OUT 80 mA

5.3 Current consumption After startup, no load 80 µA

5.4 Current consumption

6LDOBAT

6.1 Output voltage

(2)

(3)

6.2 Output current VBAT18 1.5 mA

Current consumption

6.3 LDOBAT_IN

Current consumption

6.4 VBAT

(4)

6.5 Current consumption

7Core

7.1 DC supply voltage VDD18 V

7.2 DC supply voltage VDDIO V Low-level input voltage

7.3 VDD18 domain

High-level input voltage

7.4 VDD18 domain

Notes: 1. The LDO18 is a built in low dropout voltage regulator, which can be used if the host system does not provide the core volt-

age VDD18.

3. Supply voltage VBAT18 for backup domain is generated internally by the LDOBAT.

4. If no current is caused by outputs (pad output current as well as current across internal pull-up resistors)

= open A4 f

ext

= 100 pF A4 f

ext

3dB_AGC

A4 V

With specified crystal A8 Pn

Standby mode (LDO_EN = 0)

VBAT18 1.65 1.8 1.95 V

After startup (sleep/backup mode), at room temperature

After startup (backup mode and LDOBAT_IN = 0V), at room temperature

After startup (normal mode), at room temperature

VDD18 = 1.65V to 1.95V V

AGCO

100

PU,on

PU,off

O,18

O,IO

IL,18

IH,18

250 kHz

33 kHz

0.9 2.3 V

–80 dBc/Hz

–100 dBc/Hz

1.3 V

0.5 V

15µA

15 µA

10 µA

1.5 µA

0 VDD18 V 0 VDDIO V

–0.3

0.7 ×

VDD18

0.3 ×

VDD18

VDD18 +

0.3

4920A–GPS–01/06

Page 32

9. Electrical Characteristics (Continued)

If no additional information is given in column Test Conditions, the values apply to temperature range from –40°C to +85°C.

No. Parameters Test Conditions Pin Symbol Min Typ Max Unit

Low-level input voltage

7.5 VDDIO domain

High-level input voltage

7.6 VDDIO domain

Low-level input voltage

7.7 VBAT18 domain

High-level input voltage

7.8 VBAT18 domain

Low-level input voltage

7.9 USB

High-level input voltage

7.10 USB

Low-level output voltage

7.11 VDD18 domain

High-level output voltage

7.12 VDD18 domain

Low-level output voltage

7.13 VDDIO domain

High-level output voltage

7.14 VDDIO domain

Low-level output voltage

7.15 VBAT18 domain

High-level output voltage

7.16 VBAT18 domain

Low-level output voltage

7.17 USB

High-level output voltage

7.18 USB

Input-leakage current

7.19 (standard inputs and I/Os)

7.20 Input capacitance I Input pull-up resistor

7.21 NRESET

Input pull-up resistors

7.22 TCK, TDI, TMS

Input pull-up resistors P9,

7.23 P13, P22, P31

Notes: 1. The LDO18 is a built in low dropout voltage regulator, which can be used if the host system does not provide the core volt-

age VDD18.

3. Supply voltage VBAT18 for backup domain is generated internally by the LDOBAT.

4. If no current is caused by outputs (pad output current as well as current across internal pull-up resistors)

VDDIO = 1.65V to 3.6V V

VBAT18 = 1.65V to 1.95V

A11, B10, C10, D10

VDD_USB = 3.0V to 3.6V C9, D9 V

IOL = 1.5 mA, VDD18 = 1.65V

IOH = –1.5 mA, VDD18 = 1.65V

= 1.5 mA,

VDDIO = 3.0V IOH = –1.5 mA,

VDDIO = 3.0V

IOL = 1 mA

= –1 mA

P9, P13,

P22, P31

P9, P13,

P22, P31

IOL = 2.2 mA, VDD_USB = 3.0V to 3.6V,

DP, DM V

27Ω external series resistor

= 0.2 mA,

VDD_USB = 3.0V to 3.6V,

DP, DM V

OH,USB

27Ω external series resistor VDD18 = 1.95V

= 0V

–40°C to +85°C A7 R

–40°C to +85°C

G9, H10,

G10

A11, B10, C10, D10

IL,IO

IH,IO

IL,BAT

IH,BAT

IL,USB

IH,USB

OL,18

OH,18

OL,IO

OH,IO

OL,BAT

OH,BAT

OL,USB

LEAK

CAP

–0.3 +0.41 V

1.46 5.0 V

–0.3 +0.41 V

1.46 5.0 V

–0.3 +0.8 V

2.0 3.6 V

0.4 V

VDD18 –

0.45

0.4 V

VDDIO –

0.5

0.4 V

1.2 V

0.3 V

2.8 V

–1 +1 µA

10 pF

0.7 1.8 kΩ

718kΩ

100 235 kΩ

ATR0630 [Preliminary]

4920A–GPS–01/06

Page 33

ATR0630 [Preliminary]

9. Electrical Characteristics (Continued)

If no additional information is given in column Test Conditions, the values apply to temperature range from –40°C to +85°C.

No. Parameters Test Conditions Pin Symbol Min Typ Max Unit

Input pull-down resistors

7.24 DBG_EN, NTRST, RF_ON

Input pull-down resistors

7.25 P0, P15, P30

Configurable input pull-up resistors P1, P2, P8, P12,

7.26 P14, P16 to P21, P23 to

P27, P29 Configurable input

pull-down resistors P1, P2,

7.27 P8, P12, P14, P16 to P21,

P23 to P27, P29 Configurable input pull-up

7.28

resistor USB_DP (idle state)

Configurable input pull-up

7.29

resistor USP_DP (operation state)

Input pull-down resistors

7.30 USB_DP, USB_DM

Notes: 1. The LDO18 is a built in low dropout voltage regulator, which can be used if the host system does not provide the core volt-

age VDD18.

3. Supply voltage VBAT18 for backup domain is generated internally by the LDOBAT.

4. If no current is caused by outputs (pad output current as well as current across internal pull-up resistors)

–40°C to +85°C E8, H11 R

–40°C to +85°C

F10, C8,

F11, G12

–40°C to +85°C R

–40°C to +85°C C9 R

–40°C to +85°C C9, D9 R

CPU

CPD

CPU

718kΩ

100 235 kΩ

62 330 kΩ

45 160 kΩ

0.9 1.575 kΩ

1.425 3.09 kΩ

10 500 kΩ

10. Power Consumption

Mode Conditions Typ Unit

Sleep At 1.8V, no CLK23 0.065 Shutdown RTC, backup SRAM and LDOBAT 0.007

Satellite acquisition 40

Normal

Normal tracking on 6 channels with 1 fix/s; each additional active tracking channel adds 0.5 mA 29 All channels disabled 26

Note: 1. Specified value only

4920A–GPS–01/06

(1)

Page 34

11. Ordering Information

Extended Type Number Package MPQ Remarks

ATR0630-7KQY BGA96 2000

ATR0630-EK1 - 1 Evaluation kit/Road test kit

ATR0630-DK1 - 1

7 mm × 10 mm, 0.8 mm pitch, Pb-free, RoHS-compliant

Design kit including design guide and PCB Gerber files

12. Package Information

Package: ATR0630

Dimensions in mm

A1 Corner

Top View

1234

A B C D E

5 6 7 8 9 10 11 12 12 11 10 456789321

Pin A1 Laser Marking

technical drawings according to DIN specifications

7±0.05

5.6

0.08

0.15

n m

0.8

0.08 C

Bottom View

8.8

10±0.05

0.4±0.05

0.1C

A1 Corner

A B C D E

F G H

0.8

0.75±0.05

Drawing-No.: 6.580-5005.01-4 Issue: prel. copy; 02.03.05

0.3±0.05

1.4 max

Note:

1. All dimensions and tolerance conform to ASME Y 14.5M-1994 Dimension is measured at the maximum solder ball diameter, parallel to primary datum

2. Primary datum and seating plane are defined by the spherical crowns of the solder balls

4. The surface finish of the package shall be EDM CHARMILLE #24 - #27

5. Unless otherwise specified tolerance: Decimal ±0.05, Angular ±2

5. Raw ball diameter: 0.4 mm ref.

ATR0630 [Preliminary]

Seating plane

±0.04

0.26

4920A–GPS–01/06

Page 35

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4920A–GPS–01/06